JPS5455172A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5455172A
JPS5455172A JP12151577A JP12151577A JPS5455172A JP S5455172 A JPS5455172 A JP S5455172A JP 12151577 A JP12151577 A JP 12151577A JP 12151577 A JP12151577 A JP 12151577A JP S5455172 A JPS5455172 A JP S5455172A
Authority
JP
Japan
Prior art keywords
package
base floor
semiconductor element
heat
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12151577A
Other languages
Japanese (ja)
Inventor
Shinichi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12151577A priority Critical patent/JPS5455172A/en
Publication of JPS5455172A publication Critical patent/JPS5455172A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the need for the use of heat sink, reduce the size of element disposition base floor part and lower cost by providing a notched part to part of a resin-made package enclosing the semiconductor element and beforehand packing heat conductive resin therein. CONSTITUTION:A semiconductor element 1 is secured onto a semiconductor element disposition base floor part 14 and the electrodes of the element are connected to deriving leads 2, 2' via bonding wires 3, 3'. Thereafter, the element 1 is enclosed with a package 15 composed of epoxy resin or other, with the leads 2, 2' being projected to the outside. At this time, a notched part 16 is beforehand formed on the back of the base floor part 14 of the package 15 and the epoxy resin 17 which has been increased in heat conductivity by mixing fine silver particles is packed therein. Then, the heat radiation from the element is made better and the need for costly heat sink is eliminated.
JP12151577A 1977-10-12 1977-10-12 Semiconductor device Pending JPS5455172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12151577A JPS5455172A (en) 1977-10-12 1977-10-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12151577A JPS5455172A (en) 1977-10-12 1977-10-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5455172A true JPS5455172A (en) 1979-05-02

Family

ID=14813108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12151577A Pending JPS5455172A (en) 1977-10-12 1977-10-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5455172A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6287448U (en) * 1985-11-19 1987-06-04
JPH08288428A (en) * 1995-04-20 1996-11-01 Nec Corp Resin-sealed semiconductor device
FR2968126A1 (en) * 2010-11-29 2012-06-01 St Microelectronics Grenoble 2 THERMAL VIA SEMICONDUCTOR HOUSING AND METHOD OF MANUFACTURING
WO2016006193A1 (en) * 2014-07-11 2016-01-14 株式会社デンソー Mold package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6287448U (en) * 1985-11-19 1987-06-04
JPH08288428A (en) * 1995-04-20 1996-11-01 Nec Corp Resin-sealed semiconductor device
FR2968126A1 (en) * 2010-11-29 2012-06-01 St Microelectronics Grenoble 2 THERMAL VIA SEMICONDUCTOR HOUSING AND METHOD OF MANUFACTURING
WO2016006193A1 (en) * 2014-07-11 2016-01-14 株式会社デンソー Mold package

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