JPS5242371A - Multi-chip packaged semiconductor device - Google Patents

Multi-chip packaged semiconductor device

Info

Publication number
JPS5242371A
JPS5242371A JP50117694A JP11769475A JPS5242371A JP S5242371 A JPS5242371 A JP S5242371A JP 50117694 A JP50117694 A JP 50117694A JP 11769475 A JP11769475 A JP 11769475A JP S5242371 A JPS5242371 A JP S5242371A
Authority
JP
Japan
Prior art keywords
semiconductor device
packaged semiconductor
chip packaged
chip
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50117694A
Other languages
Japanese (ja)
Inventor
Wataru Nozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50117694A priority Critical patent/JPS5242371A/en
Publication of JPS5242371A publication Critical patent/JPS5242371A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To package LSIs at high density by connection by means of wire bonding and through-holes.
JP50117694A 1975-10-01 1975-10-01 Multi-chip packaged semiconductor device Pending JPS5242371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50117694A JPS5242371A (en) 1975-10-01 1975-10-01 Multi-chip packaged semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50117694A JPS5242371A (en) 1975-10-01 1975-10-01 Multi-chip packaged semiconductor device

Publications (1)

Publication Number Publication Date
JPS5242371A true JPS5242371A (en) 1977-04-01

Family

ID=14717974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50117694A Pending JPS5242371A (en) 1975-10-01 1975-10-01 Multi-chip packaged semiconductor device

Country Status (1)

Country Link
JP (1) JPS5242371A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446477A (en) * 1981-08-21 1984-05-01 Sperry Corporation Multichip thin film module
US5166773A (en) * 1989-07-03 1992-11-24 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
US5209390A (en) * 1989-07-03 1993-05-11 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446477A (en) * 1981-08-21 1984-05-01 Sperry Corporation Multichip thin film module
US5166773A (en) * 1989-07-03 1992-11-24 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
US5209390A (en) * 1989-07-03 1993-05-11 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid

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