JPS6084845A - Sealed semiconductor device - Google Patents

Sealed semiconductor device

Info

Publication number
JPS6084845A
JPS6084845A JP58193174A JP19317483A JPS6084845A JP S6084845 A JPS6084845 A JP S6084845A JP 58193174 A JP58193174 A JP 58193174A JP 19317483 A JP19317483 A JP 19317483A JP S6084845 A JPS6084845 A JP S6084845A
Authority
JP
Japan
Prior art keywords
semiconductor device
recess
sealed
resin
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58193174A
Other languages
Japanese (ja)
Inventor
Taro Fukui
太郎 福井
Shinobu Ikeno
池野　忍
Tsuyoshi Imazu
今津　強
Hideo Kawamura
英雄 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP58193174A priority Critical patent/JPS6084845A/en
Publication of JPS6084845A publication Critical patent/JPS6084845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain the titled device of a low cost and high reliability which can prevent the stress due to the expansion and shrinkage of resin and the infiltration of moisture and is excellent in the property of heat dissipation by a method wherein a metallic substrate is bonded to the contact of a flat circuit by soldering or thermal welding, and a semiconductor element is hermetically sealed with the metallic substrate. CONSTITUTION:The metallic substrate 1 having a recess 1a has a Cu foil 2 formed in a circuit pattern on the surface and consists of a metallic layer 1b and an insulation layer 1c. The recess is provided with a diebonding part 3, and the bonding part 2a of a Cu foil current 2 faces to this recess. The semiconductor element 4 is fixed by adhesion to this part 3, and this element is bonded to the part 2a with wires 5. The element, wires, and part 2a are buffer-coated with a soft resin 6 such as silicone rubber or silicone gel. In the device using such a semiconductor chip A, the chip is placed by inversion on the flat substrate 7 having the Cu circuit pattern 2', the contact-conduction part 8 of the substrate 1 is bonded by soldering or thermal welding.

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、能動電子部品（半導体、ＩＣ，ＬＳｌ）の
樹脂封止構造を改善した封止半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a sealed semiconductor device with an improved resin-sealed structure for active electronic components (semiconductors, ICs, LSIs).

〔背景技術〕[Background technology]

トランジスタ、ＩＣ，ＬＳＩなどの半導体素子に対して
は、温度・湿度などの外部環境から保護し、機械的な振
動・衝撃などによる破損やデバイス特性の変化を防止す
るため、金属・セラミックを用いる気密封止か、エポキ
シ樹脂やシリコン樹脂を用いる樹脂封止が行なわれてい
る。封止の信頼性では、水を全く通さない気密封止が優
れているが、量産性に冨みかつ安価であるという点から
、現在では約８０％程度の素子が樹脂封止されている。Metals and ceramics are often used to protect semiconductor devices such as transistors, ICs, and LSIs from external environments such as temperature and humidity, and to prevent damage and changes in device characteristics due to mechanical vibrations and shocks. Hermetic sealing or resin sealing using epoxy resin or silicone resin is performed. In terms of sealing reliability, hermetic sealing, which does not allow any water to pass through, is superior, but at present, about 80% of the elements are sealed with resin because it is suitable for mass production and is inexpensive.

樹脂を用いる封止法としては、■粉体樹脂を熔解し、圧
力によって金型に注入し封止する低圧トランスファー成
形法、■ボッティング、キャスティングと呼ばれる注型
法および■冷間成形されたＢステージ状樹脂りブレツト
を加熱溶融する方法が知られているが、量産性に優れて
いることから、殆どの半導体素子は■の低圧トランスフ
ァー成形方式で封止されている。Sealing methods using resin include: - low-pressure transfer molding in which powdered resin is melted and injected into a mold under pressure for sealing, - casting methods called botting and casting, and - cold molded B. A method of heating and melting a stage-shaped resin bullet is known, but most semiconductor devices are encapsulated by the low-pressure transfer molding method (2) because it is easy to mass-produce.

この低圧トランスファー成形方式で封止された半導体素
子では、■樹脂の硬化収縮応力や温度サイクルによる膨
張収縮応力などの外力が半導体素子やボンディング部に
かかるため、素子やバツシヘーション膜にクラックが入
る、■湿気が樹脂ノ１ルクおよびリード線と朴１脂の界
面を通って拡散しへｌ配線を腐食する、などの問題があ
るほか、■金型の値段が高い、■金型と完成品との離型
が悪い、■ランナ一部分において樹脂のロスが発生ずる
、などの改善すべき課題をもっている。In semiconductor devices encapsulated using this low-pressure transfer molding method, external forces such as curing and contraction stress of the resin and expansion and contraction stress due to temperature cycles are applied to the semiconductor device and the bonding area, resulting in cracks in the device and the sealing film. In addition to problems such as moisture diffusing through the resin glue and the interface between the lead wire and the resin and corroding the wiring, there are also problems such as high mold costs, and poor contact between the mold and the finished product. There are issues that need to be improved, such as poor mold release and resin loss in some parts of the runner.

一方、注型法や樹脂タブレツ１−を加熱溶融する方法は
■〜■の問題はなく、ハイブリット川Ｃやチップオンボ
ードの素子封止に用いられているが、樹脂封止に伴う前
記■、■の問題を有している状況は変わらない。On the other hand, the casting method and the method of heating and melting the resin tablet 1- do not have the problems of ■ to ■ and are used for encapsulating hybrid Kawa C and chip-on-board devices, but the above-mentioned problems associated with resin sealing ■The situation with the problem remains unchanged.

また、パワートランジスタ、パワーＩＣには数Ｗから数
十Ｗと消費電力の大きい素子が使用されているが、近年
、高集積化技術の著しい進歩により、メモリ素子の領域
においてもＩＷ程度の素子が開発されている。そこで、
素子動作時の発熱による温度上昇を低減させるために、
熱放散効果の高い封止設計が重要な課題となっている。In addition, power transistors and power ICs use elements with large power consumption ranging from several watts to several tens of watts, but in recent years, due to significant advances in high-integration technology, elements on the order of IW have become available even in the area of memory elements. being developed. Therefore,
In order to reduce the temperature rise due to heat generation during element operation,
A sealing design with high heat dissipation efficiency has become an important issue.

放熱性を良くする方法としては、封止樹脂に熱電導率の
良い充填材を添加する方法があるが、充填材の混入量に
限りがあるうえ、低応力化など力学的性質上マイナスの
影響がでてくるといった問題がある〔発明の目的〕 この発明は、従来の樹脂封止の欠点であった樹脂の膨張
・収縮による応力や湿気の侵入を防ぐことができ、熱放
散性に優れた安価で信頼性の高い封止半導体装置を提供
することを目的とする。One way to improve heat dissipation is to add a filler with good thermal conductivity to the sealing resin, but there is a limit to the amount of filler that can be mixed in, and it has negative effects on mechanical properties such as reducing stress. [Objective of the Invention] This invention prevents the intrusion of stress and moisture caused by the expansion and contraction of the resin, which were the drawbacks of conventional resin sealing, and has excellent heat dissipation properties. The purpose is to provide an inexpensive and highly reliable sealed semiconductor device.

〔発明の開示〕[Disclosure of the invention]

上記目的を達成するために、この発明はつぎのように構
成されている。すなわち、表面に回路パターンを有する
金属基板に凹みが形成されていて、ダイボンド部と回路
のボンディング部がこの凹み内に配設され、前記ダイボ
ンド部に固定された半導体素子がワイヤで前記ポンチ９
イング部と結合されてなる半導体チップが、回路パター
ンを有する平らな基板上に反転載置され、金属基板と回
路基板の接触導電部分が接合されているのである。In order to achieve the above object, the present invention is configured as follows. That is, a recess is formed in a metal substrate having a circuit pattern on the surface, a die bonding part and a circuit bonding part are disposed in this recess, and a semiconductor element fixed to the die bonding part is connected to the punch 9 with a wire.
The semiconductor chip, which is connected to the connecting part, is placed upside down on a flat substrate having a circuit pattern, and the contact conductive parts of the metal substrate and the circuit board are bonded.

以下にこれを、その実施例をあられす図面に基づいて詳
しく述べる。This will be described in detail below with reference to the accompanying drawings.

第１．２図は、この発明にがかる封止半導体装置の一実
施例を示すもので、第１図は、かかる封止半導体装置の
一部を構成する半導体チップＡであり、凹み１ａを有す
る金属基板１は、表面に銅箔２が回路パターン状に形成
されていて、金属層ｌｂと絶縁層ＩＣからなる。凹みｌ
ａにはダイボンド部３が配設され、銅箔回路２のボンデ
ィング部２ａもこの凹みｌａに臨んでいる。ダイホント
部３には半導体素子４が接着固定され、この半導体素子
とボンディング部２ａとはワイヤ５で結合されている。FIG. 1.2 shows an embodiment of a sealed semiconductor device according to the present invention, and FIG. 1 shows a semiconductor chip A forming a part of the sealed semiconductor device, which has a recess 1a. The metal substrate 1 has a copper foil 2 formed in a circuit pattern on its surface, and is composed of a metal layer lb and an insulating layer IC. dent l
A die bonding portion 3 is disposed in a, and a bonding portion 2a of the copper foil circuit 2 also faces this recess la. A semiconductor element 4 is adhesively fixed to the die bonnet part 3, and this semiconductor element and the bonding part 2a are connected by wires 5.

半導体素子４．ワイヤ５およびボンディング部２ａは、
シリコンゴムあるいはシリコンゲルなどの柔らかい樹脂
６でバツファーコ−１・されている。第２図は、第１図
の半導体チップＡを用いた封止半導体装置であり、銅回
路パターン２′を有する平らな基板７上に半導体チップ
Ａが反転載置され、金属基板ｌと回路基板７との接触導
電部分８がハンダあるいは熱溶着により接合されている
。Semiconductor element 4. The wire 5 and the bonding part 2a are
It is buffer coated with a soft resin such as silicone rubber or silicone gel. 2 shows a sealed semiconductor device using the semiconductor chip A of FIG. 1, in which the semiconductor chip A is placed inverted on a flat substrate 7 having a copper circuit pattern 2', and a metal substrate A contact conductive portion 8 with 7 is joined by soldering or thermal welding.

第３．４図は、別の実施例を示すもので、第３図は、金
属基板１の凹み１ａ全体にエポキシ樹脂６′が充填され
ている半導体チップＢである。第４図は、第３図の半導
体チップＢを用いた封止半導体装置であり、第２図と同
様に、銅回路パターン２′を有する平らな基板７上に半
導体チップＢが反転載置され、金属基板１と回路基板７
との接触導電部分８がハンダあるいは熱溶着により接合
されている。第３．４図中、第１，２図と同一の符号部
分は同一部分をあられす。3.4 shows another embodiment, and FIG. 3 shows a semiconductor chip B in which the entire recess 1a of the metal substrate 1 is filled with epoxy resin 6'. FIG. 4 shows a sealed semiconductor device using the semiconductor chip B of FIG. 3, in which the semiconductor chip B is placed inverted on a flat substrate 7 having a copper circuit pattern 2', similar to FIG. , metal substrate 1 and circuit board 7
The contact conductive portion 8 is joined by soldering or thermal welding. In Figure 3.4, the same reference numerals as in Figures 1 and 2 refer to the same parts.

第５図および第６図はこの発明にかかる封止半導体装置
の表面電路の引出し構造を示す。第５図の場合は、平ら
な回路基板７上の表面電路部２′に電路引出しのための
リード脚９が取り付けられている。第６図の場合は、封
止半導体装置の平らな回路基板７上の表面電路部２′に
、周囲に導通部１０が形成されたスルーボール孔１１が
設けられ、表面電路部２′はこの孔を通して裏面の下部
電極へと導通されるようになっている。FIGS. 5 and 6 show a structure for drawing out surface electric circuits of a sealed semiconductor device according to the present invention. In the case of FIG. 5, lead legs 9 for drawing out the electric circuit are attached to the surface electric circuit section 2' on the flat circuit board 7. In the case of FIG. 6, a through ball hole 11 with a conductive part 10 formed around it is provided in a surface electric circuit section 2' on a flat circuit board 7 of a sealed semiconductor device. Electricity is established through the hole to the lower electrode on the back surface.

〔発明の効果〕〔Effect of the invention〕

上にみたように、この発明の封止半導体装置では、金属
基板と平らな回路基板の接触部がハンダあるいは熱溶着
により接・合されていて、半導体素子が金属基板により
実質上気密封止されることになり、湿気の侵入を防ぐこ
とができる。素子やボンディング部は金属基板に担持さ
れた上から１剥脂封止されているため、素子やワイヤに
樹脂の膨張・収縮応力がかからない。また、半導体素子
が金属基板に直接接合されていＣ１かつこの金属基板が
外部に対向した構造を有しているため、放熱性に優れて
いるという利点がある。さらに、凹み部にマウントされ
た半導体素子に樹脂封止（バッファーコートを含む）が
なされるので、加熱硬化時に樹脂が流れ出ずのを防止す
るための枠体が不要である。As seen above, in the sealed semiconductor device of the present invention, the contact portion between the metal substrate and the flat circuit board is joined by soldering or thermal welding, and the semiconductor element is substantially hermetically sealed by the metal substrate. This will prevent moisture from entering. Since the elements and bonding parts are supported on the metal substrate and sealed with a single layer of adhesive, no expansion or contraction stress of the resin is applied to the elements or wires. Further, since the semiconductor element is directly bonded to the metal substrate C1 and the metal substrate faces the outside, there is an advantage that heat dissipation is excellent. Furthermore, since the semiconductor element mounted in the recess is sealed with resin (including a buffer coat), there is no need for a frame to prevent the resin from flowing out during heat curing.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第６図はこの発明の実施例を示すもので、第
１．　３図は半導体チップの断面図、第２．４図は封止
半導体装置の断面図、第５図および第６図は表面電路部
の引出し構造を示すＷ１面図である。 ■・・・金属基板　１ａ・・・凹み　１ｂ・・・金属層
１ｃ・・・絶縁層　２．２′・・・銅回路パターン　２
ａ・・・ボンディング部　３・・・ダイボンド部　４・
・・半導体素子　５・・・ボンディングワイヤ　６・・
・バッファーコート　６′・・・エポキシ樹脂　７・・
・回路基板８・・・両回路接触導電部分　９・・・リー
ド脚　１ｏ・・・導通部　１１・・・スルーホール孔　
Ａ、Ｂ川［１チツプ 代理人　弁理士　松　本　武　彦 第５図　第６図 第３図 第４図1 to 6 show embodiments of the present invention. 3 is a sectional view of the semiconductor chip, FIGS. 2.4 are sectional views of the sealed semiconductor device, and FIGS. 5 and 6 are W1 side views showing the lead-out structure of the surface electric circuit section. ■... Metal substrate 1a... Recess 1b... Metal layer 1c... Insulating layer 2.2'... Copper circuit pattern 2
a... Bonding part 3... Die bonding part 4.
...Semiconductor element 5...Bonding wire 6...
・Buffer coat 6'...Epoxy resin 7...
・Circuit board 8...Conductive part that contacts both circuits 9...Lead leg 1o...Conducting part 11...Through hole hole
A, B River [1 Chip Agent Patent Attorney Takehiko Matsumoto Figure 5 Figure 6 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 （ｌ）　表面に回路パターンを有する金属基板に凹みが
形成されていて、グイボンド部と回路のボンディング部
がこの凹み内に配設され、前記グイボンド部に固定され
た半導体素子がワイヤで前記ボンディング部と結合され
てなる半導体チップが、回路パターンを有する平らな基
板上に反転載置され、金属基板と回路基板の接触導電部
分が接合されている封止半導体装置。 （２）　半導体チップが、柔らかい樹脂でバッファーコ
ートされている特許請求の範囲第１項記載の封止半導体
装置。 （３）　半導体チップが、金属基板の凹み全体に充填さ
れているエポキシ樹脂により封止されている特許請求の
範囲第１項記載の封止半導体装置。 （４）　平らな回路基板上の表面電路部に電路引出しの
ためのリード脚が取り付けられている特許請求の範囲第
１項から第３項までのいずれかに記載の封止半導体装置
。 （５）平らな回路基板上の表面電路部に電路引出しのた
めの、周囲に導通部の形成されたスルーポール孔が設け
られていて、表面電路部はこの孔を通して裏面の下部電
極に導通されるようになっている特許請求の範囲第１項
から第３項までのいずれかに記載の封止半導体装置。[Scope of Claims] (l) A recess is formed in a metal substrate having a circuit pattern on the surface, a bonding portion for a circuit and a bonding portion for a circuit are arranged in the recess, and a semiconductor element is fixed to the bonding portion. A sealed semiconductor device in which a semiconductor chip, in which a semiconductor chip is bonded to the bonding portion with a wire, is placed inverted on a flat substrate having a circuit pattern, and contact conductive portions of the metal substrate and the circuit board are bonded. (2) The sealed semiconductor device according to claim 1, wherein the semiconductor chip is buffer coated with a soft resin. (3) The sealed semiconductor device according to claim 1, wherein the semiconductor chip is sealed with an epoxy resin that fills the entire recess of the metal substrate. (4) The sealed semiconductor device according to any one of claims 1 to 3, wherein lead legs for drawing out electric circuits are attached to the surface electric circuit section on a flat circuit board. (5) A through-pole hole with a conductive part formed around the periphery is provided for drawing out the electric circuit in the front surface electric circuit section of the flat circuit board, and the front surface electric circuit section is electrically connected to the lower electrode on the back surface through this hole. A sealed semiconductor device according to any one of claims 1 to 3.
JP58193174A 1983-10-14 1983-10-14 Sealed semiconductor device Pending JPS6084845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58193174A JPS6084845A (en) 1983-10-14 1983-10-14 Sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58193174A JPS6084845A (en) 1983-10-14 1983-10-14 Sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6084845A true JPS6084845A (en) 1985-05-14

Family

ID=16303528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58193174A Pending JPS6084845A (en) 1983-10-14 1983-10-14 Sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6084845A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364077U (en) * 1986-06-02 1988-04-27
JPH01132147A (en) * 1987-08-08 1989-05-24 Toshiba Corp Semiconductor device
JPH0412673U (en) * 1990-05-23 1992-01-31
JPH04275481A (en) * 1991-03-04 1992-10-01 Rohm Co Ltd Laser diode
JPH04276679A (en) * 1991-03-05 1992-10-01 Rohm Co Ltd Laser diode
KR100256293B1 (en) * 1995-11-07 2000-05-15 모기 쥰이찌 Semiconductor device and manufacturing method
DE10146854B4 (en) * 2001-09-24 2009-05-20 Infineon Technologies Ag Electronic component with at least one semiconductor chip and method for producing an electronic component with at least one semiconductor chip
WO2012064708A1 (en) * 2010-11-12 2012-05-18 Apple Inc. Unitary housing for electronic device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364077U (en) * 1986-06-02 1988-04-27
JPH01132147A (en) * 1987-08-08 1989-05-24 Toshiba Corp Semiconductor device
JPH0412673U (en) * 1990-05-23 1992-01-31
JPH04275481A (en) * 1991-03-04 1992-10-01 Rohm Co Ltd Laser diode
JPH04276679A (en) * 1991-03-05 1992-10-01 Rohm Co Ltd Laser diode
KR100256293B1 (en) * 1995-11-07 2000-05-15 모기 쥰이찌 Semiconductor device and manufacturing method
DE10146854B4 (en) * 2001-09-24 2009-05-20 Infineon Technologies Ag Electronic component with at least one semiconductor chip and method for producing an electronic component with at least one semiconductor chip
WO2012064708A1 (en) * 2010-11-12 2012-05-18 Apple Inc. Unitary housing for electronic device
US8730656B2 (en) 2010-11-12 2014-05-20 Apple Inc. Unitary housing for electronic device
US10118560B2 (en) 2010-11-12 2018-11-06 Apple Inc. Unitary housing for electronic device
US10696235B2 (en) 2010-11-12 2020-06-30 Apple Inc. Unitary housing for electronic device
US11505131B2 (en) 2010-11-12 2022-11-22 Apple Inc. Unitary housing for electronic device

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