JPH11126776A - Bonding pad of semiconductor and method of manufacturing the same - Google Patents
Bonding pad of semiconductor and method of manufacturing the sameInfo
- Publication number
- JPH11126776A JPH11126776A JP9289860A JP28986097A JPH11126776A JP H11126776 A JPH11126776 A JP H11126776A JP 9289860 A JP9289860 A JP 9289860A JP 28986097 A JP28986097 A JP 28986097A JP H11126776 A JPH11126776 A JP H11126776A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bpsg
- bonding pad
- metal
- bpsg film
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にはボンディングパッド及びその製造方法に関する。
なお本明細書においては、リン５％とボロン１０％程度
を含んだ酸化膜リン５％とボロン１０％程度を含んだ酸
化膜をＢＰＳＧと記載し、実質的にリンやボロンを含ま
ず主にシリケートガラスからなる酸化膜を以下ＮＳＧ膜
と記載する。The present invention relates to a semiconductor device,
In particular, it relates to a bonding pad and a method for manufacturing the same.
In this specification, an oxide film containing 5% of phosphorus and about 10% of boron is referred to as an BPSG, and an oxide film containing about 5% of phosphorus and about 10% of boron is mainly contained substantially without phosphorus or boron. An oxide film made of silicate glass is hereinafter referred to as an NSG film.
【０００２】[0002]
【従来の技術】従来のボンディングパッドは、図２に示
すように、フィールド酸化膜１の上にＢＰＳＧ膜２が形
成されている。ＢＰＳＧ膜は、８００℃程度の熱処理を
行うことで、容易に表面平坦化が行えるため、最下層メ
タル下の層間膜として、広く利用されている。2. Description of the Related Art A conventional bonding pad has a BPSG film 2 formed on a field oxide film 1 as shown in FIG. The BPSG film can be easily flattened by performing a heat treatment at about 800 ° C., and is therefore widely used as an interlayer film under the lowermost metal.
【０００３】ＢＰＳＧ膜２の上には、下層メタルパッド
４が形成され、その上には、上層メタルパッド５を有す
る。下層メタルパッド４と上層メタルパッド５とは、タ
ングステンＣＶＤで層間絶縁膜６中を埋設された多数の
孔７で接続されており、最上層にあるパッシベーション
膜８は、上層メタルパッド５の上を開孔している。ま
た、配線の配線寿命を向上させるため、配線下にはチタ
ンなどの高融点金属で形成されたバリアメタル層３が、
０．０５μｍ成膜されている。A lower metal pad 4 is formed on the BPSG film 2, and an upper metal pad 5 is formed thereon. The lower metal pad 4 and the upper metal pad 5 are connected by a number of holes 7 buried in the interlayer insulating film 6 by tungsten CVD, and the uppermost passivation film 8 is formed on the upper metal pad 5. It is open. In order to improve the wiring life of the wiring, a barrier metal layer 3 made of a high melting point metal such as titanium is provided under the wiring.
The film is formed to a thickness of 0.05 μm.
【０００４】図２の構造は、図３に示すような、上層メ
タルパッド単独で形成された場合に発生する剥がれの問
題を解決するために、採用された構造であり、その原因
としては、素子の微細化に伴うメタル層の薄膜化のた
め、ボンディングするときの荷重を単層メタルパッド１
０では支えきらないためである。従来技術の問題点は、
下層メタルパッドが、ＢＰＳＧ膜と接しているため、下
層メタルパッドとＢＰＳＧ膜の界面で、ボンディング時
に剥がれが生じるということである。[0004] The structure shown in FIG. 2 is adopted to solve the problem of peeling that occurs when the upper metal pad is formed alone as shown in FIG. 3. In order to make the metal layer thinner due to the miniaturization of the metal, the load at the time of bonding is reduced to a single-layer metal pad 1.
It is because 0 cannot support it. The problem with the prior art is that
Since the lower metal pad is in contact with the BPSG film, peeling occurs at the interface between the lower metal pad and the BPSG film during bonding.
【０００５】その理由は、バリアメタルとして下層メタ
ルパッドとＢＰＳＧ膜の間に形成されているチタンなど
の高融点金属とＢＰＳＧ膜との密着強度が不足するから
である。前記ＢＰＳＧ層とバリアメタル層の密着性を高
める手段は、たとえば特開平６−１９６５２５にメタル
パッドとポリシリコンパッド間の接続孔を多数のスリッ
トまたは多数の孔の分散した配列により形成したものが
記載されている。しかしながらそこにはＢＰＳＧ膜と高
融点金属膜との間にＮＳＧ膜を有することは記載されて
はいない。[0005] The reason is that the adhesion strength between the BPSG film and a high melting point metal such as titanium formed between the lower metal pad and the BPSG film as a barrier metal is insufficient. The means for improving the adhesion between the BPSG layer and the barrier metal layer is described, for example, in JP-A-6-196525 in which connection holes between metal pads and polysilicon pads are formed by a large number of slits or a dispersed arrangement of a large number of holes. Have been. However, it does not disclose that an NSG film is provided between the BPSG film and the refractory metal film.
【０００６】また特開平５−１６０１３３には半導体装
置に関して、ボンディングパット上にタングステン及び
金の中間層を用いることが示されている。しかしながら
そこにはＢＰＳＧ膜と高融点金属膜との間にＮＳＧ膜を
有することは記載されてはいない。Japanese Unexamined Patent Publication No. 5-160133 discloses the use of an intermediate layer of tungsten and gold on a bonding pad for a semiconductor device. However, it does not disclose that an NSG film is provided between the BPSG film and the refractory metal film.
【０００７】[0007]
【発明が解決しようとする課題】従来技術の問題点は、
下層メタルパッドが、ＢＰＳＧ膜と接しているため、下
層メタルパッドとＢＰＳＧ膜の界面で、ボンディング時
に剥がれが生じるということである。その理由は、バリ
アメタルとして下層メタルパッドとＢＰＳＧ膜の間に形
成されているチタンなどの高融点金属とＢＰＳＧ膜との
密着強度が不足するからである。Problems with the prior art are as follows.
Since the lower metal pad is in contact with the BPSG film, peeling occurs at the interface between the lower metal pad and the BPSG film during bonding. The reason is that the adhesion strength between the high melting point metal such as titanium formed between the lower metal pad and the BPSG film as the barrier metal and the BPSG film is insufficient.
【０００８】本発明は、下層メタルパッド下のバリアメ
タルがＢＰＳＧ膜に直接接することをなくし、ボンディ
ング時にパッドの剥がれを発生しにくくすることを目的
とする。An object of the present invention is to prevent a barrier metal under a lower metal pad from coming into direct contact with a BPSG film, thereby making it difficult for the pad to peel off during bonding.
【０００９】[0009]
【課題を解決するための手段】本発明のボンディングパ
ッドでは、上層メタルと下層メタル間を多数の分散した
孔で接続している集積回路のボンディングパッドの下層
メタルを高融点金属膜を介してＢＰＳＧ膜と接合させる
構造において、ＢＰＳＧ膜と高融点金属膜との間にリ
ン、ボロン等の不純物を含有しない膜を設けたことを特
徴とする。According to the bonding pad of the present invention, the lower metal of the bonding pad of the integrated circuit in which the upper metal and the lower metal are connected by a large number of dispersed holes is connected to the BPSG via the refractory metal film. In the structure which is bonded to a film, a film which does not contain impurities such as phosphorus and boron is provided between the BPSG film and the high melting point metal film.
【００１０】[0010]
【発明の実施の形態】上層メタルと下層メタル間を多数
の分散した孔で接続している集積回路のボンディングパ
ッドにおいて、ＢＰＳＧ膜と高融点金属膜とＮＳＧ膜を
有し、ＢＰＳＧ膜と高融点金属膜との間にＮＳＧ膜を有
することを特徴とする。具体的には、ＢＰＳＧ膜とバリ
アメタル層を直接に接触させず、ＢＰＳＧ膜とバリアメ
タル層を分離する手段としてＮＳＧ膜（図１の９）を有
する。BEST MODE FOR CARRYING OUT THE INVENTION A bonding pad of an integrated circuit connecting an upper metal layer and a lower metal layer with a large number of dispersed holes has a BPSG film, a refractory metal film, and an NSG film. It is characterized by having an NSG film between itself and a metal film. Specifically, an NSG film (9 in FIG. 1) is provided as a means for separating the BPSG film and the barrier metal layer without directly contacting the BPSG film and the barrier metal layer.
【００１１】ＢＰＳＧ膜とバリアメタル層の間に、リン
やボロン等の不純物を含有しない酸化膜（以下ＮＳＧ膜
と記述）を有することで、元来密着性の良くないＢＰＳ
Ｇ膜とバリアメタル層を分離する。Since an oxide film containing no impurities such as phosphorus and boron (hereinafter referred to as an NSG film) is provided between the BPSG film and the barrier metal layer, the BPSG film originally has poor adhesion.
The G film and the barrier metal layer are separated.
【００１２】[0012]
【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。本発明のボンディングパッドの構造
においては、上層メタルパッド５と下層メタルパッド４
間を多数の分散した孔９で接続している集積回路のボン
ディングパッドにおいて、ＢＰＳＧ膜２と高融点金属膜
３とＮＳＧ膜９を有し、ＢＰＳＧ膜２と高融点金属膜３
との間にＮＳＧ膜２を有することを特徴とするものであ
る。図１を参照すると、本発明の実施例は、フィールド
酸化膜１の上に０．５〜１．５μｍ厚のＢＰＳＧ膜２形
成されており、ＢＰＳＧ膜２の上には、ＮＳＧ膜８が
０．１〜０．３μｍの厚さで形成されている。その上に
は、０．０５μｍ厚のバリアメタル層３と０．５μｍ厚
の下層メタルパッド４と０．６μｍ厚の上層メタルパッ
ド５を有し、下層メタルパッド４と上層メタルパッド５
は、１μｍの厚さの層間絶縁膜６中をＣＶＤ技術でタン
グステンを埋設した多数の孔７で接続されていて、最上
層にある１μｍの膜厚のパッシベーション膜８は、上層
アルミパッド５の上を開孔している。Next, embodiments of the present invention will be described in detail with reference to the drawings. In the structure of the bonding pad of the present invention, the upper metal pad 5 and the lower metal pad 4
In a bonding pad of an integrated circuit in which a plurality of holes 9 are connected to each other, a BPSG film 2, a refractory metal film 3, and an NSG film 9 are provided.
And an NSG film 2 between them. Referring to FIG. 1, in the embodiment of the present invention, a BPSG film 2 having a thickness of 0.5 to 1.5 μm is formed on a field oxide film 1, and an NSG film 8 is formed on the BPSG film 2. It is formed in a thickness of 0.1 to 0.3 μm. A barrier metal layer 3 having a thickness of 0.05 μm, a lower metal pad 4 having a thickness of 0.5 μm, and an upper metal pad 5 having a thickness of 0.6 μm are provided thereon.
Is connected by a large number of holes 7 in which tungsten is buried by a CVD technique in an interlayer insulating film 6 having a thickness of 1 μm, and a passivation film 8 having a thickness of 1 μm on the uppermost layer is formed on the upper aluminum pad 5. The hole is opened.
【００１３】又、本発明の製造方法は、半導体基板上に
フィールド酸化膜を介してＢＰＳＧ膜を形成する工程、
当該ＢＰＳＧ膜上にリン、ボロン等の不純物を含有しな
い膜（ＮＳＧ膜）を形成する工程、当該ＮＳＧ膜上にバ
リアメタル層を形成する工程とからなることを特徴とす
るボンディングパッドの構造の製造方法である。The manufacturing method of the present invention further comprises a step of forming a BPSG film on a semiconductor substrate via a field oxide film.
Forming a film (NSG film) containing no impurities such as phosphorus and boron on the BPSG film; and forming a barrier metal layer on the NSG film. Is the way.
【００１４】[0014]
【発明の効果】発明の効果は、下層メタルパッド下のバ
リアメタル層が、ＢＰＳＧ膜と直接に接触しなくなるた
め、下層メタルパッドの下での剥がれが発生しにくいこ
とである。その理由は、密着性の悪いバリアメタル層と
ＢＰＳＧ膜との間に、ＮＳＧ膜を形成することで密着性
の劣化を防止するからである。The effect of the present invention is that the barrier metal layer under the lower metal pad does not come into direct contact with the BPSG film, so that peeling under the lower metal pad hardly occurs. The reason is that by forming an NSG film between the barrier metal layer having poor adhesion and the BPSG film, deterioration of the adhesion is prevented.
【図１】本発明のボンディングパッドの実施例の断面
図。FIG. 1 is a sectional view of an embodiment of a bonding pad of the present invention.
【図２】従来のボンディングパッドの断面図。FIG. 2 is a cross-sectional view of a conventional bonding pad.
【図３】従来の単層メタルパッドの断面図。FIG. 3 is a cross-sectional view of a conventional single-layer metal pad.
１…フィールド酸化膜 ２…ＢＰＳＧ膜 ３…バリアメタル層 ４…下層メタルパッド ５…上層メタルパッド ６…層間絶縁膜 ７…孔 ８…パッシベーション膜 ９…ＮＳＧ膜 １０…単層メタルパッド REFERENCE SIGNS LIST 1 field oxide film 2 BPSG film 3 barrier metal layer 4 lower metal pad 5 upper metal pad 6 interlayer insulating film 7 hole 8 passivation film 9 NSG film 10 single layer metal pad
Claims (6)
した孔で接続している集積回路のボンディングパッドの
下層メタルを高融点金属膜を介してＢＰＳＧ膜と接合さ
せる構造において、ＢＰＳＧ膜と高融点金属膜との間に
リン、ボロン等の不純物を含有しない膜（ＮＳＧ膜）を
設けたことを特徴とするボンディングパッドの構造。In a structure in which a lower layer metal of a bonding pad of an integrated circuit which connects an upper layer metal and a lower layer metal with a large number of dispersed holes is bonded to a BPSG film via a high melting point metal film, A structure of a bonding pad, wherein a film (NSG film) containing no impurities such as phosphorus and boron is provided between the film and the melting point metal film.
％程度を含んだ酸化膜であることを特徴とする請求項１
記載のボンディングパッドの構造。2. The BPSG film according to claim 1, wherein said BPSG film comprises 5% phosphorus and 10% boron.
2. An oxide film containing about% by weight.
The structure of the bonding pad described.
とを特徴とする請求項１または２記載のボンディングパ
ッドの構造。3. The bonding pad structure according to claim 1, wherein said high melting point metal film is made of a titanium alloy.
てＢＰＳＧ膜を形成する工程、当該ＢＰＳＧ膜上にリ
ン、ボロン等の不純物を含有しない膜（ＮＳＧ膜）を形
成する工程、当該ＮＳＧ膜上にバリアメタル層を形成す
る工程とからなることを特徴とするボンディングパッド
の構造の製造方法。4. A step of forming a BPSG film on a semiconductor substrate via a field oxide film, a step of forming a film (NSG film) containing no impurities such as phosphorus and boron on the BPSG film, and a step of forming a film on the NSG film. Forming a barrier metal layer on the bonding pad.
％程度を含んだ酸化膜であることを特徴とする請求項４
記載のボンディングパッドの構造の製造方法。5. The BPSG film according to claim 1, wherein said BPSG film comprises 5% phosphorus and 10% boron.
5. An oxide film containing about%.
A method for manufacturing the structure of the bonding pad described above.
とを特徴とする請求項４または５記載のボンディングパ
ッドの構造の製造方法。6. The method according to claim 4, wherein the high melting point metal film is a titanium alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28986097A JP3211749B2 (en) | 1997-10-22 | 1997-10-22 | Bonding pad for semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28986097A JP3211749B2 (en) | 1997-10-22 | 1997-10-22 | Bonding pad for semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11126776A true JPH11126776A (en) | 1999-05-11 |
| JP3211749B2 JP3211749B2 (en) | 2001-09-25 |
Family
ID=17748705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28986097A Expired - Fee Related JP3211749B2 (en) | 1997-10-22 | 1997-10-22 | Bonding pad for semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3211749B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313540B1 (en) | 1998-12-25 | 2001-11-06 | Nec Corporation | Electrode structure of semiconductor element |
| KR100367737B1 (en) * | 2000-02-18 | 2003-01-10 | 주식회사 하이닉스반도체 | Manufacturing method for pad in semiconductor device |
| WO2003001595A3 (en) * | 2001-06-25 | 2004-05-27 | Koninkl Philips Electronics Nv | Electronic device |
| KR100605194B1 (en) | 2004-12-29 | 2006-07-31 | 동부일렉트로닉스 주식회사 | Method for forming the pad layer of semiconductor device |
| JP2012160633A (en) * | 2011-02-02 | 2012-08-23 | Lapis Semiconductor Co Ltd | Wiring structure of semiconductor device and method of manufacturing the same |
| US10418336B2 (en) | 2017-03-14 | 2019-09-17 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
-
1997
- 1997-10-22 JP JP28986097A patent/JP3211749B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313540B1 (en) | 1998-12-25 | 2001-11-06 | Nec Corporation | Electrode structure of semiconductor element |
| KR100367737B1 (en) * | 2000-02-18 | 2003-01-10 | 주식회사 하이닉스반도체 | Manufacturing method for pad in semiconductor device |
| WO2003001595A3 (en) * | 2001-06-25 | 2004-05-27 | Koninkl Philips Electronics Nv | Electronic device |
| KR100605194B1 (en) | 2004-12-29 | 2006-07-31 | 동부일렉트로닉스 주식회사 | Method for forming the pad layer of semiconductor device |
| JP2012160633A (en) * | 2011-02-02 | 2012-08-23 | Lapis Semiconductor Co Ltd | Wiring structure of semiconductor device and method of manufacturing the same |
| US10418336B2 (en) | 2017-03-14 | 2019-09-17 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3211749B2 (en) | 2001-09-25 |
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