JP4646789B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4646789B2
JP4646789B2 JP2005348562A JP2005348562A JP4646789B2 JP 4646789 B2 JP4646789 B2 JP 4646789B2 JP 2005348562 A JP2005348562 A JP 2005348562A JP 2005348562 A JP2005348562 A JP 2005348562A JP 4646789 B2 JP4646789 B2 JP 4646789B2
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electrode pad
vias
semiconductor device
electrode
pad
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JP2007157857A (en
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知規 伊藤
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
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    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

本発明は、半導体装置に関する。特に、素子形成領域上に入出力パッドを備えた半導体装置に関する。   The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device provided with an input / output pad on an element formation region.

図４（ａ）は従来の半導体装置の上面を模式的に示している。図４（ｂ）はその要部ＡＡの断面を示している。
半導体装置１００は、半導体チップ１１０の中央部分に形成された内部回路１１２と、半導体チップ１１０の外周部分に形成された入出力回路１１４とを備えている。入出力回路１１４は、複数の入出力セル１２０から構成されており、入出力セル１２０は、半導体チップ１１０の外周部分に一列に配列されている。 FIG. 4A schematically shows the upper surface of a conventional semiconductor device. FIG. 4B shows a cross section of the main part AA.
The semiconductor device 100 includes an internal circuit 112 formed in the central portion of the semiconductor chip 110 and an input / output circuit 114 formed in the outer peripheral portion of the semiconductor chip 110. The input / output circuit 114 is composed of a plurality of input / output cells 120, and the input / output cells 120 are arranged in a line on the outer periphery of the semiconductor chip 110.

入出力セル１２０は、シリコン基板上に形成された最下層配線１４４と、最下層配線１４４の上層に形成された電源配線１４２と、各層の配線を電気的に絶縁する絶縁膜１４０と、絶縁膜１４０の最上層の上面に形成された電極パッド１２２とを有している。電極パッド１２２には、電極パッド引き出し部１４６が電気的に接続されており、絶縁膜１４０の上面には、電極パッド１２２を露出するように保護膜１２４が形成されている。なお、絶縁膜１４０の中に位置する電源配線１４２は、半導体チップ１１０の外周部分を取り囲むようにリング状に形成されている。   The input / output cell 120 includes a lowermost layer wiring 144 formed on a silicon substrate, a power supply wiring 142 formed on an upper layer of the lowermost layer wiring 144, an insulating film 140 that electrically insulates the wiring of each layer, an insulating film 140 and electrode pads 122 formed on the upper surface of the uppermost layer. An electrode pad lead portion 146 is electrically connected to the electrode pad 122, and a protective film 124 is formed on the upper surface of the insulating film 140 so as to expose the electrode pad 122. Note that the power supply wiring 142 located in the insulating film 140 is formed in a ring shape so as to surround the outer peripheral portion of the semiconductor chip 110.

この電極パッド１２２は、例えばワイヤーボンディングによってリードフレームと接続され、内部回路１１２と外部回路とを電気的に接続する役割を有している。電極パッド１２２がリードフレームと接続された後は、半導体チップ１１０の全体が封止されてＱＦＰ（Quard Flat Package）やＳＯＰ（Small Outline Package）などのパッケージにされることになる。また、ＣＳＰ（Chip Size Package）やＴＣＰ（Tape Carrier Package）などのパッケージにする場合、電極パッド１２２には、スタッドバンプ（金バンプ）や電解めっき法・蒸着法などで形成したバンプＢが設けられることになる。   The electrode pad 122 is connected to the lead frame by wire bonding, for example, and has a role of electrically connecting the internal circuit 112 and the external circuit. After the electrode pad 122 is connected to the lead frame, the entire semiconductor chip 110 is sealed to form a package such as QFP (Quard Flat Package) or SOP (Small Outline Package). Further, when a package such as CSP (Chip Size Package) or TCP (Tape Carrier Package) is used, the electrode pad 122 is provided with a bump B formed by a stud bump (gold bump), an electrolytic plating method, an evaporation method, or the like. It will be.

電極パッド１２２は、半導体チップ１１０の外周部の最も外周側（半導体チップ外周方向５０の最も外周側）に設けられている。ワイヤーボンディングやバンプ形成を行う際には、電極パッド１２２を通じて電極パッド１２２の下方に衝撃が伝わることになる。この衝撃が半導体装置の特性に影響を及ぼさないようにするために、電極パッド１２２の下方に位置する部位のシリコン基板には拡散形成を行っておらず、電極パッド１２２の下方に位置する絶縁膜１４０中には配線などの素子を設けていない。すなわち、電極パッド１２２は、素子形成領域（トランジスタなどの素子が形成される領域）でない部分のシリコン基板（Ｓｉ基板）の上方に配置されている。   The electrode pad 122 is provided on the outermost peripheral side of the outer peripheral portion of the semiconductor chip 110 (the outermost peripheral side in the semiconductor chip outer peripheral direction 50). When wire bonding or bump formation is performed, an impact is transmitted to the lower part of the electrode pad 122 through the electrode pad 122. In order to prevent the impact from affecting the characteristics of the semiconductor device, the silicon substrate in the portion located below the electrode pad 122 is not diffused and the insulating film located below the electrode pad 122 is not formed. No elements such as wiring are provided in 140. That is, the electrode pad 122 is disposed above the silicon substrate (Si substrate) in a portion that is not an element formation region (a region where an element such as a transistor is formed).

図５はスタッドバンプの一般的な形成工程を示している。
先ず、図５（ａ）に示すように、筒状のキャピラリツール２より金属細線３を引き出し、キャピラリツール２の上部に取り付けられたクランパ機構４によって金属細線３の上部を保持した状態で、放電トーチ手段を用いて例えば放電Ａによる通電によって金属細線３の先端を加熱し、これによって図５（ｂ）に示すように金属ボール３１を形成する。次に、図５（ｃ）に示すようにキャピラリツール２により金属ボール３１を半導体チップ１１０の端子面１３に押し付け、超音波振動を与えることによって、金属ボール３１を変形させながら端子面１３と結合させる。次に、図５（ｄ）に示すように金属細線３を保持しながらキャピラリツール２を引き上げることによって金属細線３を引き千切り、端子面１３にバンプＢを形成する方法が用いられている。１１は基材となるシリコン層，１２は配線層である。金属ボール３１をキャピラリツール２によって半導体チップ１１０の端子面１３に押し付ける図５（ｃ）の工程において、その押し付け荷重が半導体チップ１１０の内部の配線層１２に影響し、絶縁膜の亀裂や界面剥離などのダメージＮＧを引き起こす可能性がある。ワイヤーボンディングの場合にも同様にダメージＮＧを引き起こす可能性がある。 FIG. 5 shows a general process for forming stud bumps.
First, as shown in FIG. 5 (a), the metal thin wire 3 is pulled out from the cylindrical capillary tool 2 and the upper portion of the metal thin wire 3 is held by the clamper mechanism 4 attached to the upper portion of the capillary tool 2. Using the torch means, for example, the tip of the thin metal wire 3 is heated by energization by the discharge A, thereby forming the metal ball 31 as shown in FIG. Next, as shown in FIG. 5 (c), the metal ball 31 is pressed against the terminal surface 13 of the semiconductor chip 110 by the capillary tool 2, and ultrasonic waves are applied to deform the metal ball 31 and couple with the terminal surface 13. Let Next, as shown in FIG. 5 (d), a method is used in which the fine metal wire 3 is pulled up by pulling up the capillary tool 2 while holding the fine metal wire 3 and bumps B are formed on the terminal surface 13. Reference numeral 11 denotes a silicon layer serving as a base material, and reference numeral 12 denotes a wiring layer. In the step of FIG. 5C in which the metal ball 31 is pressed against the terminal surface 13 of the semiconductor chip 110 by the capillary tool 2, the pressing load affects the wiring layer 12 inside the semiconductor chip 110, causing cracks in the insulating film and interface peeling. May cause damage NG. Similarly, in the case of wire bonding, damage NG may be caused.

（特許文献１）には、図６に示すように、チップサイズを小さくした半導体装置にすることを目的として、電極パッド１２２を入出力セル１２０の素子形成領域上に配置したパッド構造が提案されている。この公報によると、例えば、ロジック回路やドライバ回路が形成された素子形成領域上に絶縁膜が設けられ、その上に入力パッドまたは出力パッドが形成されている。   (Patent Document 1) proposes a pad structure in which an electrode pad 122 is arranged on an element formation region of an input / output cell 120 for the purpose of making a semiconductor device with a reduced chip size, as shown in FIG. ing. According to this publication, for example, an insulating film is provided on an element formation region where a logic circuit and a driver circuit are formed, and an input pad or an output pad is formed thereon.

（特許文献２）には、図７（ａ）に示すように、外部接続用電極が端子面に形成される電極パッド１２１と、電極パッド１２１の下層に位置する配線層１２３と、電極パッド１２１と電極パッド１１６とを接続する複数のビア１１９を設けた半導体装置が記載されている。ビア１１９の配置は、図７（ｂ）に示すようにハニカム状の絶縁膜１１７の中に導電材料を充填して構成されている。
特開平６―２４４２３５号公報 図２ 特開２００５−１２３５８７公報 図１，図２ In Patent Document 2, as shown in FIG. 7A, an electrode pad 121 in which an external connection electrode is formed on a terminal surface, a wiring layer 123 positioned below the electrode pad 121, and an electrode pad 121. And a semiconductor device provided with a plurality of vias 119 for connecting the electrode pads 116 to each other. As shown in FIG. 7B, the vias 119 are arranged by filling a honeycomb-like insulating film 117 with a conductive material.
Japanese Patent Laid-Open No. 6-244235 FIG. [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-123587 FIG.

（特許文献２）に示すように、電極パッド１２１と電極パッド１１６の間に図７（ｂ）に示すように多数のビア１１９を設けることによって、電極パッド１２１に対してバンプ形成時やワイヤーボンディングする際の衝撃荷重や金属細線の引き千切り時の引張り力の影響によって、配線や絶縁膜に与えるダメージを低減できる。   As shown in (Patent Document 2), a large number of vias 119 are provided between the electrode pad 121 and the electrode pad 116 as shown in FIG. Damage to the wiring and the insulating film can be reduced by the influence of the impact load at the time of pulling and the pulling force when the fine metal wire is drawn.

しかしながら、入出力セルごとに多数のビア１１９を形成することは、作業性ならびにコストの点で問題があり、改善が要望されているのが現状である。
本発明は、入出力セルごとに従来よりも数少ないビアを設けるだけで、バンプ形成時やワイヤーボンディングする際の衝撃荷重や金属細線の引き千切り時の引張り力から、配線や絶縁膜を保護できる半導体装置を提供することを目的とする。 However, the formation of a large number of vias 119 for each input / output cell has a problem in terms of workability and cost, and the present situation is that improvement is desired.
The present invention provides a semiconductor that can protect a wiring and an insulating film from an impact load at the time of bump formation or wire bonding and a pulling force at the time of cutting a thin metal wire by providing fewer vias for each input / output cell. An object is to provide an apparatus.

本発明の請求項１記載の半導体装置は、内部回路と外部回路との電気接続用の入出力パッドを、端子面またはその上層にスタッドバンプが形成される第１電極パッドと、前記第１電極パッドの下層に位置する配線層から形成される第２電極パッドと、前記第１電極パッドと前記第２電極パッドとの間に位置する絶縁膜中に形成され前記第１電極パッドと前記第２電極パッドとを接続する複数のビアとを設けた半導体装置であって、第１電極パッドの端子面またはその上層に形成されたスタッドバンプを有し、複数の前記ビアを、前記スタッドバンプの前記第１電極パッドと接合される台座部分とその上部の部分との境界の外周の直下のみに、１〜２μｍの間隔で、環状に配列したことを特徴とする。 The semiconductor device according to claim 1 of the present invention includes an input / output pad for electrical connection between an internal circuit and an external circuit, a first electrode pad on which a stud bump is formed on a terminal surface or an upper layer thereof, and the first electrode. A second electrode pad formed from a wiring layer located in a lower layer of the pad; and the first electrode pad and the second electrode formed in an insulating film positioned between the first electrode pad and the second electrode pad. A semiconductor device provided with a plurality of vias for connecting to electrode pads, comprising a stud bump formed on a terminal surface of the first electrode pad or an upper layer thereof, and a plurality of the vias being connected to the stud bump It is characterized in that it is arranged in an annular shape at an interval of 1 to 2 μm only immediately below the outer periphery of the boundary between the pedestal portion bonded to the first electrode pad and the upper portion thereof.

本発明の請求項２記載の半導体装置は、請求項１において、前記ビア径が、デザインルールの最小寸法であることを特徴とする。 According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the via diameter is a minimum dimension of a design rule .

本発明の請求項３記載の半導体装置は、請求項１または請求項２において、環状に配列した前記ビアの内側に、前記第１電極パッドと前記第２電極パッドとを接続するビアを環状に配設し、かつ、環状に配列した前記ビアの外側の面積が広い領域にも前記第１電極パッドと前記第２電極パッドとを接続するビアを配設したことを特徴とする。
本発明の請求項４記載の半導体装置は、内部回路と外部回路との電気接続用の入出力パッドを、端子面またはその上層にスタッドバンプが形成される第１電極パッドと、前記第１電極パッドの下層に位置する配線層から形成される第２電極パッドと、前記第１電極パッドと前記第２電極パッドとの間に位置する絶縁膜中に形成され前記第１電極パッドと前記第２電極パッドとを接続する複数のビアとを設けた半導体装置であって、複数の前記ビアを、前記スタッドバンプの前記第１電極パッドと接合される台座部分とその上部の部分との境界の外周の直下の円の外周側と内周側にのみ交互に配設したことを特徴とする。 According to a third aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein the via connecting the first electrode pad and the second electrode pad is annularly formed inside the via arranged in an annular shape. A via that connects the first electrode pad and the second electrode pad is also provided in a region having a large area outside the via arranged in a ring shape .
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising: an input / output pad for electrical connection between an internal circuit and an external circuit; a first electrode pad having a stud bump formed on a terminal surface or an upper layer thereof; and the first electrode A second electrode pad formed from a wiring layer located in a lower layer of the pad; and the first electrode pad and the second electrode formed in an insulating film positioned between the first electrode pad and the second electrode pad. A semiconductor device provided with a plurality of vias for connecting to electrode pads, wherein the plurality of vias are arranged at the outer periphery of a boundary between a pedestal portion bonded to the first electrode pad of the stud bump and an upper portion thereof It is characterized by being alternately arranged only on the outer peripheral side and the inner peripheral side of the circle immediately below.

本発明によれば、複数のビアを外部接続用電極の径に応じた環状に配列したため、一つのビアの大きさを同じとした場合に、従来よりも数少ないビアを設けるだけで、バンプ形成時やワイヤーボンディングする際の衝撃荷重や金属細線の引き千切り時の引張り力から、配線や絶縁膜を保護でき、信頼性の向上を期待できる。   According to the present invention, since a plurality of vias are arranged in an annular shape corresponding to the diameter of the external connection electrode, when the size of one via is the same, only a few vias are provided as compared with the prior art. Wiring and insulating films can be protected from the impact load during wire bonding and the pulling force when thin metal wires are cut, and improved reliability can be expected.

以下、本発明の半導体装置を図１〜図３に基づいて説明する。
（実施の形態１）
図１と図２は本発明の（実施の形態１）を示す。 The semiconductor device of the present invention will be described below with reference to FIGS.
(Embodiment 1)
1 and 2 show (Embodiment 1) of the present invention.

図１（ｂ）は、半導体装置１００の入出力回路１１４の前記要部ＡＡの断面を模式的に示している。半導体装置１００の上面図は図３（ａ）と同じであり、半導体装置１００は、半導体チップの中央部分に形成された内部回路１１２と、半導体チップの外周部分に形成された入出力回路１１４とを備えている。入出力回路１１４は、複数の入出力セル１２０から構成されており、入出力セル１２０は、例えば、半導体チップの外周部分に一列に配列されている。   FIG. 1B schematically shows a cross section of the main part AA of the input / output circuit 114 of the semiconductor device 100. The top view of the semiconductor device 100 is the same as FIG. 3A, and the semiconductor device 100 includes an internal circuit 112 formed in the central portion of the semiconductor chip and an input / output circuit 114 formed in the outer peripheral portion of the semiconductor chip. It has. The input / output circuit 114 is composed of a plurality of input / output cells 120, and the input / output cells 120 are arranged in a line on the outer periphery of the semiconductor chip, for example.

入出力セル１２０は、半導体基板（シリコン基板）の素子形成領域上に位置する絶縁膜１４０の上に形成されており、積層ビア構造３０を有している。積層ビア構造３０は、最上層の第１配線層から構成された第１電極パッド３２と、第１配線層の下層に位置する第２配線層から構成された第２電極パッド３４と、第１電極パッド３２と第２電極パッド３４との間の絶縁膜１４０中に形成され、第１電極パッド３２と第２電極パッド３４とを接続するビア３６とを有している。   The input / output cell 120 is formed on the insulating film 140 located on the element formation region of the semiconductor substrate (silicon substrate), and has the laminated via structure 30. The stacked via structure 30 includes a first electrode pad 32 configured from the uppermost first wiring layer, a second electrode pad 34 configured from the second wiring layer positioned below the first wiring layer, and a first A via 36 is formed in the insulating film 140 between the electrode pad 32 and the second electrode pad 34 and connects the first electrode pad 32 and the second electrode pad 34.

この実施の形態では、最上層（第４層）に形成した第１電極パッド３２と、その１つ下層（第３層）に形成した第２電極パッド３４とが、基板法線方向から見て互いに重なるように形成されており、第１電極パッド３２と第２電極パッド３４の間は複数のビア３６によって接続されている。第１電極パッド３２および第２電極パッド３４は、例えばアルミの単層（厚さ：例えば０．５μｍ〜１．０μｍ程度）から構成されており、ビア３６は、例えば、タングステンから構成されている。第１電極パッド３２と第２電極パッド３４の下方には、電源配線４２および最下層配線４４が形成されており、絶縁膜１４０の最上層には、第１電極パッド３２の一部を露出するようにして保護膜１２４が形成されている。半導体チップ１１０の外周部に各入出力セル１２０を隣接して配置した場合、電源配線（第２層）４２は、チップ外周部を取り囲むようにリング状に形成されている。電源配線４２の下には、入出力回路内の第１層である最下層配線４４が形成されており、最下層配線層４４のさらに下面には、トランジスタ等を含む拡散層が形成されている。最下層配線層４４は、引き出し配線部４６を通じて第２電極パッド３４に電気的に接続されている。   In this embodiment, the first electrode pad 32 formed in the uppermost layer (fourth layer) and the second electrode pad 34 formed in one lower layer (third layer) are viewed from the substrate normal direction. The first electrode pad 32 and the second electrode pad 34 are connected to each other by a plurality of vias 36. The first electrode pad 32 and the second electrode pad 34 are made of, for example, a single aluminum layer (thickness: about 0.5 μm to 1.0 μm, for example), and the via 36 is made of, for example, tungsten. . A power supply wiring 42 and a lowermost layer wiring 44 are formed below the first electrode pad 32 and the second electrode pad 34, and a part of the first electrode pad 32 is exposed on the uppermost layer of the insulating film 140. Thus, the protective film 124 is formed. When the input / output cells 120 are arranged adjacent to the outer periphery of the semiconductor chip 110, the power supply wiring (second layer) 42 is formed in a ring shape so as to surround the outer periphery of the chip. A lowermost layer wiring 44 that is a first layer in the input / output circuit is formed under the power supply wiring 42, and a diffusion layer including a transistor or the like is formed on the lower surface of the lowermost layer wiring layer 44. . The lowermost wiring layer 44 is electrically connected to the second electrode pad 34 through the lead wiring part 46.

ここでビア３６の配置は、図１（ａ）に示すように、第１電極パッド３２の端子面に形成されている外部接続用電極としてのバンプＢの径に応じた環状に配列されている。図２はバンプＢの形成が終わった状態の半導体装置を示している。   Here, the vias 36 are arranged in an annular shape corresponding to the diameter of the bump B as an external connection electrode formed on the terminal surface of the first electrode pad 32 as shown in FIG. . FIG. 2 shows the semiconductor device in a state where the formation of the bumps B is finished.

図１（ｂ）では、半導体基板（例えばＳｉ基板）上に形成された４層構造の配線構造を示し、その配線構造の下の拡散層（素子形成領域）は示していない。なお、図１（ｂ）の構成に限定されず、２層以上の配線構造であれば適用可能であり、勿論、５層以上の配線構造にも好適に適用可能である。   FIG. 1B shows a four-layer wiring structure formed on a semiconductor substrate (for example, a Si substrate), and does not show a diffusion layer (element formation region) under the wiring structure. Note that the present invention is not limited to the configuration shown in FIG. 1B, and can be applied to any wiring structure having two or more layers, and of course, can also be suitably applied to a wiring structure having five or more layers.

さらに詳しく説明する。
図１（ｂ）はキャピラリツール２により金属ボール３１を第１電極パッド３２の端子面１３に押し付け、超音波振動を与えることによって、金属ボール３１を変形させながら第１電極パッド３２の端子面と結合させる工程を示している。キャピラリツール２の形状と押し付け力とで決まるバンプＢの台座部分の内径をＤ１とした場合、バンプＢの台座部分の内径の直下位置に複数のビア３６が環状に並ぶように、複数のビア３６の配列されている直径Ｄ２は、Ｄ２＝Ｄ１に設定されている。ビア３６の断面形状はデザインルール上許容される最小の寸法（例えば、０．４μｍ程度）にされており、各ビア３６の間隔は例えば１〜２μｍ程度である。ビア３６の長さ（高さ）は、第１電極パッド３２と第２電極パッド３４との間に位置する絶縁膜１４０の厚さと同じであり、例えば１．０μｍ程度である。 This will be described in more detail.
In FIG. 1B, the metal ball 31 is pressed against the terminal surface 13 of the first electrode pad 32 by the capillary tool 2 and ultrasonic vibration is applied to deform the metal ball 31 and the terminal surface of the first electrode pad 32. The process to combine is shown. When the inner diameter of the pedestal portion of the bump B determined by the shape of the capillary tool 2 and the pressing force is D1, the plurality of vias 36 are arranged so that the plurality of vias 36 are arranged in a ring shape immediately below the inner diameter of the pedestal portion of the bump B. Are arranged such that D2 = D1. The cross-sectional shape of the via 36 is set to the minimum dimension (for example, about 0.4 μm) allowed by the design rule, and the interval between the vias 36 is, for example, about 1 to 2 μm. The length (height) of the via 36 is the same as the thickness of the insulating film 140 located between the first electrode pad 32 and the second electrode pad 34, and is about 1.0 μm, for example.

この構成によると、一つのビアの大きさを従来と同じとした場合に、従来よりも数少ないビアを設けるだけで、バンプＢの形成時の衝撃荷重や金属細線の引き千切り時の引張り力を適度に分散させることができ、拡散層（素子形成領域）上方に第１電極パッド３２と第２電極パッド３４が形成されていても、配線部や拡散素子に加わる内部応力を緩和してダメージの発生を抑制することができるので、チップサイズの縮小を図りながら、信頼性を向上させた半導体装置１００を実現できる。   According to this configuration, when the size of one via is the same as that of the conventional one, only a few vias are provided, and the impact load at the time of forming the bump B and the tensile force at the time of shredding the fine metal wire are moderate. Even if the first electrode pad 32 and the second electrode pad 34 are formed above the diffusion layer (element formation region), the internal stress applied to the wiring portion and the diffusion element is relieved to generate damage. Therefore, the semiconductor device 100 with improved reliability can be realized while reducing the chip size.

なお、Ｄ２＝Ｄ１の場合を説明したが、バンプＢの外周部に沿って環状に複数のビア３６を配列し、Ｄ２がＤ１よりも僅かに大きい
Ｄ２ ＞ Ｄ１
の場合にも同様の効果を期待できる。具体的には、複数のビア３６の配列されている直径Ｄ２は、少なくともバンプＢが電極３２と接触する外形部分から、キャピラリツール２の内径に相当する部分までの間に設定されればよい。 Although the case of D2 = D1 has been described, a plurality of vias 36 are arranged in a ring shape along the outer periphery of the bump B, and D2 is slightly larger than D1. D2> D1
The same effect can be expected in the case of. Specifically, the diameter D <b> 2 in which the plurality of vias 36 are arranged may be set between at least the outer portion where the bump B contacts the electrode 32 and the portion corresponding to the inner diameter of the capillary tool 2.

（実施の形態２）
図３は本発明の（実施の形態２）を示す。
（実施の形態１）の図１（ａ）では、複数のビア３６を直径Ｄ２の円周上に配列したが、（実施の形態２）ではこの具体的な配列が異なっている。その他は（実施の形態１）と同じである。 (Embodiment 2)
FIG. 3 shows (Embodiment 2) of the present invention.
In FIG. 1A of (Embodiment 1), the plurality of vias 36 are arranged on the circumference of the diameter D2, but this specific arrangement is different in (Embodiment 2). Others are the same as (Embodiment 1).

図３（ａ）では、複数のビア３６を、バンプＢの径に応じた直径Ｄ２の円周の外周側と内周側に交互に配設している。
図３（ｂ）では、複数のビア３６の一部をバンプＢの径に応じた直径Ｄ２の第１の環状に配列し、前記第１の環状の内側にビア３６の残りを配設している。 In FIG. 3A, a plurality of vias 36 are alternately arranged on the outer peripheral side and the inner peripheral side of the circumference having a diameter D2 corresponding to the diameter of the bump B.
In FIG. 3B, a part of the plurality of vias 36 is arranged in a first annular shape having a diameter D2 corresponding to the diameter of the bump B, and the remainder of the vias 36 is disposed inside the first annular shape. Yes.

図３（ｃ）では、複数のビア３６の一部をバンプＢの径に応じた直径Ｄ２の円周上に環状に配列し、前記第１の環状の外側の面積の比較的広い領域にビア３６の残りを配設している。   In FIG. 3C, a part of the plurality of vias 36 are annularly arranged on the circumference of the diameter D2 corresponding to the diameter of the bump B, and the vias are formed in a relatively wide area outside the first annular area. The remainder of 36 is arranged.

図３（ｄ）では、複数のビア３６の一部をバンプＢの径に応じた直径Ｄ２の円周上に環状に配列し、前記第１の環状の外側の面積の比較的広い領域と、前記第１の環状の内側にビア３６の残りを配設している。   In FIG. 3D, a part of the plurality of vias 36 is annularly arranged on the circumference of the diameter D2 corresponding to the diameter of the bump B, and a relatively wide area outside the first annular region, The remainder of the via 36 is disposed inside the first annular shape.

この図３（ａ）〜図３（ｄ）の何れの場合にも、バンプＢの形成時の衝撃荷重や金属細線の引き千切り時の引張り力を適度に分散させることができ、拡散層（素子形成領域）上方に第１電極パッド３２と第２電極パッド３４が形成されていても、配線部や拡散素子に加わる内部応力を緩和してダメージの発生を抑制することができるので、チップサイズの縮小を図りながら、信頼性を向上させた半導体装置１００を実現できる。   In any of the cases shown in FIGS. 3A to 3D, the impact load at the time of forming the bump B and the tensile force at the time of cutting the thin metal wire can be appropriately dispersed. Even if the first electrode pad 32 and the second electrode pad 34 are formed above the formation region), it is possible to relieve internal stress applied to the wiring portion and the diffusion element and suppress the occurrence of damage. The semiconductor device 100 with improved reliability can be realized while reducing the size.

上記の各実施の形態では外部接続用電極がスタッドバンプの場合を例に挙げて説明したが、半導体チップの端子面と基板とをワイヤーボンディングする半導体パッケージにおいても本発明は効果的であり、外部接続用電極にはワイヤーボンディング線の一端を半導体チップの端子面に押し付けて形成される接続点も含まれている。   In each of the above embodiments, the case where the external connection electrode is a stud bump has been described as an example. However, the present invention is also effective in a semiconductor package in which the terminal surface of the semiconductor chip and the substrate are wire-bonded. The connection electrode includes a connection point formed by pressing one end of the wire bonding line against the terminal surface of the semiconductor chip.

半導体装置や同様の実装技術で組み立てられている各種センサなどの信頼性の向上に寄与できる。   This contributes to improving the reliability of various sensors assembled with semiconductor devices and similar mounting technologies.

本発明の半導体装置の（実施の形態１）の要部の平面図と断面図Plan view and cross-sectional view of essential parts of (Embodiment 1) of the semiconductor device of the present invention 同実施の形態の断面図Cross-sectional view of the same embodiment 本発明の半導体装置の（実施の形態２）の要部の平面図The top view of the principal part of (Embodiment 2) of the semiconductor device of this invention 従来の半導体装置を模式的に示す平面図と断面図A plan view and a cross-sectional view schematically showing a conventional semiconductor device 一般的なスタッドバンプの形成工程図Typical stud bump formation process diagram 別の従来例の断面図Sectional view of another conventional example 更に別の半導体装置の断面図Sectional view of yet another semiconductor device

符号の説明Explanation of symbols

Ｂ バンプ（外部接続用電極）
Ｄ２ 複数のビア３６の配列の直径
Ｄ１ バンプ台座部分の内径
３０ 積層ビア構造
３１ 金属ボール
３２ 第１電極パッド
３４ 第２電極パッド
３６ ビア
４２ 電源配線
４４ 最下層配線
４６ 引き出し配線部
５０ 半導体チップ外周方向
１００ 半導体装置
１１０ 半導体チップ
１１２ 内部回路
１１４ 入出力回路
１２４ 保護膜
１４０ 絶縁膜 B Bump (External connection electrode)
D2 Diameter of arrangement of a plurality of vias D1 Inner diameter 30 of bump pedestal portion Laminated via structure 31 Metal ball 32 First electrode pad 34 Second electrode pad 36 Via 42 Power supply wiring 44 Lowermost layer wiring 46 Lead-out wiring section 50 Peripheral direction of semiconductor chip 100 Semiconductor Device 110 Semiconductor Chip 112 Internal Circuit 114 Input / Output Circuit 124 Protective Film 140 Insulating Film

Claims (4)

内部回路と外部回路との電気接続用の入出力パッドを、端子面またはその上層にスタッドバンプが形成される第１電極パッドと、前記第１電極パッドの下層に位置する配線層から形成される第２電極パッドと、前記第１電極パッドと前記第２電極パッドとの間に位置する絶縁膜中に形成され前記第１電極パッドと前記第２電極パッドとを接続する複数のビアとを設けた半導体装置であって、
第１電極パッドの端子面またはその上層に形成されたスタッドバンプを有し、複数の前記ビアを、前記スタッドバンプの前記第１電極パッドと接合される台座部分とその上部の部分との境界の外周の直下のみに、１〜２μｍの間隔で、環状に配列した
半導体装置。 An input / output pad for electrical connection between an internal circuit and an external circuit is formed from a first electrode pad on which a stud bump is formed on a terminal surface or an upper layer thereof, and a wiring layer located below the first electrode pad. A second electrode pad and a plurality of vias formed in an insulating film located between the first electrode pad and the second electrode pad are provided to connect the first electrode pad and the second electrode pad. A semiconductor device,
A stud bump formed on the terminal surface of the first electrode pad or on an upper layer thereof, and a plurality of the vias are connected to a boundary between a pedestal portion bonded to the first electrode pad of the stud bump and an upper portion thereof. A semiconductor device arranged in a ring shape at intervals of 1 to 2 μm just below the outer periphery. 前記ビア径が、デザインルールの最小寸法である請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the via diameter is a minimum dimension of a design rule. 環状に配列した前記ビアの内側に、前記第１電極パッドと前記第２電極パッドとを接続するビアを環状に配設し、かつ、環状に配列した前記ビアの外側の面積が広い領域にも前記第１電極パッドと前記第２電極パッドとを接続するビアを配設した
請求項１または請求項２に記載の半導体装置。 The vias that connect the first electrode pads and the second electrode pads are annularly arranged inside the annularly arranged vias, and the area outside the vias arranged annularly is also large. 3. The semiconductor device according to claim 1, wherein a via for connecting the first electrode pad and the second electrode pad is provided. 4. 内部回路と外部回路との電気接続用の入出力パッドを、端子面またはその上層にスタッドバンプが形成される第１電極パッドと、前記第１電極パッドの下層に位置する配線層から形成される第２電極パッドと、前記第１電極パッドと前記第２電極パッドとの間に位置する絶縁膜中に形成され前記第１電極パッドと前記第２電極パッドとを接続する複数のビアとを設けた半導体装置であって、
複数の前記ビアを、前記スタッドバンプの前記第１電極パッドと接合される台座部分とその上部の部分との境界の外周の直下の円の外周側と内周側にのみ交互に配設した
半導体装置。 An input / output pad for electrical connection between an internal circuit and an external circuit is formed from a first electrode pad on which a stud bump is formed on a terminal surface or an upper layer thereof, and a wiring layer located below the first electrode pad. A second electrode pad and a plurality of vias formed in an insulating film located between the first electrode pad and the second electrode pad are provided to connect the first electrode pad and the second electrode pad. A semiconductor device,
A semiconductor in which a plurality of the vias are alternately arranged only on the outer peripheral side and the inner peripheral side of the circle immediately below the outer periphery of the boundary between the base portion joined to the first electrode pad of the stud bump and the upper portion thereof apparatus.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH06204283A (en) * 1992-09-18 1994-07-22 Lsi Logic Corp Bonding pad for semiconductor
JPH08293523A (en) * 1995-02-21 1996-11-05 Seiko Epson Corp Semiconductor device and its manufacture
JP2000058583A (en) * 1998-08-06 2000-02-25 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204283A (en) * 1992-09-18 1994-07-22 Lsi Logic Corp Bonding pad for semiconductor
JPH08293523A (en) * 1995-02-21 1996-11-05 Seiko Epson Corp Semiconductor device and its manufacture
JP2000058583A (en) * 1998-08-06 2000-02-25 Fujitsu Ltd Semiconductor device

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