JP4093165B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP4093165B2
JP4093165B2 JP2003337194A JP2003337194A JP4093165B2 JP 4093165 B2 JP4093165 B2 JP 4093165B2 JP 2003337194 A JP2003337194 A JP 2003337194A JP 2003337194 A JP2003337194 A JP 2003337194A JP 4093165 B2 JP4093165 B2 JP 4093165B2
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semiconductor integrated
integrated circuit
electrode pad
circuit device
insulating interlayer
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JP2005108954A (en
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賢治 植田
忠昭 三村
毅 濱谷
篤人 水谷
和弘 石川
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

本発明は、半導体集積回路装置の電極パッドの下地における配線構造に関するものであり、特に配線プロセスの微細化に対応するため、複数層の下地の構成を最適化した高信頼性の半導体集積回路装置に関する。   BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure in an electrode pad base of a semiconductor integrated circuit device, and more particularly, a highly reliable semiconductor integrated circuit device having an optimized configuration of a plurality of layers of base in order to cope with miniaturization of a wiring process. About.

図３は、従来の半導体集積回路装置の一般的な電極パッドの下地における配線構造を示す断面図の概略である。図３に示すように、半導体集積回路装置の電極パッドは２層構造で、電極パッド１ａ、１ｂは回路素子３や内層回路配線５ａ、５ｂ、５ｃなどが多層に構成されている内部回路配線エリアの外周部に設けられており、電極パッド１ａ、１ｂの直下には回路素子３や内層回路配線５ａ、５ｂ、５ｃは設けられておらず、絶縁層間膜（例えば、ＳｉＯＮやＴＥＯＳ膜など）４ａ、４ｂ、４ｃ、４ｄのみとなっている。ここで、半導体集積回路装置の上面には、ＳｉＮ（ナイトライド）膜２が形成されており、電極パッド１ａ、１ｂには、キャピラリー９により、Ａｕワイヤ７がワイヤボンディングされる。   FIG. 3 is a schematic cross-sectional view showing a wiring structure under a general electrode pad of a conventional semiconductor integrated circuit device. As shown in FIG. 3, the electrode pad of the semiconductor integrated circuit device has a two-layer structure, and the electrode pads 1a and 1b are internal circuit wiring areas in which circuit elements 3, inner layer circuit wirings 5a, 5b, 5c, etc. are formed in multiple layers. The circuit element 3 and the inner layer circuit wirings 5a, 5b, and 5c are not provided immediately below the electrode pads 1a and 1b, and an insulating interlayer film (for example, SiON or TEOS film) 4a is provided. 4b, 4c, 4d only. Here, a SiN (nitride) film 2 is formed on the upper surface of the semiconductor integrated circuit device, and an Au wire 7 is wire-bonded to the electrode pads 1 a and 1 b by a capillary 9.

さらに、最近では、半導体集積回路装置自身の面積を小さくするという要望から、電極パッド１ａ、１ｂを回路素子３や内層回路配線５ａ、５ｂ、５ｃ上に設けることで半導体集積回路装置自身の面積を有効に使う手法が広まりつつある（例えば、特許文献１参照）。
特開平３−１３１１０４４号公報 Furthermore, recently, in order to reduce the area of the semiconductor integrated circuit device itself, the area of the semiconductor integrated circuit device itself can be reduced by providing the electrode pads 1a and 1b on the circuit elements 3 and the inner layer circuit wirings 5a, 5b and 5c. Methods that are used effectively are becoming widespread (see, for example, Patent Document 1).
JP-A-3-1311044

従来の半導体集積回路装置では、半導体集積回路装置自体の高機能化などにより、外部と接続する電極パッド数が増加することが予想され、必然的に半導体集積回路装置の面積が大きくなるという問題があった。一般的には、この課題を解決する手法として、電極パッドの配列のピッチを１００μｍ、８０μｍと縮めることにより、半導体集積回路装置の面積増大を抑制してきたが、６０μｍ以下の電極パッドとなると、プローブ検査やワイヤボンディングの関係上、電極パッドが長方形となり、半導体集積回路装置の面積増大が総合的には抑制できなくなってきている。   In the conventional semiconductor integrated circuit device, the number of electrode pads connected to the outside is expected to increase due to the high functionality of the semiconductor integrated circuit device itself, which inevitably increases the area of the semiconductor integrated circuit device. there were. In general, as a technique for solving this problem, an increase in the area of the semiconductor integrated circuit device has been suppressed by reducing the pitch of the electrode pad array to 100 μm and 80 μm. However, when the electrode pad is 60 μm or less, In view of inspection and wire bonding, the electrode pads are rectangular, and the increase in the area of the semiconductor integrated circuit device cannot be suppressed comprehensively.

一方で、半導体集積回路装置の面積増大の抑制として、回路素子や内層回路配線の上に電極パッドを形成するエリアパッドも考えられてきている。しかしながら、回路素子や内層回路配線上に電極パッドを設けた場合、検査におけるプローブや外部端子との接続のためのワイヤボンディングを行なった場合に、プローブ針の静荷重やワイヤボンディング時の超音波エネルギによって、電極パッドの下地の絶縁層間膜や内層回路配線、回路素子にマイクロクラックなどの損傷を与え、半導体集積回路装置の品質に大きな影響を与える。   On the other hand, an area pad for forming an electrode pad on a circuit element or inner layer circuit wiring has been considered as a suppression of an increase in the area of the semiconductor integrated circuit device. However, when electrode pads are provided on circuit elements or inner layer circuit wiring, when wire bonding is performed for connection to probes or external terminals in inspection, the probe needle is subjected to static load or ultrasonic energy during wire bonding. As a result, the insulating interlayer film, the inner layer circuit wiring, and the circuit element underlying the electrode pad are damaged by micro cracks and the quality of the semiconductor integrated circuit device is greatly affected.

また、設計変更などにより、パッド位置が変更になった場合、電極パッド直下の回路素子や内部回路変更とのポジショニングも変更する必要性が発生し、それに伴うマスクや設計変更に要する工数が増大するという課題があった。   In addition, when the pad position is changed due to a design change, it is necessary to change the positioning of the circuit element directly under the electrode pad and the internal circuit change, and the man-hours required for the mask and the design change associated therewith increase. There was a problem.

前記、半導体集積回路装置の面積増大の抑制のひとつである回路素子や内層回路配線の上に電極パッドを形成したときの課題を解決するために、本発明の半導体集積回路装置の電極パッドの下地配線構造は以下のような構成を有している。   In order to solve the problem when the electrode pad is formed on the circuit element or inner layer circuit wiring which is one of the suppression of the area increase of the semiconductor integrated circuit device, the base of the electrode pad of the semiconductor integrated circuit device of the present invention The wiring structure has the following configuration.

本発明の半導体集積回路装置は、電極パッドの下部において、絶縁層間膜を介して少なくとも２階層以上の内部回路配線を有し、前記電極パッドの直下の第１層にあたる前記内部回路配線が、半導体集積回路装置の外周部で、すべての前記電極パッドの直下を含む電極パッド幅以上のリング状領域に形成されていないことを特徴とする。   The semiconductor integrated circuit device of the present invention has at least two levels of internal circuit wiring below the electrode pad via an insulating interlayer, and the internal circuit wiring corresponding to the first layer immediately below the electrode pad is a semiconductor In the outer peripheral portion of the integrated circuit device, it is not formed in a ring-shaped region having a width equal to or larger than the electrode pad width including immediately below all the electrode pads.

以上のように、本発明の半導体集積回路装置は、電極パッドの下部で第１層より下に回路素子や内層回路配線を設けた場合でも、電極パッドの直下の第１層にあたる内部回路配線が、半導体集積回路装置の外周部ですべての電極パッドの直下を含むリング状領域に形成されていないため、リング状に沿って、電極パッドの位置変更が容易にでき、かつ検査におけるプローブやワイヤボンディングを行なった場合においても、絶縁層間膜の厚みを増しているため、絶縁層間膜自身の剛性が高くなり、電極パッドの下地となっている絶縁層間膜に損傷を与えることがない下地配線構造を提供することができ、半導体集積回路装置面積の縮小、高歩留まり、高信頼性が実現でき、半導体集積回路装置を製造コストの上昇をさせることなく作成できる。   As described above, in the semiconductor integrated circuit device of the present invention, even when the circuit element and the inner layer circuit wiring are provided below the first layer below the electrode pad, the internal circuit wiring corresponding to the first layer immediately below the electrode pad is provided. Since the outer periphery of the semiconductor integrated circuit device is not formed in a ring-shaped region including directly under all electrode pads, the position of the electrode pads can be easily changed along the ring shape, and probes and wire bonding in inspection In this case, since the thickness of the insulating interlayer film is increased, the rigidity of the insulating interlayer film itself is increased, and the underlying wiring structure that does not damage the insulating interlayer film underlying the electrode pad is obtained. The semiconductor integrated circuit device area can be reduced, the yield can be increased, the reliability can be realized, and the semiconductor integrated circuit device can be manufactured without increasing the manufacturing cost

以下、本発明の実施の形態について、図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の一実施形態における半導体集積回路装置の電極パッド周辺を示す概略図である。図１（ａ）は半導体集積回路装置の上面図で、半導体集積回路装置の外周部で電極パッドが一重にリング状位置に形成された場合の概略図であり、図１（ｂ）は図１（ａ）に示した半導体集積回路装置における電極パッドでの断面図である。   FIG. 1 is a schematic view showing the periphery of an electrode pad of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 1A is a top view of a semiconductor integrated circuit device, and is a schematic view when electrode pads are formed in a single ring-like position on the outer periphery of the semiconductor integrated circuit device, and FIG. It is sectional drawing in the electrode pad in the semiconductor integrated circuit device shown to (a).

図１（ａ）、（ｂ）に示すように、半導体集積回路装置６はその周囲において、枠状に電極パッド１０が配列された構成となっている。ここでは、電極パッド１０は、ＡＬとＣｕなどのように異なった金属材質の積層で構成された電極パッド１０ａ、１０ｂで構成されている。電極パッド１０上には電気信号を外部に導出するためのＡｕバンプやＡｕワイヤ７が接合される。   As shown in FIGS. 1A and 1B, the semiconductor integrated circuit device 6 has a configuration in which electrode pads 10 are arranged in a frame shape around the semiconductor integrated circuit device 6. Here, the electrode pad 10 is composed of electrode pads 10a and 10b formed of a laminate of different metal materials such as AL and Cu. On the electrode pad 10, an Au bump or an Au wire 7 for leading an electric signal to the outside is bonded.

半導体集積回路装置表面には、ＳｉＮ（ナイトライド）などの保護膜１１が形成され、電極パッド１０を含む半導体集積回路装置の下地には、ここでは、３階層の内部回路配線１５ａ、１５ｂ、１５ｃと回路素子１２が形成され、電極パッド１０、内部回路配線１５ａ、１５ｂ、１５ｃと回路素子１２のそれぞれの間には、ＴＥＯＳもしくはＳｉＯＮなどの材料による絶縁層間膜１３ａ、１３ｂ、１３ｃ、１３ｄが形成されている。内部回路配線１５ａ、１５ｂ、１５ｃはＡＬもしくはＣｕの単体材料で構成されている。   A protective film 11 such as SiN (nitride) is formed on the surface of the semiconductor integrated circuit device, and the base of the semiconductor integrated circuit device including the electrode pad 10 is, here, three layers of internal circuit wirings 15a, 15b, 15c. Insulating interlayer films 13a, 13b, 13c, and 13d made of a material such as TEOS or SiON are formed between the electrode pad 10 and the internal circuit wirings 15a, 15b, and 15c and the circuit element 12, respectively. Has been. The internal circuit wirings 15a, 15b, and 15c are made of a single material of AL or Cu.

図１（ａ）で、半導体集積回路装置の周辺で、電極パッド１０を囲むように２本の枠状・リング状に点線で示した領域８は、電極パッド１０ａ、１０ｂの下地の第１層の内部回路配線１５ｃが配設されていない領域を示す。つまり、その領域には第１層の内部回路配線１５ｃが形成されずに絶縁層間膜１３ｄが形成されている。リング状の領域８の幅は電極パッド１０の幅以上である。図１（ｂ）で、１４は、従来には電極パッド１０の直下に内部回路配線１５ｃが形成されていたが、本発明では、その内部回路配線１５ｃを形成しない状態を示しており、その部分に形成された絶縁層間膜である。   In FIG. 1A, a region 8 indicated by dotted lines in the form of two frames and rings so as to surround the electrode pad 10 around the semiconductor integrated circuit device is a first layer underlying the electrode pads 10a and 10b. The region in which the internal circuit wiring 15c is not provided is shown. That is, the insulating interlayer film 13d is formed in that region without forming the first-layer internal circuit wiring 15c. The width of the ring-shaped region 8 is not less than the width of the electrode pad 10. In FIG. 1B, reference numeral 14 represents a state in which the internal circuit wiring 15c is conventionally formed immediately below the electrode pad 10, but in the present invention, the internal circuit wiring 15c is not formed. It is the insulating interlayer film formed in (1).

このように、電極パッド１０の直下に位置するリング状の領域８に第１層目の内部回路配線１５ｃを形成しないようにすることにより、電極パッド１０の直下の第２層目の内部回路配線１５ｂまでの絶縁層間膜自体の厚みを厚くすることができる。つまり、絶縁層間膜の厚みは、絶縁層間膜１３ｃと絶縁層間膜１３ｄ（絶縁層間膜１４部分を含む）とを合わせて、１０００ｎｍ以上となる。   In this way, by preventing the first-layer internal circuit wiring 15c from being formed in the ring-shaped region 8 located immediately below the electrode pad 10, the second-layer internal circuit wiring immediately below the electrode pad 10 is formed. It is possible to increase the thickness of the insulating interlayer film itself up to 15b. That is, the thickness of the insulating interlayer film is 1000 nm or more when the insulating interlayer film 13c and the insulating interlayer film 13d (including the insulating interlayer film 14 portion) are combined.

また、積層された電極パッド１０ａ、１０ｂを合わせた厚みは最低でも１０００ｎｍの厚みを有し、可能であれば、それ以上の厚みに形成される。半導体集積回路装置自身の検査には、一般的には、カンチレバー方式のプローブ針を電極パッド１０ａに接触させ、半導体集積回路装置の検査を行なうが、この時、電極パッド１０ａにはプローブ針の接触により、電極パッド直下の絶縁層間膜１３ｃ、１３ｄにはプローブ針による静荷重が掛かる。このときのプローブ針の荷重は、プローブ針１本あたり約４〜６ｇである。この絶縁層間膜１３ｃ、１３ｄの総厚が小さいと、プローブ針の静荷重に耐えることができず、絶縁層間膜１３ｃ、１３ｄにマイクロクラックなどのダメージを生じさせることになる。   Further, the total thickness of the stacked electrode pads 10a and 10b has a thickness of at least 1000 nm, and if possible, it is formed to a thickness greater than that. For the inspection of the semiconductor integrated circuit device itself, generally, the cantilever type probe needle is brought into contact with the electrode pad 10a to inspect the semiconductor integrated circuit device. At this time, the electrode pad 10a is contacted with the probe needle. As a result, a static load by the probe needle is applied to the insulating interlayer films 13c and 13d immediately below the electrode pads. The load of the probe needle at this time is about 4 to 6 g per probe needle. If the total thickness of the insulating interlayer films 13c and 13d is small, it cannot withstand the static load of the probe needle, and damage such as microcracks is caused in the insulating interlayer films 13c and 13d.

また、この電極パッド１０ａ、１０ｂに熱超音波併合型のワイヤボンディングを用いて、Ａｕワイヤ７を接合させる場合、Ａｕワイヤ７の先端にボールを形成し、１５０〜２５０℃の高温下で超音波振動を掛けながら、キャピラリーツールでＡｕワイヤ７のボールを接続する。この時、ワイヤボンディング時の超音波エネルギが、下地の絶縁層間膜に伝達するのであるが、電極パッド１０ａ、１０ｂの直下の絶縁層間膜１４の層に内層回路配線を有していないため、超音波エネルギによって起こる内層回路配線のエッジ部の応力集中が発生しない。また、内層回路配線１５ｂのエッジに対しては、超音波エネルギが絶縁層間膜１３ｄ、１４、１３ｃを伝播する間に減衰されるため、マイクロクラックなどのダメージを生じさせるだけの応力集中を避けることができる。   Further, when the Au wire 7 is bonded to the electrode pads 10a and 10b by using thermo-ultrasonic combined wire bonding, a ball is formed at the tip of the Au wire 7 and ultrasonic waves are generated at a high temperature of 150 to 250 ° C. The ball of the Au wire 7 is connected with a capillary tool while applying vibration. At this time, the ultrasonic energy at the time of wire bonding is transmitted to the underlying insulating interlayer film, but since there is no inner layer circuit wiring in the layer of the insulating interlayer film 14 immediately below the electrode pads 10a, 10b, Stress concentration at the edge portion of the inner circuit wiring caused by the sonic energy does not occur. Further, since the ultrasonic energy is attenuated while propagating through the insulating interlayer films 13d, 14 and 13c at the edge of the inner layer circuit wiring 15b, avoid stress concentration that causes damage such as microcracks. Can do.

実験の結果、絶縁層間膜の厚みが５００ｎｍでは電極パッド１０ｂと内部回路配線１５ｂの間でマイクロクラックが１％程度発生するのに対し、絶縁層間膜の厚みを１０００ｎｍにすることにより電極パッド１０ｂと内部回路配線１５ｂの間で、マイクロクラックは確認できなかった。この結果、電極パッド１０の直下に位置するリング状の領域８に第１層目の内部回路配線１５ｃを形成しないようにすることが必要であることがわかる。   As a result of the experiment, about 1% of microcracks occur between the electrode pad 10b and the internal circuit wiring 15b when the thickness of the insulating interlayer film is 500 nm, whereas the thickness of the insulating interlayer film becomes 1000 nm. Microcracks were not confirmed between the internal circuit wirings 15b. As a result, it can be seen that it is necessary not to form the first-layer internal circuit wiring 15 c in the ring-shaped region 8 located immediately below the electrode pad 10.

図１（ｃ）は、電極パッド１０が半導体集積回路装置６の周辺から２重に形成されている場合の半導体集積回路装置の上面図を示し、第１層の内部回路配線１５ｃが配設されていない領域８は、２重の電極パッド１０の領域を含んでリング状となる。   FIG. 1C shows a top view of the semiconductor integrated circuit device in a case where the electrode pads 10 are doubled from the periphery of the semiconductor integrated circuit device 6, and the first layer internal circuit wiring 15c is provided. The region 8 that is not formed includes a region of the double electrode pad 10 and has a ring shape.

図２は、本発明の他の実施形態である半導体集積回路装置の電極パッド周辺の断面図を示したものである。図２は、電極パッドが１層の金属層の場合で、ＡＬかＣｕの単材質で構成された電極パッドの半導体集積回路装置の断面図である。この場合も同様に、電極パッド２０の直下の第１層目の内部回路配線１５ｃを半導体集積回路の外周部のリング状の領域８に形成しない。この時の絶縁層間膜の厚みは、絶縁層間膜１３ｃと絶縁層間膜１３ｄ、内部回路配線１５ｃを形成していない領域の絶縁層間膜１４とを合わせて、１０００ｎｍ以上４０００ｎｍ以下の厚みとする。電極パッド２０の厚みは４００ｎｍ以上１０００ｎｍ以下とする。しかしながら、絶縁層間膜や電極パッドを厚くしすぎても、所望の膜厚形成に時間がかかり、コスト高になったり、厚すぎる場合の技術的、信頼性面的な２次課題が発生したりする場合があるので適宜厚みの範囲を設定する必要があることは言うまでもない。   FIG. 2 is a sectional view of the periphery of an electrode pad of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device having an electrode pad made of a single material of AL or Cu when the electrode pad is a single metal layer. In this case as well, the first-layer internal circuit wiring 15c immediately below the electrode pad 20 is not formed in the ring-shaped region 8 on the outer peripheral portion of the semiconductor integrated circuit. The insulating interlayer film at this time has a thickness of 1000 nm or more and 4000 nm or less including the insulating interlayer film 13c, the insulating interlayer film 13d, and the insulating interlayer film 14 in the region where the internal circuit wiring 15c is not formed. The electrode pad 20 has a thickness of 400 nm to 1000 nm. However, even if the insulating interlayer film and the electrode pad are made too thick, it takes time to form a desired film thickness, resulting in high costs, and technical and reliability secondary problems in the case of being too thick. Needless to say, it is necessary to appropriately set the thickness range.

さらに、半導体集積回路装置の拡散工程においても、電極パッド１０ａ、１０ｂの直下の第１層目の内部回路配線１５ｃを設計上、半導体集積回路の外周部の領域８に形成しないだけであるため、拡散工程の増加やマスクの増加などの必要がなく、製造コストの増加につながるという問題も発生しない。   Furthermore, even in the diffusion process of the semiconductor integrated circuit device, the first-layer internal circuit wiring 15c immediately below the electrode pads 10a and 10b is not designed to be formed in the region 8 on the outer peripheral portion of the semiconductor integrated circuit. There is no need for an increase in the diffusion process and an increase in the mask, and there is no problem that the manufacturing cost increases.

また、第１層目の内部回路配線１５ｃをリング状の領域８に形成しないことにより、電極パッド１０、２０の位置が変更になった場合においても、内部回路配線１３ｄ用のマスクを変更する必要がなく、電極パッド１０、２０用のマスクのみの変更となり、パッド位置の設計変更に対しても容易にすることができる。   Further, by not forming the first layer internal circuit wiring 15c in the ring-shaped region 8, it is necessary to change the mask for the internal circuit wiring 13d even when the positions of the electrode pads 10 and 20 are changed. Therefore, only the mask for the electrode pads 10 and 20 is changed, and the design of the pad position can be easily changed.

なお、内部回路配線を３階層の場合について説明したが、２階層の場合でも同様である。   Although the case where the internal circuit wiring has three layers has been described, the same applies to the case of two layers.

本発明は、微細化に伴い電極パッドの下部に内部回路配線や回路素子を複数層配置しないといけない半導体集積回路装置に利用できる。   The present invention can be used for a semiconductor integrated circuit device in which a plurality of layers of internal circuit wirings and circuit elements must be arranged under the electrode pad as the size is reduced.

本発明の一実施形態の半導体集積回路装置を示す概略図1 is a schematic diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. 本発明の一実施形態の半導体集積回路装置を示す断面図Sectional drawing which shows the semiconductor integrated circuit device of one Embodiment of this invention 従来の半導体集積回路装置を示す断面図Sectional drawing which shows the conventional semiconductor integrated circuit device

符号の説明Explanation of symbols

６ 半導体集積回路装置
７ Ａｕワイヤ
１０、２０ 電極パッド
１１ 保護膜
１２ 回路素子
１３ａ、１３ｂ、１３ｃ、１３ｄ 絶縁層間膜
１５ａ、１５ｂ、１５ｃ 内部回路配線 6 Semiconductor integrated circuit device 7 Au wire 10, 20 Electrode pad 11 Protective film 12 Circuit element 13a, 13b, 13c, 13d Insulating interlayer film 15a, 15b, 15c Internal circuit wiring

Claims (4)

外周部に沿って電極パッドを有し、前記電極パッドの下部において、絶縁層間膜を介して少なくとも２階層以上の内部回路配線と回路素子とを有する半導体集積回路装置であって、
前記電極パッドの下部の第１層にあたる前記内部回路配線が、前記半導体集積回路装置の外周部で、すべての前記電極パッドの直下を含む前記電極パッドの幅以上のリング状領域に形成されておらず、前記電極パッドの下部の第２層以下のいずれかの階層にあたる前記内部回路配線は、前記電極パッドの直下に形成されていることを特徴とする半導体集積回路装置。 A semiconductor integrated circuit device having an electrode pad along an outer periphery, and having at least two layers of internal circuit wiring and circuit elements via an insulating interlayer film below the electrode pad,
The internal circuit wiring corresponding to the first layer under the electrode pad is formed in a ring-shaped region having a width equal to or larger than the width of the electrode pad, including immediately below all the electrode pads, in the outer peripheral portion of the semiconductor integrated circuit device. The semiconductor integrated circuit device is characterized in that the internal circuit wiring corresponding to any one of the second and lower layers below the electrode pad is formed immediately below the electrode pad. 前記電極パッドは、前記半導体集積回路装置の外周部に沿って、少なくとも２列以上形成されており、
前記電極パッドの下部の第１層にあたる前記内部回路配線は、複数の前記電極パッドの列幅以上のリング状領域に形成されていないことを特徴とする請求項１に記載の半導体集積回路装置。 The electrode pads are formed in at least two rows along the outer periphery of the semiconductor integrated circuit device,
2. The semiconductor integrated circuit device according to claim 1, wherein the internal circuit wiring corresponding to the first layer below the electrode pad is not formed in a ring-shaped region having a width equal to or larger than a column width of the plurality of electrode pads. 前記絶縁層間膜の材質はＴＥＯＳもしくはＳｉＯＮからなり、前記内部回路配線の配線材料はＡＬもしくはＣｕで構成されていることを特徴とする請求項１または２に記載の半導体集積回路装置。 3. The semiconductor integrated circuit device according to claim 1, wherein the insulating interlayer film is made of TEOS or SiON, and the wiring material of the internal circuit wiring is made of AL or Cu. 前記電極パッドの厚みは４００ｎｍ以上１０００ｎｍ以下の範囲であり、前記電極パッドの直下の前記絶縁層間膜の厚みは１０００ｎｍ以上４０００ｎｍ以下で構成されていることを特徴とする請求項１から３にいずれかに記載の半導体集積回路装置。 4. The electrode pad according to claim 1, wherein the thickness of the electrode pad is in a range of 400 nm to 1000 nm, and the thickness of the insulating interlayer immediately below the electrode pad is 1000 nm to 4000 nm. A semiconductor integrated circuit device according to 1.
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