JPS62183134A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor device while utilizing a material having good resistance to corrosion, by providing a semiconductor chip with external electrodes seperately from probe testing electrodes while forming these two kinds of electrodes of different materials. CONSTITUTION:Each bonding pad 15 as an external electrode comprises an insulation film 13 of silicon nitride on which a titanium layer 15A, a copper layer 15B and a solder layer 15C are superposed one after another in that order. The copper layer 15B prevents abnormal reaction between the solder layer 15C and the titanium layer 15A while the solder layer 15C improves resistance to corrosion of the bonding pad 15. In order to perform probe tests, probe testing pads 10P consisting of an aluminum layer are arranged on a field insulation film 2 in the peripheral region of substrate 1. A conducting layer 10A is formed so as t have one end extended to below the bonding pad 15 and the other end formed integrally with the probe testing pad 10P. Accordingly, the bonding pad 15, which is a conducting layer located above the probe testing pad 10P, can be arranged in any position on the chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to electrodes of a semiconductor device.

[Conventional technology]

It has been considered to directly mount a chip such as a microcomputer or memory on a printed circuit board or the like to form a module. The chip and the wiring on the substrate must be electrically connected by leads or external leads such as bonding wires. For this purpose, (bonding) pads are provided on the chip as external terminals.

An example of mounting a chip directly on a printed circuit board is shown in, for example, Nikkei Electronics, published by Nikkei McGraw-Hill, March 2, 1981, pp. 138-140.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered the first problem as a result of studying the connection between pads on a chip and wiring on a substrate. That is, at the final stage of the wafer manufacturing process, a chip is subjected to a probe test to measure its electrical dynamic characteristics and static characteristics.

Probe testing is typically done using bonding pads placed around the periphery of the chip. As a result, the conductive layer constituting the bonding pad may be significantly damaged, resulting in a defective connection with the lead or bonding wire.

Furthermore, according to the inventor's study, in order to achieve high integration or increase the adhesion area between pads and leads or bonding wires, it is necessary to place pads on areas (active areas) where semiconductor elements such as MOSFETs are formed. It is effective to form the However, there is a problem in that during the above-mentioned probe inspection, the underlying semiconductor element may be damaged.

An object of the present invention is to provide highly reliable electrical connection between a semiconductor chip and external leads.

Another object of the present invention is to form external terminals of a semiconductor chip on a semiconductor element within the semiconductor chip.

Another object of the present invention is to provide a technique that allows external electrodes of a semiconductor chip to be placed at arbitrary positions on the semiconductor chip.

Another object of the present invention is to provide a technique that allows external electrodes of a semiconductor chip to be formed after inspection.

Another object of the present invention is to provide a technique for improving the electrical reliability of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to clarify the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the external electrodes (terminals) of the semiconductor chip are provided separately from the probe testing electrodes, and these two electrodes are made of different materials.

[Effect]

According to the above-described means, the external electrode can be formed of a material that is difficult to corrode and is different from the electrode for probe testing, so that reliability can be improved.

The configuration of the present invention will be explained below along with examples.

[Example I]

FIG. 1 is a cross-sectional view of the chip mainly showing bonding pads, and FIG. 2 is a plan view of the chip mainly showing bonding pads.

As shown in FIG. 1, a field insulating film 2 made of a silicon oxide film is provided on the surface of a semiconductor substrate 1 made of P-type single crystal silicon. A p-type channel stopper region 3 is provided under the field insulating film 2. The portion of the surface of the substrate 1 that is not covered with the field insulating film 2 is MISFE.
This is an element area for providing a semiconductor element such as T. M.I.
The SFET has a gate electrode 4 made of a polycrystalline silicon film,
A gate insulating film 5 made of a silicon oxide film and a source.

It consists of an n-type semiconductor region 6 which is a drain region.

Note that the gate electrode 4 is not limited to a polycrystalline silicon film; for example, Mo, W,
It may be a two-layer film provided with a film of a high melting point metal such as Ta or Ti or a silicide film thereof. Further, the gate electrode 4 may be formed only of the high dew point metal film or its silicide film.

An n-type semiconductor region 6A is provided in the periphery of the chip (substrate 1) to be used as a conductive layer for applying a predetermined potential to the substrate 1, for example, 0 [V], which is the circuit ground potential Vss. Further outside the n4 type semiconductor region 6A is a dicing region (also referred to as a scribe region) 7 for dividing the substrate 1 in a wafer state into individual chips. Although the n-type semiconductor region 6B is also formed in the dicing region 7,
This n''' type semiconductor region 6B is the source of the MISFET,
This was formed when forming the n-type semiconductor region 6, which is the drain region.

Gate electrode 4. An insulating film 8 made of phosphosilicate glass (PSG) or the like is provided on the field insulating film 2 or the like. The gate insulating film 5 and insulating film 8 above the source and drain regions, that is, the rl' type semiconductor region 6, are selectively removed to form a connection hole 9. A conductive layer IO made of an aluminum layer is connected to the n1 type semiconductor region 6, which is the source and drain region, through the connection hole 9. This conductive layer 1° has a power supply potential Vc,
c, for example, 5 [■] or a circuit ground potential Vss, for example, 0 [v], or semiconductor elements such as MI S FETs are electrically connected.

At the final stage of the manufacturing process, the ffl pneumatic dynamic and static characteristics of the substrate 1 in the wafer state are tested. This test is generally called a probe test. In this embodiment, for the probe test, a probe test pad IOP made of an aluminum layer is placed on the field insulating film 2 at the outer periphery of the chip, that is, the substrate 1. The probe testing pad LOP connects semiconductor elements such as MTSFET,
Also, a conductive flt layer 10 for applying a predetermined potential between semiconductor elements.
It consists of the same aluminum layer. The probe testing pad IOP is the outermost semiconductor element among the semiconductor elements such as MI S FET provided on the substrate l.

an n-type semiconductor region 6 for applying a predetermined potential to the substrate 1;
It is disposed on the field insulating film 2 between A and A. What is the film thickness of the probe testing pad LOP?

It is about 0.8 μml. Probe testing pad IO
P is connected to the n-type semiconductor region 6, which is the source and drain region of the MISFET provided at the outermost periphery, through the connection hole 9A.

In Figure 1, the probe test pad IOP is shown as the first aluminum layer, but the probe test pad LOP constitutes internal circuits such as memory, output buffer, logic gate, input/output amplifier, etc. M I S to do
Among the aluminum wirings connecting semiconductor elements such as FETs, the aluminum layer is made of the same layer as the uppermost aluminum layer wiring.

The probe testing pad LOP and the conductive layer 10 are covered with an insulating film 11 made of a silicon nitride film formed by plasma CVD. The thickness of the insulating film 11 is 1.1 [μml
That's about it. The insulating film 11 also covers the dicing area (scribe area) 7 that is the outermost portion of the substrate 1 .

An opening 12 is formed by selectively removing a portion of the insulating film 11 above the probe testing pad LOP. This frontage 1
The lower part of 2 is the probe testing pad IOP. The lower part of the opening 12, that is, the probe testing pad LO
From P to the n° type semiconductor region 6 which is the source and drain region
Conductivity up to the part connected to y? ! j10A is a wiring for connecting the probe test pad 10P and the MISFET and a bonding pad 15 to be described later. Note that the probe testing pad 10 shown in FIG.
P is connected to the n4 type semiconductor region which is the source and drain region, but some of the multiple stages of probe testing pads 10P are connected to the gate electrode 4.P of the MISFET.
Or a clamp MISFE connected in the form of a resistor or diode that constitutes an input protection circuit (not shown)
It is connected to the n-type semiconductor region of T, etc.

Absolutely! An insulating film 13 made of, for example, a silicon nitride film made of plasma CVI) is provided on the film 511.

The thickness of the insulating film 13 is approximately 1.1 μml.

The insulating film 13 covers the upper surface of the probe testing pad IOP that is completely exposed in the opening 12 .

In this embodiment, the insulating film 13 is placed in the dicing area 7 of the substrate 1.
It is also installed above. Therefore, dicing area 7
is covered with an insulating film 11 and an insulating film 13. That is,
At least the top surface of the substrate l has no exposed portion. Therefore, the finger 17 (see FIG. 3) connected to the bonding pad 15 (described later) will not be short-circuited with the substrate l.

The bonding pad 15, which is an external electrode of the semiconductor device, is constructed by laminating a titanium polishing layer 15A, a copper layer 15B, and a half-EH layer 15C in order from the bottom on an insulating film 13 made of a silicon nitride film. Titanium layer 15A is bonding pad 1
This is to improve the adhesion between the film 5 and the insulating film 13 made of a silicon nitride film. Copper layer 15B is solder layer 15C
This is to prevent an abnormal reaction between the titanium layer 15A and the titanium layer 15A. The solder layer 15C is for improving the corrosion resistance of the bonding pad 15. In addition, the titanium layer 15A
and a conductive layer different from the copper layer 15B between the solder layer 15C,
For example, a palladium layer may be provided. The bonding pad 15 is the uppermost conductive layer of the conductive layers provided on the chip, ie, the substrate l. In this way, by making the bonding pad 15 the uppermost conductive layer on the substrate l.

The bonding pad 15 can be placed at any position on the substrate 1 after the probe test.

The bonding pad 15 is connected to the insulating film 11 and the insulating film 13.
is connected to the upper surface of the conductive layer 10A through a connection hole 14 formed by selectively removing a portion above the end of the conductive layer 10A. Therefore, bonding pad 15 is connected to probe testing pad LOP through conductive layer 10A. Further, the bonding pad 15 is connected to the conductive layer 1
It is connected to the n0 type semiconductor region 6 which is the north and drain region through 0A. Note that, as described above, some of the plurality of probe testing pads LOP are M I S
FET gate electrode 4. It is connected to the clamp MISFET in the form of a resistor or diode forming the input protection circuit.

Therefore, as described later, six bonding pads 15 are provided in this embodiment, and some of these bonding pads 15 are connected to the gate electrode 4 of the MISFET.
The resistive element can also be connected to the n' type semiconductor region of the clamp MI 5FET.

On the other hand, the side and top surfaces of the bonding pads 15 are exposed. That is, no protective film is provided on the bonding pad 15. This is to facilitate the connection between the finger 17 (see FIG. 3) and the bonding pad 15, and to make the overall thickness of the IC card as thin as possible.

As shown in FIG. 2, in this embodiment, a total of 36 probe testing pads IOP are provided, 18 on both sides of the chip, that is, the substrate 1. Note that the arrangement of the probe testing pads IOP is not limited to both sides of the chip. For example, the probe testing pads IOP may be arranged all around the chip 1, that is, along the four sides of the chip 1. Further, the number of probe testing pads IOP is not limited to 36, and may be more than 36 or less than 36.

The probe testing pad 1oP has a square planar pattern. -The length of the sides is approximately 200 [μm]. The planar pattern of the opening 12 on the probe testing pad IOP shown in FIG.
Like the planar pattern of P, it has a square shape.

On the other hand, the bonding pad 15 is connected to the active area of the chip 1, that is, the MIS that constitutes the memory, logic circuit, input/output amplifier, input/output buffer, decoder, etc.
It is constructed on a region where semiconductor elements such as FETs are provided. By configuring the bonding pads 15 on the active region in this manner, the planar pattern of the bonding pads 15 can be enlarged. In this embodiment, the short diameter of the bonding pad 15 is 1 [mm1P1
It has a rectangular shape with a length of 1.5 mm and a major axis of about 1.5 mm.

That is, the bonding pad 15 is made larger than the probe testing pad LOP. Therefore, since there is a large margin for alignment between the finger 17 (see FIG. 3) and the bonding pad 15, the connection between the finger 17 and the bonding pad 15 can be easily achieved.

Further, since the contact area between the fingers 17 and the bonding band 15 increases, the reliability of bonding them is improved.

Furthermore, by increasing the size of the bonding pad 15 as described above, even if the bonding pad 15 may be tilled, disconnection of the bonding pad 15 can be prevented. therefore.

The reliability of semiconductor devices has improved.

Note that the shape of the bonding pad 15 is not limited to a rectangular shape, but may be a square shape or another shape. Further, the size of the bonding pad 15 is not limited to the above value.

In this embodiment, six bonding pads 15 are provided for one chip in addition to the probe testing pads 10P. Each of these six bonding pads 15 is connected to six probe test pads 10P selected from 36 probe test pads IOP through a conductive layer 10A. Note that the layout of the six bonding pads 15 can be changed in various ways.

For example, in FIG. 2, when the rows of probe test pads 10P are arranged in the column direction, three bonding pads 15 are arranged in the row direction, and the three bonding pads 15 arranged in the row direction are arranged in the column direction. It is arranged in two lines. but,
The bonding bands 15 may be arranged three times in the column direction, and the three bonding bands 15 arranged in the column direction may be arranged in two columns in the row direction. That is, the number of bonding pads 15 facing one row of bonding pads 15 may be three.

In FIG. 2, a portion of the bonding pad 15 is formed to protrude laterally, and the protruding portion of the bonding band 15 is connected to the conductive layer 10A through the connection hole 14. However, in order to connect the bonding pad 15 to the conductive layer 10A, as shown in FIG.
It is not necessary to make any part of the image stand out. The conductive layer 10A may be formed so as to go under the bonding pad 15.

The conductive layer 10A extends with the same width from below the connection hole 14 to between the probe testing pads IOP.

As already mentioned, the conductive layer 10A is connected to a semiconductor element such as a MISFET through the connection hole 9A. One end of the conductive layer 10A is formed integrally with the probe testing pad IOP. The conductive FFjIOA is the conductive ff1O shown in FIG. 1, that is, the wiring for connecting the MISFETs, or the power supply potential Vcc,
It extends between the conductive layers 1o to which the circuit ground potential Vss is applied. Therefore, the conductive layer 10A extends over the insulating film 8. The extending pattern of the conductive layer 10A is varied depending on the layout of the bonding pads 15 and which probe testing pad 10P4 the bonding pads 15 are connected to. In addition, Figure 2 shows the first
The conductive layer IO shown in the figure is not shown.

As described above, by forming the bonding pad 15 as a conductive layer above the probe testing pad IOP, the bonding pad 15 can be placed at an arbitrary position on the chip 1.

Here, FIG. 3 shows a cross section of the IC card built into the chip l.

In FIG. 3, 16 is a printed circuit board made of glass epoxy, and has a built-in chip (substrate 1). 17
is a finger (reed) made of copper alloy, for example,
This finger 17 connects the bonding pad 15 of the chip (substrate 1) and the electrode 18 of the printed circuit board 17.

The fingers 17 are attached to the entire surface of the bonding pads 15 of the chip l. The width of the finger 17 is as large as the bonding pad 15, about 1 to 1.5 [mm1]. Therefore, the fingers 17 are not disconnected due to corrosion.

Further, the resistance value does not increase significantly. finger 1
7 is provided by being attached to a tape 19 made of polyimide, for example. 20 is a surface material made of resin, and the chip 1 is sealed with this surface material 20.

As explained using FIG. 2, by making it possible to arbitrarily change the position of the bonding pad 15,
The planar layout or arrangement of the fingers 17 can be easily changed.

Next, a method of manufacturing the probe testing pad 10P and bonding pad 15 in this embodiment will be mainly explained.

4 to 13 are cross-sectional views of the vicinity of the probe testing pad 1OP and the bonding pad 1 bow of the chip 1 in the manufacturing process of this embodiment.

As shown in FIG. 4, a field insulating film 2 and a P-type channel stopper region 3 are formed on a p'' type semiconductor substrate l using a well-known technique.Furthermore, a gate insulating film 5 and a gate electrode 4 are formed using a well-known technique. n which is the source and drain region
A square-shaped semiconductor region 6A for applying a predetermined potential to the square-shaped semiconductor region 6 and the substrate 1 is formed, respectively. When forming the semiconductor regions 6 and 6A, an n° type semiconductor region 6B is formed in the dicing area (scribe area) 7.

Next, as shown in FIG. 5, an insulating film 8 made of a PSG film is formed on the substrate 1 by, for example, CVD. In this embodiment, the insulating film 8 in the dicing area 7 is selectively removed by etching using a resist film.

However, it is not necessarily necessary to remove the insulating film 8 in the dicing area region 7. Next, the insulating film 8 on the n1 type semiconductor region 6, which is the source and drain region, is selectively removed by etching to form connection holes 9, 9A. For example, I(F) and N1(4F) are used as etching solutions.

Furthermore, a mask made of resist is used for etching. This mask is removed after etching.

Next, an aluminum layer is formed on the entire surface of the substrate l by, for example, sputtering, and this aluminum layer is selectively removed by, for example, wet etching using a resist mask to form the probe testing pad 10P and the conductive layer 10.
Form an IOA. The 4-conductor layer 10A is for connecting the probe testing pad IOP and the bonding pad 15 to the n' type semiconductor region 6. The planar pattern of the conductive filOA is shown in FIG. Conductive JWIOA is 3
6 selected from 6 probe testing pads IOP
It is formed integrally with the probe testing pads IOP. The conductive FalOA is formed in a pattern extending between conductive layers 10 that are signal wiring or power wiring. The thickness of the aluminum layer is approximately 0.8 [μm]. As an etching solution, for example, l13PO4-+CH3C0O
Use H+HNO3. The probe testing pad IOP is formed on the field insulating film 2 at the periphery of the chip 1, as described above.

Next, as shown in FIG. 6, a silicon nitride film is formed on the substrate l by, for example, plasma CVD. ,!
11 is formed. The film thickness is approximately 1.1 [μm].

The insulating film 11 also covers the dicing area (also called scribe area) 7. That is, in this embodiment, there is no upper surface of the substrate 1 exposed from the insulating film 11. Next, by plasma etching using, for example, CF4 as an etching gas, the insulating film 11 on the probe testing pad IOP is selectively removed to form an opening 12. Openings 12 are provided for all probe testing pads 10P. A resist film is used as a mask in the etching, and this resist mask is removed after etching. The planar pattern of the opening 12 is square like the probe testing pad IOP shown in FIG. Further, the length of one side of the opening 12 is about 200 [μm] similarly to the probe testing pad IOP.

Next, as shown in FIG. 7, the probe testing pad IO
A probe P of a tester (not shown) is pressed against the surface exposed from the opening 12 of P to carry out a probe test. In this embodiment, as shown in FIG. 2, 18 probe testing pads 10P are provided on both sides of the substrate l.
There are 36 in total. Probes P are applied to all 36 probe testing pads lOP.

Next, as shown in FIG. 8, an insulating film 13 made of a silicon nitride film is formed over the entire surface of the substrate l by, for example, plasma CVD.
form. The upper surface of the probe testing pad IOP exposed through the opening 12 is covered with an insulating film 13. The thickness of the insulating film 13 is approximately 1°l [μm]. Insulating film 1
3 is also formed in a part of the dicing area 7.

Next, as shown in FIG. 9, the insulating film 11 on, for example, the end portion of the conductive layer 10A is etched by, for example, plasma etching.
and 13 are selectively removed to form connection holes 14. Etching uses a resist film as a mask. The etching mask is removed after etching.

Next, as shown in FIG. 10, a titanium layer 15A is formed on the entire surface of the substrate 1 by, for example, sputtering, and a copper layer 15B is further formed on the entire surface of the substrate 1, for example, by sputtering. Note that the copper WJ15B may be a palladium layer (Pd). The titanium layer 15A and the copper layer 15B are connected to the connection hole 1.
4 and is connected to the conductive layer 10A.

Next, as shown in FIG. 11, a resist 1-mask 22 having openings 21 in the pattern of the bonding pads 15 shown in FIG. 2 is formed over the entire surface of the substrate 1. Therefore, the pattern of the openings 21 in the copper layer 15B is exposed.

The number of openings 21 is the same as the number of bonding pads 15,
That is, six pieces are formed. Further, the planar pattern of the frontage 21 is large like the bonding pad 15.

In this embodiment, since the titanium layer 15A and the copper WJ 15B above the connection hole 14 also become part of the bonding pad 15, the opening 21 has a pattern in which the copper layer 15A above the connection hole 14 is exposed.

Next, as shown in FIG. 12, a solder layer 15C is formed on the upper surface of the copper layer 15B exposed through the opening 21 of the resist mask 22 by plating. The planar pattern of the solder layer 15C is a pattern of openings 21.

That is, it is formed in the planar pattern of the bonding pad 15 shown in FIG.

Next, as shown in FIG. 13, the resist 1-mask 22 shown in FIGS. 11 and 12 is removed.

The copper layer 15 covered by the resist mask 22
Expose B. Next, using the solder M15C as an etching mask, the steel layer 15 exposed from the solder [1,5C] is etched.
B is removed by etching. This etching exposes the portions of the titanium layer 15A other than those used as bonding pads 15. The exposed portion of the titanium layer 15A is removed by etching using the solder layer 15C as a mask. When the patterning of the copper layer 15B and the titanium layer 15A is completed, the bonding pad 15 is completed. As described above, the copper layer 15B and the titanium layer 15A are formed in a self-aligned manner with respect to the solder layer 15G.

By forming the bonding pad 15 on the active area where the semiconductor element such as M r S FET is provided, a large bonding pad 15 with a − side of about 1 to 1.5 [mm] can be formed. I can do it.

[Example ■] FIG. 14 is a cross-sectional view of the chip 1 mainly showing the bonding pads 15 of Example ■, and FIG.
FIG.

In Example 2, bonding pad 15 is used during bonding.
This prevents stress from concentrating around the area.

As shown in FIG. 14, similarly to Example I, a field insulating film 2, a substrate 1 made of a p-type single crystal silicon layer,
p-type channel stopper region 3. Gate voltage wA4, gate insulating film 5, n° type semiconductor region 6.6A, 6B1, e.g. P
An insulating film 8 made of SG, a conductive layer 10 made of an aluminum layer, an IOA, and a probe testing pad IOP are provided. Insulating film 11.13. Opening 12. The connection hole 14 is also the same as in Example (2).

The bonding pad 15 of this embodiment has a titanium layer 15A, a copper layer 15B, and a solder layer 15C laminated from the bottom on an insulating film 13, and a copper layer 15A surrounding the solder layer 15C.
A titanium layer 15D is provided on top of the titanium layer 15D. The titanium layer 15A covers the entire bonding pad 15 and the insulating film 13.
This is to improve adhesion to the titanium layer 15A, and is not particularly limited to the titanium layer 15A. copper layer 15
B is for preventing an abnormal reaction between the titanium layer 15A and the solder layer 15C, and is not particularly limited to the copper layer 1513, but may be a palladium layer. Solder layer 1
5C is connected to the finger 17 with the bonding pad 15 of this embodiment exposed, so any material having good corrosion resistance may be used. The upper titanium layer 15D is for preventing the stress applied to the bonding pad 15 when the fingers 17 are connected from being concentrated around the bonding pad 15, that is, at the edge portion. That is, this is to ensure that the stress at the time of connecting the fingers 17 is distributed over substantially the entire bottom surface of the titanium layer 15A without being concentrated on the edge portion of the lower titanium layer 15A.

Therefore, the metal surrounding the solder layer 15G is the titanium layer 15G.
D is not limited to the metal provided between the lower titanium layer 15A and the solder layer 15C (in this example, the copper layer 1
As shown in FIG. 14, the solder layer 15C has good adhesion to the upper titanium layer 15D.
It has a thicker film thickness. At least 1 finger
Before connecting 7, the solder layer 15C is thicker than the titanium layer 15D.

The underlying titanium layer 15A conducts electricity through the connection hole 14! !
Connected to the top of FIOA. Further, the copper layer 15B and the upper titanium layer 150 are provided so as to fill the inside of the connection hole 14.

As shown in FIG. 15, the planar pattern of the bonding pad 15 of this embodiment has a rectangular shape with a short axis of about 1 [mm1] and a long axis of about 1.5 [mm1]. Note that the plane pattern of the bonding pad 15 is not limited to a rectangular shape, and the length of one side of the bonding pad 15 in the plane is not limited. The planar patterns of the lower titanium layer 15A and the copper layer 15B thereon are the same. Further, since the solder layer 15G is surrounded by the titanium layer 150, it is smaller than the lower titanium layer 15A and copper layer 15B by an amount corresponding to the width of the titanium layer 15D. The planar pattern of the solder layer 15C is rectangular as shown in FIG. However, the planar pattern of the solder layer 15C is not limited to a rectangular shape. Since the upper titanium layer LSD has a structure surrounding the solder layer 15C, its planar pattern is ring-shaped.

Next, a method of manufacturing the bonding pad 15 of this embodiment will be explained.

16 to 21 are cross-sectional views or plan views of the chip 1 in the manufacturing process of this embodiment.

As shown in FIG. 16, similarly to Example I, a field insulating film 2, a p-type channel stopper region 3, a gate insulating film 5, a gate electrode 4, an insulating film 8, and a connection hole 9 are provided on a P-type substrate l. .9A, conductive layer 10.10A.

Probe testing pad 1OP, insulating film 11. Insulating film 13
First, the contact hole 14 is formed by selectively removing, for example, the insulation film 11.13 on the end portion of the conductive layer 10A by dry etching or the like. A mask made of a resist film is used for the etching. This mask is removed after etching.

Next, a titanium layer 15A is formed on the entire surface of the substrate 1 by, for example, sputtering. The titanium layer 15A is connected to the upper surface of the conductive layer 10A through the connection hole 14. Next, similarly to the titanium layer 15A, a copper layer 15B is placed on the entire surface of the substrate 1.
Titanium 15D is laminated in order.

Next, as shown in FIG. 18, a resist mask 23 having the same pattern as the bonding pad 15 (see FIG. 15) is applied to the bonding pad 15 on the upper titanium layer 15D.
It is formed in the part where it is provided. The number of resist masks 23 is the same as that of bonding pads 15, that is, 6 in this embodiment.
Form individuals.

Next, first, the upper titanium layer 150 exposed from the resist mask 23 is removed by etching. Further, the copper layer 15B exposed from the resist mask 23 and the lower titanium layer 15A are etched in this order. After this etching, the resist mask 23 is removed.

Next, as shown in FIG. 19, a new resist mask 24 is formed on the substrate l. A planar pattern of this mask 24 is shown in FIG. The mask 24 is formed in a pattern with openings 25 so that the portions of the titanium layer 15D where the solder layer 15G is provided are exposed. Therefore, mask 24
is the solder layer 1 of the remaining upper titanium layer 150.
Create a pattern that does not expose the ring that surrounds 5C. The number of openings 25 is the same as the number of bonding pads 15.

That is, six pieces are formed. Next, the portion of the upper titanium layer 15D exposed from the opening 25 is removed by etching. This etching exposes the copper layer 15B.

Next, as shown in FIG. 21, a solder layer 15C is formed on the copper layer 15B exposed through the opening 25 by plating. The semiconductor layer 15C is formed thicker than the upper titanium layer 15D. After forming the solder layer 15C, the resist mask 24 is removed.

Next, as shown in FIG. 22, the fingers 17 attached to the tape 19 are bonded to the solder layer 15C by, for example, thermocompression bonding.
Connect to the top of the The stress during this connection causes the insulating film 13. Furthermore, the stress is applied to the underlying insulating film 11, but since the solder layer 15G is surrounded by the titanium layer 150, the stress is dispersed over substantially the entire surface of the lower titanium layer 15A. That is, when the fingers 17 are connected, the stress is applied to the lower titanium layer 15.
The cracks are not concentrated around A, that is, at the edge portions. Therefore, when the fingers 17 are connected, cracks or the like do not occur in the insulating film 13 or the insulating film 11 below it.

Further, since stress is not concentrated on the semiconductor element such as the MISFET under the bonding pad 15, destruction or deterioration of the semiconductor element can be prevented.

[Example 2] Figures 23 to 29 are cross-sectional views of the chip 1 in the manufacturing process of Example 2.

In Example m, the probe test pad L is used after the probe test.
By removing the OP, a short circuit between the probe testing pad 10P and the bonding pad 15 is prevented.

As shown in FIG. 23, similarly to Example I, a field insulating film 2. P-type channel stopper region 3. Gate electrode 5, gate insulating film 4. n° type semiconductor region 6.6A
, 6B, an insulating film 8 made of PSG. Conductive layer 10. IOA
, a probe testing pad LOP, a connecting hole 9.9A, a silicon nitride film, and a 7th order forming a silicon nitride film II[11].
The insulating film 11 on all the probe test pads IOP is selectively removed by etching to form an opening 12.

Here, the plane of the chip 1 is shown in FIG.
Figure 4 mainly shows the probe testing pad IOP and conductive layer 10A.
, and other items are not shown. The conductive WIOA extends between the conductive layers 10 that connect semiconductor elements, power supply wiring, and the like.

Next, as shown in FIG. 25, a probe P of a tester (not shown) is applied to the upper surface of the probe testing pad LOP through the opening 12 to perform a probe test. The same number of probes P as the probe testing pads IOP are provided, and are applied to each probe testing pad IOP at the same time. Therefore, the probe P is pressed with a predetermined pressure to prevent poor contact with the probe testing pad 10P. Therefore, although not shown, the portion of the probe testing pad IOP to which the probe P is applied is depressed, while the surrounding area is greatly raised.

As shown in FIG. 26 after the probe test is completed.

The exposed portions of the openings 12 of all probe testing pads LOP are removed by etching. Insulating film 1
1 becomes the etching mask. For this reason, conductive WIO
A is not etched. Probe testing pad IOP
By removing this, when the probe P of the tester is applied to the probe testing pad 10P, the raised portion of the probe testing pad IOP disappears.

Next, as shown in FIG. 27, an insulating film 13 made of a silicon nitride film is formed over the entire surface of the substrate l by, for example, plasma CVD. The thickness of the insulating film 13 is 1.1 [μm]
to a certain degree. The exposed cross section of the probe testing pad LOP is covered with an insulating film 13.

Next, as shown in FIG. 28, the insulating films 11 and 13 on, for example, the ends of the conductive layer 10A are selectively removed by etching to form a connection hole 14. A mask made of a resist film is used for etching. This mask is removed after etching.

Next, as in Example I, a titanium layer 15A is formed on the insulating film 13.
, a bonding pad 15 consisting of a copper layer 15B and a solder layer 15C is formed. The bonding pano 15 is connected to the connection hole 14
It is connected to the conductive layer 10A through the conductive layer 10A.

Here, the plane of the chip 1 is shown in FIG. 29. The probe testing pad IOP was removed in the previous etching process. Note that FIG. 29 mainly shows the bonding pad 15 and the conductive layer 10A.

After forming the bonding pad 15, dicing is performed, and then the finger 17 shown in FIG. 3 is connected to the upper surface of the bonding pad 15, that is, the solder layer 15C, by, for example, thermocompression bonding. When the fingers 17 are connected, the fingers 17 may droop because the fingers 17 and tape 19 are made of flexibility. on the other hand,
As already mentioned, the probe testing pad IOP is greatly deformed by the probe P applied during the probe testing. In other words, it comes to exhibit large irregularities. Therefore, the protruding portion of the probe testing pad 10P is exposed from the insulating films 11 and 13. Therefore, the finger 17 may cause a short circuit between the bonding pad 15 and the probe testing pad LOP to which it should not be connected. However, in this embodiment, since the probe testing pad IOP is removed, the bonding pad 15 and the probe testing pad 10P are removed as described above.
There will be no short circuit.

Note that the probe test pad 10P in Example 2 may also be removed before the probe test, as in the present example.

Further, in Examples I to 2, the insulating films 11 and 13 between the probe testing pads 10P and the bonding pads 15 are silicon nitride films, but a coating film of polyimide or the like may be used. That is, the insulating film 11 may be formed by applying polyimide, and the insulating film 13 made of a silicon nitride film may be provided thereon. Alternatively, the insulating film 11 may be a silicon nitride film, and the insulating film 13 may be formed by applying polyimide. By using a coating film under the bonding pad 15 in this manner, the flatness of the upper surface of the bonding pad 15 can be improved.

According to the new technology disclosed in this application, the following effects can be obtained.

(1) Since the bonding pad is made of a conductive material with good corrosion resistance, the bonding pad will not become disconnected or thin due to corrosion, and the connection between the bonding pad and the finger will not deteriorate. , it is possible to improve the electrical reliability of the semiconductor device.

(2) According to (1) above, since a protective film covering the bonding pad is not required, the height from the bottom surface of the chip to the top surface of the finger can be lowered and the thickness of the IC card can be reduced.

(3) By making the 6 bonding pad a conductive layer above the probe test pad, the bonding pad can be formed after the probe test, so the bonding pad can be placed at any position on the board. . In other words, the degree of freedom in arranging the bonding pads can be increased.

(4), according to (3) above, the bonding pad is
Since the bonding pad can be formed over a so-called active region in which a semiconductor element such as an SFET is provided, the bonding pad can be made large.

(5) By providing a metal layer (titanium layer) to surround the solder layer, which is a component of the bonding pad, stress during finger connection will not be concentrated around the bonding pad, that is, at the edges. , it is possible to prevent damage to the insulating film or the semiconductor element under the bonding pad, thereby improving the reliability of the semiconductor device.

(6) By removing the probe test pad after the probe test, there will be no short circuit between the bonding pad and the probe test pad to which it should not be connected, improving the electrical reliability of the semiconductor device. can be achieved.

(7) By arranging the probe testing pads on the field insulating film around the chip, the tester's probes will not damage semiconductor elements such as MIS FETs, improving the reliability of probe testing and semiconductor devices. It is possible to improve sexual performance.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

By forming the external electrode separately from the probe testing electrode, a material with excellent corrosion resistance can be used, and reliability can be improved.

[Brief explanation of drawings]

1 to 13 are plan views or cross-sectional views of the chip of Example I, FIGS. 14 to 22 are plan views or cross-sectional views of the chip of Example H, and FIGS. 15 to 29 are plan views or cross-sectional views of the chip of Example I. FIG. 3 is a bottom view or a cross-sectional view of the chip (2). DESCRIPTION OF SYMBOLS 1... Substrate, 2... Field insulating film, 3... Channel stopper, 4... Glue electrode, 5... Gate insulating film, 6.6A, 6B... Semiconductor region, 7... Dicing area, 8.11.13... Insulating film, 9.9A,
14... Connection hole, 10, IOA... Conductive layer, LOP
・Probe testing pad, 12.21.25...open 0.15.15A, ISB, 15C, 15D...bonding pad, 16...printed circuit board, 17...
Finger, 18... Electrode of printed circuit board, 19 thread tape, 20... Surface material, 22.23.24... Resist mask.

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized in that a measurement electrode and an external electrode made of a conductive material different from the measurement electrode are provided on a semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the measurement electrode is a probe test pad for testing dynamic and static characteristics of a semiconductor element, and the external electrode is a bonding pad. 3. The semiconductor device according to claim 1, wherein the external electrode is comprised of a conductive layer above the measurement electrode. 4. The measurement electrode is made of an aluminum layer, and the external electrode is made of at least a three-layer film in which a copper layer or a palladium layer is provided on a titanium layer, and a solder layer is provided on the copper layer or palladium layer. Claim 1 characterized in that
The semiconductor device described. 5. The external electrode is formed by sequentially laminating a titanium layer, a copper layer or palladium layer, and a solder layer, and further providing a second titanium layer on the copper layer or palladium layer so as to surround the solder layer. Claim 1 or 4 characterized in
1. Semiconductor device described in Section 1. 6. The number of external electrodes is smaller than the number of measurement electrodes,
5. The semiconductor device according to claim 1, wherein the plurality of external electrodes are connected to some measurement electrodes selected from among the plurality of measurement electrodes. 7. The measurement electrode is provided on the top of a field insulating film around the chip, and the external electrode is provided on the top of a semiconductor element such as a MISFET. 4. The semiconductor device according to item 4. 8. The semiconductor device according to claim 1 or 4, wherein the measurement electrode is removed after probe testing.