JPH0760874B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0760874B2 JPH0760874B2 JP9927890A JP9927890A JPH0760874B2 JP H0760874 B2 JPH0760874 B2 JP H0760874B2 JP 9927890 A JP9927890 A JP 9927890A JP 9927890 A JP9927890 A JP 9927890A JP H0760874 B2 JPH0760874 B2 JP H0760874B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- insulating layer
- resin
- thermal expansion
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関する。The present invention relates to a semiconductor device.
〔従来の技術〕 シリコンチップは熱膨張率が３〜４×10-6/℃と小さ
い。そこで、従来の半導体装置では、シリコンチップは
熱膨張率の小さいセラミックス配線板に搭載されてい
た。しかし、セラミックス配線板では、金や銀の厚膜に
よりセラミックス基板上に回路形成を行うため200μｍ
以下の微細回路の形成が難しいこと、大きな基板を製造
することが困難なこと、製造した配線板が割れやすいこ
となどの問題点があった。[Prior Art] Silicon chips have a small coefficient of thermal expansion of 3 to 4 × 10 -6 / ° C. Therefore, in the conventional semiconductor device, the silicon chip is mounted on the ceramic wiring board having a small coefficient of thermal expansion. However, in the case of a ceramic wiring board, the circuit is formed on the ceramic substrate with a thick film of gold or silver, and the thickness is 200 μm.
There are problems that it is difficult to form the following fine circuits, it is difficult to manufacture a large substrate, and the manufactured wiring board is easily broken.
また、温度が比較的一定の室内で使われる用途の半導体
装置では、シリコンチップは樹脂配線板に搭載されるこ
ともある。しかし、樹脂配線板の場合、樹脂とシリコン
チップとの熱膨張差が大きいため半導体装置の信頼性が
低下するという問題があった。特にフリップチップのよ
うに微細なはんだで接続するCCB（Controlled Collapse
Bonding）には樹脂配線板の適用は困難であった。Further, in a semiconductor device for use in a room where the temperature is relatively constant, the silicon chip may be mounted on a resin wiring board. However, in the case of the resin wiring board, there is a problem that the reliability of the semiconductor device is lowered due to a large difference in thermal expansion between the resin and the silicon chip. CCB (Controlled Collapse) that connects with fine solder like flip chip
It was difficult to apply resin wiring boards to Bonding).
また、最近では金属板に絶縁層を設け、絶縁層の表面に
回路を形成した金属ベース配線板へのシリコンチップの
搭載が検討されている。金属ベース配線板の場合、金属
板としてアルミニウム、銅、鉄、42合金等を用いること
ができるが、シリコンチップ（熱膨張率 ３〜４×10-6
/℃）に対して、熱膨張率が最も近い42合金（熱膨張率
４×10-6/℃）等の低熱膨張金属が半導体装置の接続
信頼性の点で最も優れている。そこで、42合金を用いた
金属ベース配線板も検討されている。しかし、金属板上
に設けられた絶縁層の樹脂と42合金等の金属板の低熱膨
張金属との熱膨張係数が異なるため熱サイクルにより絶
縁層に大きな熱応力が発生し、代表的な半導体装置の信
頼性試験の一つである熱サイクル試験（−50℃ 30分、
室温５分、150℃ 30分のサイクル試験）によって、300
〜400サイクル程度から絶縁層に亀裂や亀裂を起点とし
た剥離が発生するという問題のあることがわかった。Further, recently, mounting of a silicon chip on a metal base wiring board in which an insulating layer is provided on a metal plate and a circuit is formed on the surface of the insulating layer has been studied. In the case of a metal base wiring board, aluminum, copper, iron, 42 alloy, etc. can be used as the metal plate, but silicon chips (coefficient of thermal expansion 3 to 4 × 10 −6
The low thermal expansion metal such as 42 alloy (coefficient of thermal expansion 4 × 10 −6 / ° C.) having the closest thermal expansion coefficient to (/ ° C.) is the best in terms of connection reliability of the semiconductor device. Therefore, metal-based wiring boards using 42 alloy are also under study. However, because the thermal expansion coefficient of the resin of the insulating layer provided on the metal plate is different from that of the low thermal expansion metal of the metal plate such as 42 alloy, a large thermal stress is generated in the insulating layer due to the thermal cycle, and a typical semiconductor device Thermal cycle test (-50 ° C 30 minutes,
Cycle test at room temperature 5 minutes, 150 ℃ 30 minutes)
It was found that there was a problem that cracks and peeling starting from the cracks occurred in the insulating layer from about 400 cycles.
本発明は、熱サイクル試験（−50℃ 30分、室温５分、
150℃ 30分のサイクル試験）で1000サイクル以上にお
いても絶縁層に亀裂や剥離が発生することがなく、配線
板と搭載したシリコンチップとの熱膨張の整合性にも優
れているため、高い接続信頼性が保たれる半導体装置を
提供しようとするものである。The present invention is a thermal cycle test (-50 ° C 30 minutes, room temperature 5 minutes,
No cracking or peeling of the insulating layer occurs even after 1000 cycles at 150 ° C for 30 minutes (cycle test), and the thermal expansion matching between the wiring board and the mounted silicon chip is excellent, resulting in high connection. An object of the present invention is to provide a semiconductor device that maintains reliability.
本発明者らは前記課題を解決するために鋭意研究を重ね
た結果、特定の熱膨張率を有する金属板上に特定の２層
の絶縁層を設けた半導体装置により、その目的が達成さ
れることを見出し、この知見に基づいて本発明を完成す
るに至った。The inventors of the present invention have conducted extensive studies to solve the above problems, and as a result, a semiconductor device in which two specific insulating layers are provided on a metal plate having a specific coefficient of thermal expansion can achieve the object. Based on this finding, the present invention has been completed.
すなわち本発明は、熱膨張率が７×10-6/℃以下の低熱
膨張金属からなる金属板、該金属板上に設けられた有機
樹脂又は有機樹脂と無機物の複合材料からなる第１の絶
縁層、第１の絶縁層上に設けられたセラミックスの溶射
層からなる第２の絶縁層、第２の絶縁層上に設けられた
金属導体からなる配線層及び配線層と接続されたシリコ
ンチップからなり、第２の絶縁層の厚さが20μｍ以上15
0μｍ以下であることを特徴とする半導体装置を提供す
るものである。That is, the present invention provides a metal plate made of a low thermal expansion metal having a coefficient of thermal expansion of 7 × 10 −6 / ° C. or less, an organic resin provided on the metal plate, or a first insulation made of a composite material of an organic resin and an inorganic material. Layer, a second insulating layer made of a ceramic sprayed layer provided on the first insulating layer, a wiring layer made of a metal conductor provided on the second insulating layer, and a silicon chip connected to the wiring layer And the thickness of the second insulating layer is 20 μm or more 15
The present invention provides a semiconductor device having a thickness of 0 μm or less.
以下、本発明を図に基づいて詳細を説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図に本発明の一例を示す半導体装置の部分断面を表
す斜視図を示す。FIG. 1 is a perspective view showing a partial cross section of a semiconductor device showing an example of the present invention.
本発明の半導体装置は金属板１、第１の絶縁層21、第２
の絶縁層22及び配線層３からなる配線板と、配線板に搭
載されたシリコンチップ４からなる。第１の絶縁層21は
金属板１上に設けられており、その上に更に第２の絶縁
層22が設けられている。そして、第２の絶縁層22上に配
線層３が設けられており、シリコンチップ４は配線層３
に接続されている。The semiconductor device of the present invention includes a metal plate 1, a first insulating layer 21, and a second insulating layer 21.
A wiring board composed of the insulating layer 22 and the wiring layer 3 and a silicon chip 4 mounted on the wiring board. The first insulating layer 21 is provided on the metal plate 1, and the second insulating layer 22 is further provided thereon. The wiring layer 3 is provided on the second insulating layer 22, and the silicon chip 4 is
It is connected to the.
金属板１としては、シリコンチップと配線板との接続信
頼性の点から、第２の絶縁層として好適なアルミナセラ
ミックスの熱膨張率（７×10-6/℃）と同等かそれ以下
の熱膨張率を有する低熱膨張金属を用いる。すなわち、
熱膨張率が７×10-6/℃以下の低熱膨張金属を用いる。
熱膨張率が７×10-6/℃を超えると、熱サイクルにより
はんだ接続部に過大な熱応力が加わってはんだの亀裂や
剥離を起こし、シリコンチップと配線板との接続信頼性
が低下する。具体的な金属の選定は、要求される半導体
装置の信頼性の程度により決まる。このような低熱膨張
金属としては、例えば、42合金、インバーのようなニッ
ケル合金、銅／インバー／銅のような複層金属等が挙げ
られる。The metal plate 1 has a thermal expansion coefficient (7 × 10 −6 / ° C.) equal to or lower than that of alumina ceramics suitable for the second insulating layer in terms of connection reliability between the silicon chip and the wiring board. A low thermal expansion metal having an expansion coefficient is used. That is,
A low thermal expansion metal having a thermal expansion coefficient of 7 × 10 −6 / ° C. or less is used.
If the coefficient of thermal expansion exceeds 7 × 10 -6 / ° C, excessive thermal stress will be applied to the solder joints due to thermal cycles, causing solder cracks and peeling, and the connection reliability between the silicon chip and the wiring board will decrease. . The specific metal selection depends on the required degree of reliability of the semiconductor device. Examples of such a low thermal expansion metal include 42 alloy, nickel alloy such as Invar, and multi-layer metal such as copper / Invar / copper.
第１の絶縁層21は、有機樹脂又は有機樹脂と無機物の複
合材料からなる。有機樹脂としては、耐熱性の点から、
ガラス転移点が70℃以上、より好ましくは100℃以上の
ものが好適に用いられる。ガラス転移点が70℃未満であ
ると耐熱性が不充分で、はんだ耐熱試験等により金属板
１と第１の絶縁層21が剥離しやすくなる。ガラス転移点
が70℃以上の有機樹脂としては、例えば、電気特性に優
れるエポキシ樹脂、ボリイミド樹脂及びポリアミド樹脂
から選択された樹脂が好適に使用される。第１の絶縁層
21は、熱膨張を低減させるために、アルミナやシリカ等
の無機物が充填されている有機樹脂と無機物の複合材料
であることが望ましい。The first insulating layer 21 is made of an organic resin or a composite material of an organic resin and an inorganic material. As an organic resin, from the viewpoint of heat resistance,
A glass transition point of 70 ° C. or higher, more preferably 100 ° C. or higher is preferably used. If the glass transition point is lower than 70 ° C., the heat resistance is insufficient, and the metal plate 1 and the first insulating layer 21 are easily peeled off by a solder heat resistance test or the like. As the organic resin having a glass transition point of 70 ° C. or higher, for example, a resin selected from an epoxy resin, a polyimide resin, and a polyamide resin, which have excellent electric characteristics, is preferably used. First insulating layer
21 is preferably a composite material of an organic resin and an inorganic material filled with an inorganic material such as alumina or silica in order to reduce thermal expansion.
第２の絶縁層22は、セラミックスの溶射層からなる。セ
ラミックスの材料としては、熱膨張率、電気特性の点か
ら、アルミナ、ムライト等の溶射層が好適である。溶射
層の厚さは、20μｍ以上150μｍ以下とする。20μｍ未
満では連続的セラミックス層を得ることが困難であり、
150μｍを超えると生産性が悪くなる。セラミックスを
溶射することにより、容易に前記したような薄いセラミ
ックス層を得ることができる。The second insulating layer 22 is a ceramic sprayed layer. As a material for the ceramics, a thermal sprayed layer of alumina, mullite, or the like is suitable from the viewpoint of the coefficient of thermal expansion and electric characteristics. The thickness of the sprayed layer is 20 μm or more and 150 μm or less. If it is less than 20 μm, it is difficult to obtain a continuous ceramic layer,
If it exceeds 150 μm, the productivity will deteriorate. By spraying the ceramics, the thin ceramic layer as described above can be easily obtained.
本発明の半導体装置では絶縁層が有機樹脂又は有機樹脂
と無機物の複合材料からなる第１の絶縁層21とセラミッ
クスの溶射層からなる第２の絶縁層の２層構造となって
いるため、第１の絶縁層21が緩衝的作用をもち、セラミ
ックスを用いながらプレス切断等の加工が可能である。
このため、異形加工も容易にでき、半導体装置を安価に
製造することができる。In the semiconductor device of the present invention, the insulating layer has a two-layer structure of the first insulating layer 21 made of the organic resin or the composite material of the organic resin and the inorganic material and the second insulating layer made of the ceramic sprayed layer. The first insulating layer 21 has a buffer function, and can be processed by press cutting while using ceramics.
Therefore, it is possible to easily carry out the deformation processing, and the semiconductor device can be manufactured at low cost.
金属導体からなる配線層３としては、一般の配線板と同
様に銅からなるものが適している。本発明では銅箔から
なる配線層を用いることもでき、銅箔をエッチングして
回路形成することにより精度の高い回路を得ることがで
きる。必要に応じ銅箔表面にニッケル、金、銀若しくは
アルミニウムのめっきを施しためっき物又は銅とニッケ
ル、金、銀若しくはアルミニウムをクラッドした複合箔
からなる配線層を用いることもできる。配線層はエッチ
ング法等により、所定の回路に形成されていることが好
ましい。As the wiring layer 3 made of a metal conductor, one made of copper is suitable as in a general wiring board. In the present invention, a wiring layer made of a copper foil can be used, and a circuit with high accuracy can be obtained by etching the copper foil to form a circuit. If necessary, a wiring layer made of a plated product obtained by plating the surface of a copper foil with nickel, gold, silver or aluminum or a composite foil clad with copper and nickel, gold, silver or aluminum can be used. The wiring layer is preferably formed in a predetermined circuit by an etching method or the like.
シリコンチップ４としては、任意のものを用いることが
できる。シリコンチップ４と配線層３との接続法として
は、微細はんだによる接続（CCB）やワイアボンディン
グ接続等が挙げられる。第１図はCCBによる接続の一例
を示している。CCB接続など微細なはんだ接続を伴う接
続法は、従来、微細なはんだ接続部がシリコンチップと
配線板の熱膨張差による応力を受けやすく適用が困難で
あった。しかし、本発明の半導体装置ではシリコンチッ
プと配線板との熱膨張差が小さいので、微細なはんだ接
続を伴うCCB接続等も好適に使用することができる。し
たがって、本発明はシリコンチップ４として第１図に示
したようなCCB接続を行うフリップチップを使用する半
導体装置で特に有効である。Any silicon chip 4 can be used. Examples of the method for connecting the silicon chip 4 and the wiring layer 3 include fine solder connection (CCB) and wire bonding connection. FIG. 1 shows an example of connection by CCB. Conventionally, the connection method involving fine solder connection such as CCB connection is difficult to apply because the fine solder connection is susceptible to stress due to the difference in thermal expansion between the silicon chip and the wiring board. However, in the semiconductor device of the present invention, since the difference in thermal expansion between the silicon chip and the wiring board is small, CCB connection or the like involving fine solder connection can also be suitably used. Therefore, the present invention is particularly effective in a semiconductor device using a flip chip for CCB connection as shown in FIG. 1 as the silicon chip 4.
シリコンチップ４は保護のためゲル、ゴム又は樹脂等に
より封止されていることが好ましい。封止はシリコンチ
ップ４だけでなく、半導体装置全体になされていてもよ
く、少なくともシリコンチップ４が封止されていること
が好ましい。The silicon chip 4 is preferably sealed with gel, rubber, resin or the like for protection. The sealing may be performed not only on the silicon chip 4 but also on the entire semiconductor device, and at least the silicon chip 4 is preferably sealed.
以上、第１図に基づいて１個のシリコンチップが搭載さ
れている半導体装置について説明したが、本発明の半導
体装置には複数のシリコンチップや他の素子等が搭載さ
れていてもよい。Although the semiconductor device in which one silicon chip is mounted has been described above with reference to FIG. 1, a plurality of silicon chips or other elements may be mounted in the semiconductor device of the present invention.
本発明の半導体装置では、配線板の金属板として熱膨張
がシリコンチップと近い低熱膨張金属を用いることによ
り、配線板と搭載したシリコンチップとの熱膨張差によ
る応力が抑制され、シリコンチップの接続信頼性の高い
半導体装置となっている。また、絶縁層の一部として設
けられたセラミックスの溶射層からなる第２の絶縁層の
熱膨張率は有機材料に比べて小さく金属板の熱膨張率に
近い。また、セラミックの溶射層であるため、破断強度
も大きい。これらのことから、熱サイクル試験時におい
て絶縁層に亀裂や亀裂を起点とする剥離が極めて起こり
にくい半導体装置となっている。In the semiconductor device of the present invention, by using a low thermal expansion metal whose thermal expansion is close to that of the silicon chip as the metal plate of the wiring board, the stress due to the thermal expansion difference between the wiring board and the mounted silicon chip is suppressed, and the silicon chip is connected. It is a highly reliable semiconductor device. Further, the thermal expansion coefficient of the second insulating layer formed of a ceramic sprayed layer provided as a part of the insulating layer is smaller than that of the organic material and is close to the thermal expansion coefficient of the metal plate. Further, since it is a ceramic sprayed layer, it has a high breaking strength. From these facts, the semiconductor device is a semiconductor device in which cracks or peeling originating from the cracks are extremely unlikely to occur in the heat cycle test.
以下、本発明を実施例に基づいて詳細に説明するが、本
発明はこれに限定されるものではない。Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.
実施例１ 銅箔の片面にアルミナを50μｍの厚さで溶射により付着
させた。次いで、このもののアルミナ面に、アルミナフ
ィラーを50体積％充填したガラス転移温度が140℃のエ
ポキシ樹脂のワニスを塗布し、乾燥させた。その後、こ
のものと表面を研磨後シランカップリング剤処理した42
合金板（縦200mm、横200mm、厚み1mm）とをエポキシ樹
脂層と42合金板とが接するように積層し、加圧加熱して
基板を作製した。Example 1 Alumina was applied by thermal spraying to a thickness of 50 μm on one surface of a copper foil. Next, an epoxy resin varnish having a glass transition temperature of 140 ° C., which was filled with 50% by volume of an alumina filler, was applied to the alumina surface of this product and dried. Then, this and the surface were polished and treated with a silane coupling agent.
An alloy plate (length 200 mm, width 200 mm, thickness 1 mm) was laminated so that the epoxy resin layer and the 42 alloy plate were in contact with each other and heated under pressure to produce a substrate.
次いで、銅箔のエッチングにより回路形成及びソルダー
レジスト（永久マスク）形成を行って配線板を作製し
た。配線板の大きさが50mm角になるように切断後、この
配線板に5mm角のフリップチップを搭載し回路と接続し
て半導体装置を作製した。Next, a circuit board and a solder resist (permanent mask) were formed by etching the copper foil to produce a wiring board. After cutting the wiring board into 50 mm square, a 5 mm square flip chip was mounted on the wiring board and connected to a circuit to manufacture a semiconductor device.
得られた半導体装置について熱サイクル試験を行ったと
ころ、−50℃ 30分、室温５分、150℃ 30分の条件
で、1500サイクル後も電気的接続が保たれており、絶縁
層部分にも何ら異常は認められなかった。第２図に熱サ
イクル1500サイクル後の配線板表面の顕微鏡写真を示
す。ここで、５は銅配線、６は絶縁層表面、７はソルダ
ーレジストを表す。A thermal cycle test was conducted on the obtained semiconductor device. It was found that the electrical connection was maintained after 1500 cycles under the conditions of -50 ° C for 30 minutes, room temperature for 5 minutes, and 150 ° C for 30 minutes. No abnormality was found. Figure 2 shows a photomicrograph of the surface of the wiring board after 1500 thermal cycles. Here, 5 is a copper wiring, 6 is an insulating layer surface, and 7 is a solder resist.
比較例１ ガラス転移温度が140℃のエポキシ樹脂ワニスを塗布し
た銅箔と表面を研磨後シランカップリング剤処理した42
合金板とを実施例１と同様に積層し、加圧加熱して基板
を作製した。次いで回路形成して配線板を得た。更に、
この配線板にフリップチップを搭載、接続し、半導体装
置を作製した。Comparative Example 1 A copper foil coated with an epoxy resin varnish having a glass transition temperature of 140 ° C. and the surface thereof were polished and then treated with a silane coupling agent 42
An alloy plate was laminated in the same manner as in Example 1 and heated under pressure to produce a substrate. Next, a circuit was formed to obtain a wiring board. Furthermore,
A flip chip was mounted on this wiring board and connected to manufacture a semiconductor device.
得られた半導体装置について実施例１と同様に熱サイク
ル試験を行ったところ、約300〜400サイクルで絶縁層表
面に亀裂や部分的な剥離が発生した。第３図に熱サイク
ル500サイクル後の配線板表面の顕微鏡写真を示す。A thermal cycle test was performed on the obtained semiconductor device in the same manner as in Example 1. As a result, cracks or partial peeling occurred on the surface of the insulating layer in about 300 to 400 cycles. Figure 3 shows a photomicrograph of the surface of the wiring board after 500 thermal cycles.
比較例２ エポキシ樹脂ワニスの代わりに比較例１と同じ組成のエ
ポキシ樹脂ワニスにアルミナフィラーを約50体積％添加
したものを用いて比較例１と同様の半導体装置を作製し
た。Comparative Example 2 A semiconductor device similar to that of Comparative Example 1 was manufactured by using, instead of the epoxy resin varnish, an epoxy resin varnish having the same composition as that of Comparative Example 1 to which about 50% by volume of an alumina filler was added.
得られた半導体装置について実施例１と同様に熱サイク
ル試験を行ったところ、約500サイクルで絶縁層表面に
亀裂や部分的な剥離が発生した。第４図に熱サイクル50
0サイクル後の配線板表面の顕微鏡写真を示す。A thermal cycle test was conducted on the obtained semiconductor device in the same manner as in Example 1. As a result, cracks and partial peeling occurred on the surface of the insulating layer in about 500 cycles. Fig. 4 shows the thermal cycle 50
The micrograph of the wiring board surface after 0 cycle is shown.
比較例３ 比較例１と同様のエポキシ樹脂ワニスを含浸後乾燥させ
たガラス布を用いてその片面に銅箔を接着し、他面に研
磨後シランカップリング剤処理した42合金板を接着し、
比較例１と同様の半導体装置を作製した。Comparative Example 3 Using a glass cloth which was impregnated with the same epoxy resin varnish as in Comparative Example 1 and dried, a copper foil was adhered to one surface thereof, and a 42 alloy plate treated with a silane coupling agent after polishing was adhered to the other surface thereof.
A semiconductor device similar to that of Comparative Example 1 was manufactured.
得られた半導体装置について実施例１と同様にサイクル
試験を行ったところ、約500サイクルで絶縁層にマイク
ロクラックが入り、約800サイクルで絶縁層の端部から
剥離が発生した。約1500サイクルでは、端部より３〜10
mm幅にわたって絶縁層が剥離してしまった。第５図に熱
サイクル1000サイクル後の配線板表面の顕微鏡写真を示
す。A cycle test was performed on the obtained semiconductor device in the same manner as in Example 1. As a result, microcracks were formed in the insulating layer at about 500 cycles, and peeling occurred from the end portion of the insulating layer at about 800 cycles. In about 1500 cycles, 3-10 from the end
The insulating layer was peeled off over the mm width. Fig. 5 shows a photomicrograph of the surface of the wiring board after 1000 thermal cycles.
比較例４ 非晶質シリカを約50％添加したエポキシ樹脂ワニスを用
いて比較例１と同様の半導体装置を作製した。Comparative Example 4 A semiconductor device similar to Comparative Example 1 was manufactured using an epoxy resin varnish containing about 50% of amorphous silica.
得られた半導体装置について実施例１と同様に熱サイク
ル試験を行ったところ、約500サイクルで絶縁層表面に
亀裂や部分的な剥離が発生した。第６図に熱サイクル50
0サイクル後の配線板表面の顕微鏡写真を示す。A thermal cycle test was conducted on the obtained semiconductor device in the same manner as in Example 1. As a result, cracks and partial peeling occurred on the surface of the insulating layer in about 500 cycles. Fig. 6 shows the thermal cycle 50
The micrograph of the wiring board surface after 0 cycle is shown.
本発明によると、熱サイクルにより絶縁層に亀裂や剥離
が発生せず、配線板と搭載したシリコンチップとの熱膨
張の整合性に優れているため、高い接続信頼性が保たれ
る半導体装置を提供することができる。According to the present invention, a crack or peeling does not occur in the insulating layer due to the thermal cycle, and since the matching of the thermal expansion between the wiring board and the mounted silicon chip is excellent, a semiconductor device with high connection reliability is provided. Can be provided.
第１図は本発明の一実施例を示す半導体装置の部分断面
を表す斜視図である。 第２図は実施例１の熱サイクル試験後の配線板表面を示
す顕微鏡写真である。第３図〜第６図はそれぞれ比較例
１〜４までの熱サイクル試験後の配線板表面を示す顕微
鏡写真である。 符号の説明 １……金属板、21……第１の絶縁層 22……第２の絶縁層、３……配線層 ４……シリコンチップ、５……銅配線 ６……絶縁層表面、７……ソルダーレジストFIG. 1 is a perspective view showing a partial cross section of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a micrograph showing the surface of the wiring board after the heat cycle test of Example 1. 3 to 6 are photomicrographs showing the surface of the wiring board after the thermal cycle test of Comparative Examples 1 to 4, respectively. DESCRIPTION OF SYMBOLS 1 ... Metal plate, 21 ... First insulating layer 22 ... Second insulating layer, 3 ... Wiring layer, 4 ... Silicon chip, 5 ... Copper wiring, 6 ... Insulating layer surface, 7 ...... Solder resist
Claims (6)
属からなる金属板、該金属板上に設けられた有機樹脂又
は有機樹脂と無機物の複合材料からなる第１の絶縁層、
第１の絶縁層上に設けられたセラミックスの溶射層から
なる第２の絶縁層、第２の絶縁層上に設けられた金属導
体からなる配線層及び配線層と接続されたシリコンチッ
プからなり、第２の絶縁層の厚さが20μｍ以上150μｍ
以下であることを特徴とする半導体装置。1. A metal plate made of a low thermal expansion metal having a coefficient of thermal expansion of 7 × 10 −6 / ° C. or less, and a first insulation made of an organic resin or a composite material of an organic resin and an inorganic material provided on the metal plate. layer,
A second insulating layer made of a ceramic sprayed layer provided on the first insulating layer, a wiring layer made of a metal conductor provided on the second insulating layer, and a silicon chip connected to the wiring layer, The thickness of the second insulating layer is 20 μm or more and 150 μm
A semiconductor device characterized by the following.
が70℃以上の有機樹脂である請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the organic resin of the first insulating layer is an organic resin having a glass transition point of 70 ° C. or higher.
ある有機樹脂が、エポキシ樹脂、ポリイミド樹脂及びポ
リアミド樹脂から選択された樹脂である請求項２記載の
半導体装置。3. The semiconductor device according to claim 2, wherein the organic resin having a glass transition point of 70 ° C. or higher in the first insulating layer is a resin selected from epoxy resin, polyimide resin and polyamide resin.
面にニッケル、金、銀若しくはアルミニウムのめっきを
施しためっき物又は銅とニッケル、金、銀若しくはアル
ミニウムをクラッドした複合箔からなる請求項１〜３い
ずれか記載の半導体装置。4. A wiring layer made of a metal conductor is a copper foil, a plated product obtained by plating the surface of a copper foil with nickel, gold, silver or aluminum, or a composite foil in which copper and nickel, gold, silver or aluminum are clad. The semiconductor device according to any one of claims 1 to 3.
求項１〜４いずれか記載の半導体装置。5. The semiconductor device according to claim 1, wherein the silicon chip is a flip chip.
は樹脂により封止されている請求項１〜５いずれか記載
の半導体装置。6. The semiconductor device according to claim 1, wherein at least the silicon chip is sealed with gel, rubber or resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9927890A JPH0760874B2 (en) | 1990-04-17 | 1990-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9927890A JPH0760874B2 (en) | 1990-04-17 | 1990-04-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03297159A JPH03297159A (en) | 1991-12-27 |
| JPH0760874B2 true JPH0760874B2 (en) | 1995-06-28 |
Family
ID=14243200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9927890A Expired - Lifetime JPH0760874B2 (en) | 1990-04-17 | 1990-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760874B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009092851A1 (en) * | 2008-01-22 | 2009-07-30 | Valtion Teknillinen Tutkimuskeskus | Method for arranging cooling for a component and a cooling element |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0592165A (en) * | 1991-05-16 | 1993-04-16 | Sansha Electric Mfg Co Ltd | Method for applying metal to ceramics substrate by plasma spray |
-
1990
- 1990-04-17 JP JP9927890A patent/JPH0760874B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009092851A1 (en) * | 2008-01-22 | 2009-07-30 | Valtion Teknillinen Tutkimuskeskus | Method for arranging cooling for a component and a cooling element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03297159A (en) | 1991-12-27 |
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