JPH03297159A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve reliability for thermal expansion by providing an organic resin insulating layer and an insulating layer made of a ceramic flame sprayed layer having a specific thickness on a metal plate having specific thermal expansion coefficient, and forming a metal wiring layer and a silicon chip thereon. CONSTITUTION:A first insulating layer 21 made of organic resin and a second insulating layer 22 made of a ceramic flame sprayed layer and having 20 to 250mum of thickness are formed on a low thermal expansion metal plate 1 having 7X10<-6>/ deg.C or less of thermal expansion coefficient. Then, the layer 22 is formed with a wiring layer 3 formed with a circuit by etching a copper foil and a silicon chip 4 connected thereto. Thus, low thermal expansion coefficient metal having near thermal expansion to that of the chip 4 is employed as the metal plate of the circuit board to suppress a stress due to a thermal expansion coefficient and to improve connecting reliability of the chip 4. Neither crack nor peeling occur in the insulting layers due to a heat cycle to obtain a semiconductor device having high reliability.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.

[Conventional technology]

Silicon chips have a small thermal expansion coefficient of 3 to 4×10 −6 /°C. Therefore, in conventional semiconductor devices, silicon chips are mounted on ceramic wiring boards with a small coefficient of thermal expansion. However, in ceramic wiring boards, the circuit is formed on the ceramic substrate using a thick film of gold or silver, so the thickness of 200μ
There were problems such as difficulty in forming microcircuits with a size of less than m, difficulty in manufacturing large substrates, and the tendency for manufactured wiring boards to break.

Furthermore, in semiconductor devices used indoors where the temperature is relatively constant, silicon chips are sometimes mounted on resin wiring boards. However, in the case of a resin wiring board, there is a problem in that the reliability of the semiconductor device decreases due to a large difference in thermal expansion between the resin and the silicon chip. In particular, CCB (Control
It was difficult to apply resin wiring boards to 1ed Collapse Bonding.

Furthermore, recently, consideration has been given to mounting a silicon chip on a metal base wiring board in which an insulating layer is provided on a metal plate and a circuit is formed on the surface of the insulating layer. In the case of a metal base wiring board, aluminum, copper, iron, 42 alloy, etc. can be used as the metal plate, but silicon chips (thermal expansion coefficient of 3 to 4
10-6/”C), the thermal expansion coefficient is closest to 42
Low thermal expansion metals such as alloys (coefficient of thermal expansion: 4 x 10-6/°C) are the most excellent in terms of connector stability for semiconductor devices. Therefore, metal-based wiring boards using 42 alloy are also being considered. However, the resin of the insulating layer provided on the metal plate and the
Since the coefficient of thermal expansion of metal plates such as two alloys is different from that of low thermal expansion metals, large thermal stress is generated in the insulating layer due to thermal cycling. A cycle test of 30 minutes at 50°C, 5 minutes at room temperature, and 30 minutes at 150°C revealed that there was a problem in which cracks or peeling starting from the cracks occurred in the insulating layer after about 300 to 400 cycles.

[Problem to be solved by the invention]

The present invention shows that the insulating layer does not crack or peel even after 1000 cycles or more in a thermal cycle test (-50°C 30 minutes, room temperature 5 minutes, 150°C 30 minutes), and the insulation layer can be easily bonded to the wiring board. The present invention aims to provide a semiconductor device that maintains high connection property because of its excellent thermal expansion matching with the silicon chip.

[Means to solve the problem]

The inventors of the present invention have conducted intensive research to solve the above problem, and as a result, the object has been achieved by a semiconductor device in which two specific insulating layers are provided on a metal plate having a specific coefficient of thermal expansion. Based on this finding, we have completed the present invention.

That is, the present invention has a thermal expansion coefficient of 7 x 10-b/'C
A metal plate made of the following low thermal expansion metal, a first insulating layer made of an organic resin or a composite material of an organic resin and an inorganic substance provided on the metal plate, and a sprayed ceramic layer provided on the first insulating layer. a second insulating layer consisting of a wiring layer made of a metal conductor provided on the second insulating layer, and a silicon chip connected to the wiring layer, the thickness of the second insulating layer is 2.
The present invention provides a semiconductor device characterized in that the thickness is 0 μm or more and 150 μm or less.

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 shows a perspective view showing a partial cross section of a semiconductor device showing an example of the present invention.

The semiconductor device of the present invention includes a wiring board including a metal plate 1, a first insulating layer 21, a second insulating layer 22, and a wiring layer 3, and a silicon chip 4 mounted on the wiring board. The first insulating layer 21 is provided on the metal plate 1, and the second insulating layer 21 is further provided on the metal plate 1.
An insulating layer 22 is provided. A wiring layer 3 is provided on the second insulating layer 22, and a silicon chip 4
is connected to the wiring layer 3.

The metal plate 1 has a thermal expansion coefficient equal to or lower than that of alumina ceramics (7X10/°C), which is suitable for the second insulating layer, from the viewpoint of the connection body φ■ between the silicon chip and the wiring board. A metal with low thermal expansion is used. That is, a low thermal expansion metal with a coefficient of thermal expansion of 7 x 10-b/"C or less is used. If the coefficient of thermal expansion exceeds 7 x 10-b/", excessive thermal stress will be applied to the solder joint due to thermal cycling. This also causes cracks and peeling of the solder, which reduces the connection reliability between the silicon chip and the wiring board. The specific selection of metal is determined by the required degree of reliability of the semiconductor device.

Examples of such low thermal expansion metals include 42 alloy,
Examples include nickel alloys such as Invar, multilayer metals such as copper/Invar/copper, and the like.

The first insulating layer 21 is made of an organic resin or a composite material of an organic resin and an inorganic material. From the viewpoint of heat resistance, the organic resin has a glass transition point of 70°C or higher, preferably 100°C.
Those mentioned above are preferably used. Glass transition point is 70℃
If it is less than that, the heat resistance will be insufficient, and the metal plate 1 and the first insulating layer 21 will easily peel off during a soldering heat resistance test or the like. Examples of organic resins having a glass transition point of 70°C or higher include:
Resins selected from epoxy resins, polyimide resins, and polyamide resins that have excellent electrical properties are preferably used.

The first insulating layer 21 is preferably a composite material of an organic resin and an inorganic material filled with an inorganic material such as alumina or silica in order to reduce thermal expansion.

The second insulation N22 is made of a sprayed ceramic layer.

As the ceramic material, thermally sprayed layers of alumina, mullite, etc. are suitable from the viewpoint of thermal expansion coefficient and electrical properties. The thickness of the sprayed layer is 20 μm or more and 150 μm or less. 2
If it is less than 0 μm, it is difficult to obtain a continuous ceramic layer, and if it exceeds 150 μm, the productivity will be poor. By thermal spraying ceramics, the above-mentioned thin ceramic layer can be easily obtained.

In the semiconductor device of the present invention, the insulating layer has a 2N structure consisting of the first insulating layer 21 made of an organic resin or a composite material of an organic resin and an inorganic material, and the second insulating layer 21 made of a sprayed ceramic layer. The insulating layer 21 has a buffering effect, and processing such as press cutting is possible while using ceramics. Therefore, irregular shape processing can be easily performed, and semiconductor devices can be manufactured at low cost.

As the wiring layer 3 made of a metal conductor, one made of copper is suitable as in a general wiring board. In the present invention, a wiring layer made of copper foil can also be used, and a highly accurate circuit can be obtained by etching the copper foil to form the circuit. If necessary, a wiring layer consisting of a copper foil surface plated with nickel, gold, silver, or aluminum, or a composite foil of copper clad with nickel, gold, silver, or aluminum can also be used. Preferably, the wiring layer is formed into a predetermined circuit by an etching method or the like.

Any silicon chip 4 can be used. Examples of the connection method between the silicon chip 4 and the wiring layer 3 include fine solder connection (ccB) and wire bonding connection.

FIG. 1 shows an example of connection by CCB.

Conventionally, connection methods involving minute solder connections such as CCB connections have been difficult to apply because the minute solder connections are susceptible to stress due to the difference in thermal expansion between the silicon chip and the wiring board. However, in the semiconductor device of the present invention, the difference in thermal expansion between the silicon chip and the wiring board is small, so CC
B connections etc. can also be suitably used. therefore,
The present invention is particularly effective in a semiconductor device that uses a flip chip that performs CCB connection as shown in FIG. 1 as the silicon chip 4.

The silicon chip 4 is preferably sealed with gel, rubber, resin, or the like for protection. The sealing may be performed not only on the silicon chip 4 but also on the entire semiconductor device, and it is preferable that at least the silicon chip 4 is sealed.

Although the semiconductor device mounted with one silicon chip has been described above based on FIG. 1, the semiconductor device of the present invention may be mounted with a plurality of silicon chips or other elements.

[Effect]

In the semiconductor device of the present invention, by using a low thermal expansion metal whose thermal expansion is close to that of the silicon chip as the metal plate of the wiring board, stress due to the difference in thermal expansion between the wiring board and the mounted silicon chip is suppressed, and the connection of the silicon chip is suppressed. It is a semiconductor device with high reliability. Further, the coefficient of thermal expansion of the second insulating layer made of a sprayed ceramic layer provided as a part of the insulating layer is smaller than that of an organic material and is close to that of the metal plate. Also, since it is a ceramic sprayed layer, it has high breaking strength. For these reasons, the semiconductor device is extremely unlikely to cause cracks in the insulating layer or peeling starting from the cracks during a thermal cycle test.

[Examples] Hereinafter, the present invention will be described in detail based on Examples, but the present invention is not limited thereto.

Example 1 Alumina was deposited on one side of copper foil to a thickness of 50 μm by thermal spraying. Next, the alumina surface of this product was filled with 50% by volume of alumina filler, and the glass transition temperature was 140.
Apply epoxy resin varnish at °C and let dry. After that, this and the 42 alloy plate (length 200ff IITl, width 200 opacity,
The epoxy resin layer and the 42 alloy plate were laminated so that they were in contact with each other and heated under pressure to produce a substrate.

Next, a wiring board was produced by etching the copper foil to form a circuit and a solder resist (permanent mask). After cutting the wiring board to have a size of 50 an square, a 5 square square flip chip was mounted on the wiring board and connected to a circuit to fabricate a semiconductor device.

When the obtained semiconductor device was subjected to a thermal cycle test, electrical connection was maintained even after 1500 cycles under the conditions of -50°C for 30 minutes, room temperature for 5 minutes, and 150°C for 30 minutes. No abnormality was observed. FIG. 2 shows a microscopic photograph of the surface of the wiring board after 1500 thermal cycles.

Here, 5 represents copper wiring, 6 represents the surface of the insulating layer, and 7 represents the solder resist.

Comparative Example 1 A copper foil coated with an epoxy resin varnish having a glass transition temperature of 140°C and a 42 alloy plate whose surface was polished and treated with a silane coupling agent were laminated in the same manner as in Example 1, and heated under pressure to form a substrate. Created. Next, a circuit was formed to obtain a wiring board. Furthermore, a flip chip was mounted and connected to this wiring board to produce a semiconductor device.

When the obtained semiconductor device was subjected to a thermal cycle test in the same manner as in Example 1, cracks and partial peeling occurred on the surface of the insulating layer after about 300 to 400 cycles. FIG. 3 shows a microscopic photograph of the surface of the wiring board after 500 thermal cycles.

Comparative Example 2 A semiconductor device similar to Comparative Example 1 was manufactured using an epoxy resin varnish having the same composition as Comparative Example 1 to which about 50% by volume of alumina filler was added instead of the epoxy resin varnish.

When the obtained semiconductor device was subjected to a thermal cycle test in the same manner as in Example 1, cracks and partial peeling occurred on the surface of the insulating layer after about 500 cycles.

FIG. 4 shows a microscopic photograph of the surface of the wiring board after 500 thermal cycles.

Comparative Example 3 Using a glass cloth impregnated with the same epoxy resin varnish as in Comparative Example 1 and then dried, copper foil was adhered to one side of the cloth, and a 42 alloy plate treated with a silane coupling agent after polishing was adhered to the other side. A semiconductor device similar to Comparative Example 1 was manufactured.

When the obtained semiconductor device was subjected to a cycle test in the same manner as in Example 1, microcracks appeared in the insulating layer after about 500 cycles, and peeling occurred from the ends of the insulating layer after about 800 cycles. After approximately 1500 cycles, the insulating layer peeled off over a width of 3 to 10 widths from the edge.

FIG. 5 shows a microscopic photograph of the surface of the wiring board after 1000 cycles of the heating vehicle.

Comparative Example 4 A semiconductor device similar to Comparative Example 1 was fabricated using an epoxy resin varnish containing approximately 50% amorphous silica.

When the obtained semiconductor device was subjected to a thermal cycle test in the same manner as in Example 1, cracks and partial peeling occurred on the surface of the insulating layer after about 500 cycles.

FIG. 6 shows a microscopic photograph of the surface of the wiring board after 500 thermal cycles.

〔Effect of the invention〕

According to the present invention, the semiconductor device maintains high connection reliability because the insulating layer does not crack or peel due to thermal cycling and the thermal expansion matches well between the wiring board and the mounted silicon chip. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a partial cross section of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a micrograph showing the surface of the wiring board after the thermal cycle test of Example 1. FIGS. 3 to 6 are micrographs showing the surfaces of the wiring boards after the thermal cycle tests of Comparative Examples 1 to 4, respectively. Explanation of symbols 1 Metal plate 21 22 Second insulating layer 3 4 Silicon chip 5 6 Insulating layer surface 7 First insulating layer wiring layer copper wiring solder resist

Claims (1)

[Scope of Claims] 1. A metal plate made of a low thermal expansion metal with a coefficient of thermal expansion of 7×10^-^6/°C or less, an organic resin provided on the metal plate, or a composite material of an organic resin and an inorganic material. a first insulating layer,
A second insulating layer made of a sprayed ceramic layer provided on the first insulating layer, a wiring layer made of a metal conductor provided on the second insulating layer, and a silicon chip connected to the wiring layer, The thickness of the second insulating layer is 20 μm or more 150
A semiconductor device characterized by having a diameter of μm or less. 2. The organic resin of the first insulating layer has a glass transition point of 70°C.
2. The semiconductor device according to claim 1, which is an organic resin as described above. 3. The semiconductor device according to claim 2, wherein the organic resin of the first insulating layer having a glass transition point of 70° C. or higher is a resin selected from epoxy resin, polyimide resin, and polyamide resin. 4. A claim in which the wiring layer made of a metal conductor is made of copper foil, a plated product in which the surface of the copper foil is plated with nickel, gold, silver, or aluminum, or a composite foil in which copper is clad with nickel, gold, silver, or aluminum. 4. The semiconductor device according to any one of 1 to 3. 5. Claims 1 to 5, wherein the silicon chip is a flip chip.
4. The semiconductor device according to any one of 4. 6. The semiconductor device according to claim 1, wherein at least the silicon chip is sealed with gel, rubber, or resin.