JPS62114245A - Manufacture of substrate for hybrid integrated circuit - Google Patents
Manufacture of substrate for hybrid integrated circuitInfo
- Publication number
- JPS62114245A JPS62114245A JP25370385A JP25370385A JPS62114245A JP S62114245 A JPS62114245 A JP S62114245A JP 25370385 A JP25370385 A JP 25370385A JP 25370385 A JP25370385 A JP 25370385A JP S62114245 A JPS62114245 A JP S62114245A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- cfrp
- board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、集積回路（ＩＣ）チップ搭載用の配線基板の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a wiring board for mounting an integrated circuit (IC) chip.
（従来の技術）
パッケージレス化したチップを印刷配線基板に直接組み
込むようにすると、高密度な実装が可能になる。そのた
めに薄い銅箔を用いた印刷配線基板が開発されてきてい
る。(Prior Art) High-density packaging becomes possible by directly incorporating a package-less chip into a printed wiring board. For this purpose, printed wiring boards using thin copper foil have been developed.
従来、この種の混成集積回路用基板としては、例えば、
特開昭５８−１５２９０号公報に示されるものがあった
。Conventionally, as this type of hybrid integrated circuit board, for example,
There was one shown in Japanese Patent Application Laid-Open No. 15290/1983.
第２図は係る従来の混成集積回路用基板の断面図である
。FIG. 2 is a sectional view of such a conventional hybrid integrated circuit board.
この図に示されるように、アルミ、鉄、鉄−ニソケル合
金などの基材ｌヘシリカなどの放熱性の充填剤を混入し
たエポキシ、ポリイミドなどの樹脂を接着層２を介して
銅箔３と接着することにより、混成集積回路用基板とし
て構成されている。As shown in this figure, a resin such as epoxy or polyimide mixed with a heat dissipating filler such as silica is bonded to a copper foil 3 through an adhesive layer 2 to a base material such as aluminum, iron, or iron-Nisokel alloy. By doing so, it is constructed as a substrate for a hybrid integrated circuit.
このように、基材１を熱伝導性の良い金属とし、接着層
２に高熱伝導性の充填剤を入れているため、アルミナと
同等の熱伝導率を示し、アルミナ基板の代替材として使
用されている。In this way, since the base material 1 is made of a metal with good thermal conductivity and the adhesive layer 2 contains a highly thermally conductive filler, it exhibits the same thermal conductivity as alumina and can be used as a substitute for alumina substrates. ing.
（発明が解決しようとする問題点）
しかしながら、上記構成の基板では、基材に金属を使用
するため、ＩＣチップと線膨脹係数が合わず、外部環境
の変化などにより熱衝撃が加わると、線膨脹係数のミス
マツチから応力が生じて、ＩＣチップが破壊されるとい
った問題があった。(Problems to be Solved by the Invention) However, since the substrate with the above structure uses metal as the base material, the coefficient of linear expansion does not match that of the IC chip, and when thermal shock is applied due to changes in the external environment, the linear expansion There was a problem in that stress was generated due to mismatching of the expansion coefficients and the IC chip was destroyed.
本発明は、上記問題点を除去し、高熱伝導性を有し、し
かも、熱膨張係数がシリコンと同等な混成集積回路用基
板を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a substrate for a hybrid integrated circuit that has high thermal conductivity and has a coefficient of thermal expansion equivalent to that of silicon.
（問題点を解決するための手段）
本発明は、上記問題点を解決するために、下層にＣＦＲ
Ｐ Ｃ熱伝導率４３にｃａｌ／＋ｗ、ｈｒ、 ℃、線膨
脹係数０．７ Ｘｌ０−’／℃）を使用し、このＣＦＲ
Ｐの表面をサンドブラストで粗面とし、かつＡｈ（ｈ砂
をＣＦＲＰ上に突き刺してＣＦＲＰ基材を構成し、エポ
キシ接着剤（プリプレグ）で銅泊と前記ＣＦＲＰ基材を
加熱加圧することにより混成集積回路用基（反を得るよ
うにしたものである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides CFR in the lower layer.
Using cal/+w, hr, ℃, coefficient of linear expansion 0.7
The surface of P is roughened by sandblasting, and Ah (h sand is pierced onto the CFRP to form a CFRP base material, and the copper foil and the CFRP base material are heated and pressurized with epoxy adhesive (prepreg) to form a hybrid accumulation. A circuit board (made to obtain a reverse circuit board).
（作用）
本発明によれば、下層として熱伝導性が良く、かつ、線
膨脹係数の小さいＣＦＲＰ Ｃ熱伝導率４３Ｋｃａｌ／
ｍ、ｈｒ、 ℃、線膨脹係数 ０．７ ｘ １０−’／
’ｃ ）を使用し、これによる熱伝導を接着層でロス
するのを防ぐため、このＣＦＲＰの表面をサンドブラス
トで粗面とし、かつ＾１２０．砂をこのＣＦＲＰ上に突
き刺し、エポキシ接着剤（プリプレグ）で銅箔と前記Ｃ
ＦＲＰ基材を加熱加圧することにより、熱伝導性が良好
な、しかも、線膨脹係数がシリコンペレットに合つた混
成集積回路用基板を得ることができる。(Function) According to the present invention, the lower layer is made of CFRP C, which has good thermal conductivity and a small coefficient of linear expansion, and has a thermal conductivity of 43 Kcal/
m, hr, °C, linear expansion coefficient 0.7 x 10-'/
'c), and in order to prevent heat conduction from being lost in the adhesive layer, the surface of this CFRP is made rough by sandblasting, and ^120. Punch sand onto this CFRP and attach it to the copper foil with epoxy adhesive (prepreg).
By heating and pressing the FRP base material, it is possible to obtain a substrate for a hybrid integrated circuit that has good thermal conductivity and has a coefficient of linear expansion matching that of silicon pellets.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明に係る混成集積回路用基板の製造工程図
である。FIG. 1 is a manufacturing process diagram of a hybrid integrated circuit board according to the present invention.
まず、第１図（ａ）に示される様に、ＣＦＲＰ積層手反
１１ （例えば、パイロフィル ２１〇三菱レーヨン製
）を用意する。なお、このＣＦＲＰは熱伝導率４３Ｋｃ
ａｌ／ｍ、ｈｒ、 ’Ｃ１線膨脹係数０．７ ｘｌＯ−
’／’ｃのものである。First, as shown in FIG. 1(a), a CFRP laminated cloth 11 (for example, Pyrofil 210 manufactured by Mitsubishi Rayon) is prepared. Furthermore, this CFRP has a thermal conductivity of 43Kc.
al/m, hr, 'C1 linear expansion coefficient 0.7 xlO-
'/'c's.
次に、第１図（ｂ）に示されるように、このＣＦＲＰ積
層板１１にアルミナ砂（＃１２０〜３２０）を用いたサ
ンドブラスト処理を行い、このＣＦＲＰ積層板１１上を
粗面１２とする。Next, as shown in FIG. 1(b), this CFRP laminate 11 is subjected to sandblasting using alumina sand (#120 to 320) to form a rough surface 12 on the CFRP laminate 11.
次に、サンドブラスト処理と同時に第１図（ｃ）に示さ
れるように、アルミナ砂１５がＣＦ Ｒ，Ｐ積層板中に
入りこみ、ＣＦＲＰ１４と接続される。Next, at the same time as the sandblasting process, as shown in FIG. 1(c), alumina sand 15 penetrates into the CF R,P laminate and is connected to the CFRP 14.
このＣＦＲＰ積層板を下層１３として、厚さ０．０５龍
のエポキシプリプレグを接着剤１６として使用し、電解
銅泊１７ （１８μｍ又は３５μｍ）を表層として、加
熱加圧することにより、混成集積回路用基板を得ること
ができる。Using this CFRP laminate as the lower layer 13, using epoxy prepreg with a thickness of 0.05 mm as the adhesive 16, and using electrolytic copper foil 17 (18 μm or 35 μm) as the surface layer, by heating and pressurizing, a substrate for hybrid integrated circuits is formed. can be obtained.
なお、このように構成された混成集積回路用基板は熱伝
導性は従来のガラスエポキシ塞板に比較して２倍以上、
線膨脹係数は８〜４ ｘｔｏ−ｂ／”ｃである。Furthermore, the thermal conductivity of the hybrid integrated circuit board constructed in this way is more than twice that of the conventional glass epoxy sealing board.
The coefficient of linear expansion is 8 to 4 xto-b/''c.
このように、熱伝導性が良く線膨脹係数の小さいＣＦＲ
Ｐ積ｊｌｉ板を下層に用い、銅箔との密着性及び熱伝導
性を良くするためにアルミナ砂でＣＦＲＰ積層板表面な
粗面とし、かつ、アルミナ砂がＣＦＲＰ積層板上に残り
、更に、５０μｍ以下のエポキシプリプレグを使用した
ので、熱伝導が良好な線膨脹係数がシリコン（′！ｆＡ
膨張係数２．６ Ｘ １０−’／℃）と非常に近い混成
集積回路用基板が得られる。In this way, CFR has good thermal conductivity and a small coefficient of linear expansion.
A Plaminate board is used as the lower layer, and the surface of the CFRP laminate is made rough with alumina sand to improve adhesion with the copper foil and thermal conductivity, and the alumina sand remains on the CFRP laminate, and further, Since we used epoxy prepreg with a diameter of 50 μm or less, the coefficient of linear expansion with good thermal conductivity is silicon ('!fA).
A substrate for a hybrid integrated circuit having an expansion coefficient very close to that of 2.6 x 10-'/°C) can be obtained.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、熱伝導
性が良く、かつ線膨脹係数の小さいＣＦＲＰ積層板を用
い、該ＣＦＲＰ積層）反の表面をアルミナ砂を用いサン
ドブラスト処理を行い、かつ該アルミナ砂をＣＦＲＰ積
層板上に残存させ、該ＣＦＲＰ積Ｎ板上に接着剤を介し
て金属薄層を形成するようにしたので、熱伝導性が良好
であり、しかも線膨脹係数がシリコンに橿めて近い混成
集積回路用基板を得ることができる。(Effects of the Invention) As described above in detail, according to the present invention, a CFRP laminate having good thermal conductivity and a small coefficient of linear expansion is used, and the surface of the CFRP laminate is made of alumina sand. Sandblasting is performed, the alumina sand is left on the CFRP laminate, and a thin metal layer is formed on the CFRP laminate with an adhesive, so it has good thermal conductivity. It is possible to obtain a substrate for a hybrid integrated circuit whose coefficient of linear expansion is much closer to that of silicon.
特に、この混成集積回路用基板はＩＣチップとのなじみ
が良く、外部環境の変化に起因する熱衝撃などによって
もＩＣチップが損傷を受けることがなく、ＩＣ搭載基板
として好適であり、高密度実装を行うことができる。In particular, this hybrid integrated circuit board has good compatibility with IC chips, and the IC chips are not damaged even by thermal shock caused by changes in the external environment, making it suitable as an IC mounting board and suitable for high-density mounting. It can be performed.
第１図は本発明に係る混成集積回路用基板の製造工程図
、第２図は従来の混成集積回路用基板の断面図である。
１１・・・ＣＦＲＰ積層板、１２・・・粗面、１３・・
・下層、１４・・・ＣＦＲＰ、１５・・・アルミナ砂、
１６・・・接着剤（エポキシプリプレグ）、１７・・・
金１ｉＬｉ層（を解銅泊）。FIG. 1 is a manufacturing process diagram of a hybrid integrated circuit board according to the present invention, and FIG. 2 is a sectional view of a conventional hybrid integrated circuit board. 11...CFRP laminate, 12...Rough surface, 13...
・Lower layer, 14...CFRP, 15...Alumina sand,
16...Adhesive (epoxy prepreg), 17...
Gold 1iLi layer (copper-plated).
Claims (3)
Ｐ積層板を用い、該ＣＦＲＰ積層板の表面をアルミナ砂
を用いサンドブラスト処理を行い、かつ該アルミナ砂を
ＣＦＲＰ積層板上に残存させ、該ＣＦＲＰ積層板上に接
着剤を介して金属薄層を形成するようにしたことを特徴
とする混成集積回路用基板の製造方法。(1) CFR with good thermal conductivity and small coefficient of linear expansion
Using a P laminate, sandblast the surface of the CFRP laminate using alumina sand, leave the alumina sand on the CFRP laminate, and apply a thin metal layer onto the CFRP laminate using an adhesive. 1. A method of manufacturing a hybrid integrated circuit board, characterized in that:
を用いるようにしたことを特徴とする特許請求の範囲第
１項記載の混成集積回路用基板の製造方法。(2) The method for manufacturing a hybrid integrated circuit board according to claim 1, wherein an epoxy adhesive with a thickness of 50 μm or less is used as the adhesive.
した前記金属薄層を設け、加熱加圧するようにしたこと
を特徴とする特許請求の範囲第２項記載の混成集積回路
用基板の製造方法。(3) Manufacturing a substrate for a hybrid integrated circuit according to claim 2, characterized in that the metal thin layer is provided on the CFRP laminate via the epoxy adhesive and heated and pressurized. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25370385A JPS62114245A (en) | 1985-11-14 | 1985-11-14 | Manufacture of substrate for hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25370385A JPS62114245A (en) | 1985-11-14 | 1985-11-14 | Manufacture of substrate for hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62114245A true JPS62114245A (en) | 1987-05-26 |
Family
ID=17254974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25370385A Pending JPS62114245A (en) | 1985-11-14 | 1985-11-14 | Manufacture of substrate for hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62114245A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09246752A (en) * | 1996-03-06 | 1997-09-19 | Nec Corp | Package structure of electronic equipment |
| US10674609B2 (en) | 2014-03-31 | 2020-06-02 | Mitsubishi Gas Chemical Company, Inc. | Entry sheet for drilling |
-
1985
- 1985-11-14 JP JP25370385A patent/JPS62114245A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09246752A (en) * | 1996-03-06 | 1997-09-19 | Nec Corp | Package structure of electronic equipment |
| US10674609B2 (en) | 2014-03-31 | 2020-06-02 | Mitsubishi Gas Chemical Company, Inc. | Entry sheet for drilling |
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