JPS61179560A - Composite printed wiring substrate for mounting semiconductor element - Google Patents
Composite printed wiring substrate for mounting semiconductor elementInfo
- Publication number
- JPS61179560A JPS61179560A JP61020693A JP2069386A JPS61179560A JP S61179560 A JPS61179560 A JP S61179560A JP 61020693 A JP61020693 A JP 61020693A JP 2069386 A JP2069386 A JP 2069386A JP S61179560 A JPS61179560 A JP S61179560A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- copper foil
- insulating substrate
- holes
- foil lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体素子実装用複合印刷配線基板に係り、詳
しく述べるとIC,LSIなどの半導体素子を収納する
ための収納穴を有する絶縁基板と上記半導体素子を封止
するに用いる封止樹脂の流出を防止するための枠と導体
間の吸湿防止のための樹脂コートの役目を兼ね備えた絶
縁板とを貼合せた構造の半導体素子実装用複合印刷配線
基板に関するものである。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a composite printed wiring board for mounting semiconductor devices, and more specifically, it relates to an insulating substrate having storage holes for storing semiconductor devices such as ICs and LSIs. Composite for mounting semiconductor elements with a structure in which a frame to prevent the sealing resin used to seal the semiconductor elements from leaking out and an insulating plate that also serves as a resin coat to prevent moisture absorption between the conductors. This invention relates to printed wiring boards.
〈従来の技術とその問題点〉
従来から電子式腕時計、電子式卓上計算機、電子式カメ
ラなどの小型電気回路基板としては、セラミック基板お
るいは合成樹脂製鋼張積層板を用いて、これに所定の回
路を形成し、その基板上にIC,LSIなどの半導体素
子を装着して、金、アルミニウム、などの細線で該半導
体素子と基板上の回路とを接続する方法が実施されてき
た。<Conventional technology and its problems> Traditionally, ceramic substrates or synthetic resin steel-clad laminates have been used as small electric circuit boards for electronic wristwatches, electronic desk calculators, electronic cameras, etc. A method has been implemented in which a circuit is formed, a semiconductor element such as an IC or an LSI is mounted on the substrate, and the semiconductor element and the circuit on the substrate are connected with a thin wire made of gold, aluminum, or the like.
しかしながら、この種電子機器はますます薄型化の要求
が強くなり、このため半導体素子の一部を基板内に埋込
むことによって薄型化をはかる方法が採用されるように
なってきている。However, there is an increasing demand for thinning of this type of electronic equipment, and for this reason, a method of reducing the thickness by embedding a part of the semiconductor element in the substrate is being adopted.
しかして、このような半導体素子を収納するための収納
穴2は、これまでは第1図に示すように銅張積層板より
なる絶縁基板1上に回路3を作成したのち、該絶縁基板
1の所定位置に機械加工によって絶縁基板1の裏面まで
は貫通しないように作られていた。As shown in FIG. 1, the storage hole 2 for storing such a semiconductor element has conventionally been created after a circuit 3 is created on the insulating substrate 1 made of a copper-clad laminate. It was machined at a predetermined position so as not to penetrate to the back surface of the insulating substrate 1.
しかし、この場合穴あ【プ加工中に穴周囲の導体回路が
剥離したり、また穴の底面角部がうまく削れないことか
ら穴の深さの精度が出しにくいなどの欠点とともに、そ
の作業能率が悪いため加工費が高くつくなどの問題があ
った。However, in this case, the conductor circuit around the hole may peel off during drilling, and the bottom corner of the hole cannot be cut properly, making it difficult to accurately determine the depth of the hole. There were problems such as high processing costs due to poor quality.
また絶縁基板1上に接続された半導体素子は、これを機
械的衝撃および湿度、汚れ、温度などの環境条件から保
護するために、エポキシ樹脂などで封止されるのである
が、この封止のために用いる樹脂液の流出を防止するた
めに、流出防止枠4を被封止半導体素子周辺に設ける必
要があり、さらに導体回路間の吸湿による電気絶縁性の
低下を防止するためにエポキシ樹脂などによる樹脂被覆
を施したりしなければならず、このため工程が非常に煩
雑になるという欠点があった。Furthermore, the semiconductor elements connected to the insulating substrate 1 are sealed with epoxy resin or the like in order to protect them from mechanical shock and environmental conditions such as humidity, dirt, and temperature. In order to prevent the leakage of the resin liquid used for this purpose, it is necessary to provide a leakage prevention frame 4 around the semiconductor element to be sealed, and to prevent the electrical insulation from deteriorating due to moisture absorption between the conductor circuits, epoxy resin, etc. This has the disadvantage that the process becomes extremely complicated.
く問題点を解決するための手段〉
本発明は、上記のような従来の回路基板における欠点を
ことごとく解消すべく検討の結果得られたものであって
、半導体素子収納穴とともに半導体素子上にコーティン
グする樹脂のための流出防止枠と基板上に取付けた回路
間の吸湿防止用塗装樹脂を兼ね備えた表面層用絶縁基板
を回路基板上に設けたところの半導体素子実装用印刷配
線基板を安価にしかも容易に提供しようとするものであ
る。Means for Solving the Problems> The present invention was obtained as a result of studies to eliminate all the drawbacks of the conventional circuit boards as described above. A printed wiring board for mounting semiconductor elements is made inexpensive and has an insulating board for the surface layer on the circuit board, which has a frame to prevent the resin from flowing out and a coating resin to prevent moisture absorption between the circuits mounted on the board. It is intended to be provided easily.
〈実施例〉
以下本発明の一実施例を製造工程を示す第2図に基づい
て説明する。<Example> An example of the present invention will be described below based on FIG. 2 showing the manufacturing process.
第2図は従来セラミック等を用いて¥A造されていたL
SIフラットパッケージを合成樹脂製電気絶縁基板の貼
合わせにて得たものでおり、同図(1)が部分断面図、
(It)がその平面図である。Figure 2 shows L, which was conventionally made using ceramic etc.
The SI flat package is obtained by laminating a synthetic resin electrically insulating substrate, and Figure (1) is a partial cross-sectional view.
(It) is a plan view thereof.
図において、11が内層基板であり、この内層基板11
は流動性を有しない接着剤(図示せず)を予めその片面
に塗布した合成樹脂製電気絶縁基板に半導体素子収納穴
12と銅箔リード線22作成用穴21さらに基準孔13
を打法加工によって穿孔したのち銅箔を接着剤塗布面に
熱圧着して銅箔と前記絶縁基板を完全に接着させ、次い
で銅箔リード線作成用穴21にエツチングレジストイン
キ等を埋込み、エツチングにより導体回路14および銅
箔リード線22を形成せしめたのち、前記エツチングレ
ジストインキを除去し、必要により金、ニッケル、銀な
どのメッキを施して得たものである。In the figure, 11 is an inner layer substrate, and this inner layer substrate 11
A synthetic resin electrically insulating substrate on which a non-flowable adhesive (not shown) has been applied on one side in advance has a semiconductor element housing hole 12, a copper foil lead wire 22 forming hole 21, and a reference hole 13.
After punching the holes 21, the copper foil is thermocompressed onto the adhesive-coated surface to completely adhere the copper foil and the insulating substrate, and then etching resist ink or the like is filled into the hole 21 for creating the copper foil lead wire, and etching is performed. After forming the conductor circuit 14 and the copper foil lead wire 22, the etching resist ink was removed, and if necessary, plating with gold, nickel, silver, etc. was performed.
17は表面層用絶縁基板であり、この基板17には半導
体素子収納孔12より大きい穴16と銅箔リード線作成
用穴21と同じ穴および基準孔13を打法加工で穿孔し
である。Reference numeral 17 denotes an insulating substrate for the surface layer, and in this substrate 17, a hole 16 larger than the semiconductor element storage hole 12, a hole the same as the hole 21 for making a copper foil lead wire, and a reference hole 13 are drilled using a hammering method.
また15の底板用絶縁基板はその片面に流動性のない接
着剤(図示せず)を塗布するとともに基準孔13と銅箔
リード線作成用穴21が設けである。Further, the insulating substrate 15 for the bottom plate is coated with a non-flowable adhesive (not shown) on one side thereof, and is provided with a reference hole 13 and a hole 21 for forming a copper foil lead wire.
次いで、上記した内層基板11に対してその上面に表面
層用絶縁基板17を、また下面に底板用絶縁基板15を
それぞれ基準孔13に基づいて加熱加圧によって貼合わ
せると、半導体素子収納穴12と半導体索子封止用樹脂
流出防止枠19および銅箔リード線22を有する本発明
の半導体素子実装用複合印刷配線基板が得られるのであ
る。Next, the surface layer insulating substrate 17 is attached to the upper surface of the inner layer substrate 11, and the bottom plate insulating substrate 15 is bonded to the lower surface of the inner layer substrate 11 by heating and pressing based on the reference hole 13, thereby forming the semiconductor element housing hole 12. A composite printed wiring board for mounting a semiconductor element of the present invention having a resin outflow prevention frame 19 for sealing a semiconductor cord and a copper foil lead wire 22 is obtained.
この実施例による複合基板は、半導体素子を装着し、ワ
イヤーボンディングにて基板導体との接続を行ない、半
導体素子を樹脂封止したのち銅リード線の先端部分を打
法加工により切断することによって得られるのでおり、
従来セラミックなどで製造されていたLSIフラットパ
ッケージが合成樹脂製電気絶縁基板を用いて極めて容易
に且つ安価に製造できるのでおる。The composite board according to this example is obtained by mounting a semiconductor element, connecting it to the board conductor by wire bonding, sealing the semiconductor element with resin, and cutting the tip of the copper lead wire by a hammering process. Because it will be done,
LSI flat packages, which were conventionally made of ceramic or the like, can be manufactured extremely easily and at low cost using synthetic resin electrically insulating substrates.
本発明において用いる合成樹脂電気絶縁基板または合成
樹脂テープ材の種類としては、特に限定されるものでは
なく、例えばエポキシ樹脂ガラス基材積層板、同テープ
材、ポリイミド樹脂ガラス基材積層板、同テープ材、ポ
リイミド樹脂テープ、トリアジン樹脂ガラス基材積層板
、同テープ材などのほか、フェノール樹脂紙基材積層板
、エポキシ樹脂紙基材積層板や熱可塑性樹脂のシート、
成形品などが用いられる。The type of synthetic resin electrical insulating substrate or synthetic resin tape material used in the present invention is not particularly limited, and includes, for example, an epoxy resin glass base laminate, the same tape material, a polyimide resin glass base laminate, and the same tape. In addition to polyimide resin tape, triazine resin glass base laminates, tape materials, etc., phenolic resin paper base laminates, epoxy resin paper base laminates, thermoplastic resin sheets,
Molded products are used.
また合成樹脂絶縁基板の厚さは任意に選択されるが、0
.2#厚の半導体素子を実装する場合を例にとって説明
すると、回路基板としての銅張り絶縁基板11は半導体
素子の厚さに等しい0.2#厚が適当であり、底板用絶
縁基板15は0.05〜0.075m厚のようにできる
だけ薄いものがのぞましくまた表面層用絶縁基板17は
0.2m厚さのものを用いることにより、半導体素子(
LSIチップ)を実装後の複合印刷配線基板としての総
厚さは0.5#となり、はぼホンディング用ワイヤを含
めた半導体素子の厚さに近い薄葉化が可能となるのであ
る。Furthermore, the thickness of the synthetic resin insulating substrate can be selected arbitrarily;
.. Taking the case of mounting a 2# thick semiconductor element as an example, it is appropriate that the copper-clad insulating substrate 11 as a circuit board has a thickness of 0.2#, which is equal to the thickness of the semiconductor element, and the bottom plate insulating substrate 15 has a thickness of 0.2#, which is equal to the thickness of the semiconductor element. It is preferable that the insulating substrate 17 for the surface layer be as thin as possible, such as 0.05 to 0.075 m thick, and by using a 0.2 m thick one, the semiconductor element (
The total thickness of the composite printed wiring board after mounting the LSI chip (LSI chip) is 0.5 #, making it possible to make the board as thin as the thickness of the semiconductor element, including wires for honding.
内層基板11と底板用絶縁基板15および表面層用
′絶縁基板17の貼合せに用いる接着剤としては特に限
定はないが、接着作業時に接着剤が流動すると半導体素
子収納穴や封止用樹脂流出防止枠内および部品取付孔な
どが接着剤で埋められるおそれがあるので接着剤は流動
しないことだりが必須条件であり、それに適うものとし
てブチラールフェノール樹脂、ブチラールフェノール樹
脂とエポキシ樹脂の混合物、ナイロンとブチラールフェ
ノール樹脂の混合物、ナイロンとブチラール樹脂および
エポキシ樹脂の混合物あるいは各種熱融着フィルムなど
が好ましい。Inner layer substrate 11, bottom plate insulating substrate 15, and surface layer
'The adhesive used for bonding the insulating substrate 17 is not particularly limited, but if the adhesive flows during the bonding process, the semiconductor element housing hole, the inside of the sealing resin leakage prevention frame, the component mounting hole, etc. may be filled with the adhesive. It is essential that the adhesive does not flow, as there is a risk of the adhesive flowing, and suitable adhesives include butyral phenol resin, a mixture of butyral phenol resin and epoxy resin, a mixture of nylon and butyral phenol resin, and nylon and butyral resin and epoxy resin. A mixture of these or various heat-sealable films are preferred.
本発明において銅張り積層絶縁基板と底板用絶縁基板お
よび表面層用絶縁基板との貼合わせは各基板に穿孔した
基準孔を合致させることにより連続的に行なわれ、ホッ
トロールを用いて圧力20〜40に’j4.150〜1
80℃の加圧、加熱下で30分間熱圧すればよく、必要
に応じて150’Cで2〜4時間アフターキュアーを行
なってもよい。In the present invention, the copper-clad laminated insulating substrate, the insulating substrate for the bottom plate, and the insulating substrate for the surface layer are laminated continuously by matching the reference holes drilled in each substrate, and using a hot roll at a pressure of 20 to 40 to'j4.150~1
It is sufficient to carry out hot pressing for 30 minutes under pressure and heat at 80°C, and if necessary, after-cure may be performed at 150'C for 2 to 4 hours.
本発明による半導体素子実装用複合印刷配線基板の他の
利点は、半導体素子の実装、封止樹脂注型、同樹脂のキ
ュアー、検査などが自動的に行なえるため非常に生産能
率が向上することである。Another advantage of the composite printed wiring board for semiconductor device mounting according to the present invention is that mounting of semiconductor devices, casting of sealing resin, curing of the resin, inspection, etc. can be performed automatically, which greatly improves production efficiency. It is.
即ち、絶縁基板上に複数個以上の回路を形成し、これに
前述の如く底板用絶縁基板と表面層用絶縁基板を貼合わ
せて複合基板とした連続長尺物を所要の長さに裁断して
積載し、下部から一枚づつコンベヤ上に取出して基準孔
に基づいて半導体素子の装着とワイヤーボンディングを
行ない、次の工程で連続的に封止用樹脂の注入が行なわ
れ、さらに硬化炉へ導かれ、最後に外径を打扱くことに
より、半導体素子実装済み回路基板が得られるのである
。That is, a plurality of circuits or more are formed on an insulating substrate, and an insulating substrate for the bottom plate and an insulating substrate for the surface layer are bonded to this as described above to form a continuous long composite substrate, which is then cut to the required length. The semiconductor devices are loaded one by one onto a conveyor from the bottom, and semiconductor elements are mounted and wire bonded based on the reference holes. In the next process, sealing resin is continuously injected, and then sent to a curing furnace. By finally handling the outer diameter, a circuit board with semiconductor elements mounted thereon is obtained.
の構造を示す拡大断面図、第2図は(n)は同上の部分
平面図である。
11・・・内層用絶縁基板 12・・・収納穴1
4・・・回路 15・・・底板用絶縁
基板17・・・表面層用絶縁基板
21・・・銅箔リード線作成用穴
22・・・銅箔リード線FIG. 2(n) is an enlarged sectional view showing the structure of the same. 11... Insulating board for inner layer 12... Storage hole 1
4... Circuit 15... Insulating substrate for bottom plate 17... Insulating substrate for surface layer 21... Hole for making copper foil lead wire 22... Copper foil lead wire
Claims (1)
は合成樹脂テープの所定位置に半導体素子収納孔と銅箔
リード線作成用穴、さらに基準孔を穿孔したのち、銅箔
を接着剤塗布面に熱圧着し、次いで銅箔リード線作成用
穴にエッチングレジストインキを埋込み、エッチングに
より導体回路および銅箔リード線を形成せしめた内層基
板の一方の面に、半導体素子収納孔より大きい穴と銅箔
リード線作成用穴および基準孔を穿孔し¥さらに半導¥
¥体素子封止用樹脂流出防止枠を有する¥表面層用絶縁
基板を、他面に銅箔リード線作成用穴と基準孔を穿孔し
た底板用絶縁基板を貼合せたことを特徴とする半導体素
子実装用複合印刷配線基板。After drilling a semiconductor element housing hole, a hole for creating a copper foil lead wire, and a reference hole in the specified position of a synthetic resin electrical insulating board or synthetic resin tape coated with adhesive on one side, place the copper foil on the adhesive coated side. After thermal compression bonding, etching resist ink was filled in the hole for creating the copper foil lead wire, and a conductor circuit and the copper foil lead wire were formed by etching.On one side of the inner layer board, a hole larger than the semiconductor element storage hole and the copper foil were formed. Drill a hole for making lead wires and a reference hole, and then make a semi-conductor.
A semiconductor characterized in that an insulating substrate for a surface layer having a frame for preventing resin leakage for sealing a component element is bonded to an insulating substrate for a bottom plate having a hole for making a copper foil lead wire and a reference hole on the other side. Composite printed wiring board for device mounting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61020693A JPS61179560A (en) | 1986-01-31 | 1986-01-31 | Composite printed wiring substrate for mounting semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61020693A JPS61179560A (en) | 1986-01-31 | 1986-01-31 | Composite printed wiring substrate for mounting semiconductor element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61179560A true JPS61179560A (en) | 1986-08-12 |
JPS623580B2 JPS623580B2 (en) | 1987-01-26 |
Family
ID=12034232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61020693A Granted JPS61179560A (en) | 1986-01-31 | 1986-01-31 | Composite printed wiring substrate for mounting semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61179560A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0569949A3 (en) * | 1992-05-12 | 1994-06-15 | Akira Kitahara | Surface mount components and semifinished products thereof |
-
1986
- 1986-01-31 JP JP61020693A patent/JPS61179560A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0569949A3 (en) * | 1992-05-12 | 1994-06-15 | Akira Kitahara | Surface mount components and semifinished products thereof |
US5440452A (en) * | 1992-05-12 | 1995-08-08 | Akira Kitahara | Surface mount components and semifinished products thereof |
US5568363A (en) * | 1992-05-12 | 1996-10-22 | Kitahara; Akira | Surface mount components and semifinished products thereof |
Also Published As
Publication number | Publication date |
---|---|
JPS623580B2 (en) | 1987-01-26 |
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