JPH0427021B2 - - Google Patents

Info

Publication number
JPH0427021B2
JPH0427021B2 JP62242046A JP24204687A JPH0427021B2 JP H0427021 B2 JPH0427021 B2 JP H0427021B2 JP 62242046 A JP62242046 A JP 62242046A JP 24204687 A JP24204687 A JP 24204687A JP H0427021 B2 JPH0427021 B2 JP H0427021B2
Authority
JP
Japan
Prior art keywords
adhesive
wiring board
bonded
wiring boards
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62242046A
Other languages
Japanese (ja)
Other versions
JPS6485740A (en
Inventor
Takeshi Kano
Tooru Higuchi
Muneisa Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242046A priority Critical patent/JPS6485740A/en
Publication of JPS6485740A publication Critical patent/JPS6485740A/en
Publication of JPH0427021B2 publication Critical patent/JPH0427021B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

Description

【発明の詳細な説明】[Detailed description of the invention]

[技術分野] 本発明は、多層のプリント配線板などとして用
いられる多層積層板の製造方法に関するものであ
る。 [背景技術] ピングリツドアレイなど半導体パツケージの基
板を多層のプリント配線板で形成したものが従来
から提供されている。そしてこのような半導体パ
ツケージを製造するにあたつては第10図に示す
ようにしておこなわれる。すなわち、一方の配線
基板1aの表面に半導体チツプ4を実装するため
の凹部6を形成すると共に半導体チツプ4と接続
するためのボンデイング部7が凹部6の近傍に位
置するように凹部6を中心とする放射状に回路5
を形成し、他方の配線基板1bには凹部6より大
きな開口部3を表裏に貫通して設けると共に表面
に銅箔などの金属箔8が積層してある。そして第
10図aのように開口部3内に凹部6と回路5の
ボンデイング部7とが露出されるように位置合わ
せした状態で一方の配線基板1aに他方の配線基
板1bを重ねる。このとき開口部3以外の部分に
おいて配線基板1aと配線基板1bとの間にプリ
プレグで形成される接着材2を挟み込むように
し、これらを加熱加圧成形することによつて第1
0図bのように接着材2によつて配線基板1a,
1bを積層一体化させた多層積層板を得ることが
できる。そしてこのように作成される多層積層板
において、配線基板1bの金属箔8にエツチング
加工などを施して回路9を形成する。この回路9
が外層回路となると共に配線基板1aに設けた回
路5が内層回路となる。こののちに、開口部3の
内方において凹部6に半導体チツプ4を搭載して
実装すると共に、半導体チツプ4と回路5のボン
デイング部7との間、及び回路9の開口部3に近
接する端部のボンデイング部10との間に、金線
などのワイヤー11をボンデイングし、半導体チ
ツプ4と回路5,9とを電気的に接続させること
によつて半導体パツケージとして仕上げるのであ
る。 しかしこのものにあつて、配線基板1a,1b
を加熱加圧することによつて接着材2の接着樹脂
が一旦溶融したのちに硬化することで接着作用を
発揮し、配線基板1a,1bを積層接着させるこ
とができるのであるが、この際の加圧作用で接着
材2の溶融した接着樹脂の流れが大きく生じ、多
層積層板の板厚のばらつきが大きく発生したりあ
るいは反りが発生したりするおそれがある。特に
多層板を半導体パツケージの基板として用いる場
合に、このように接着材2の接着樹脂に流れが大
きく生じると、積層基板1a,1bの間からの接
着樹脂が大きくはみ出し、第11図に示すように
接着樹脂のはみ出し部2aが回路5のボンデイン
グ部7に作用し、ボンデイング部4が接着材2で
覆われて半導体チツプ4と回路5との間の電気的
接続の信頼性を確保できなくなるおそれがあると
いう問題があつた。。 [発明の目的] 本発明は、上記の点に鑑みて為されたものであ
り、接着材の接着樹脂の流れが大きく生じるおそ
れなく配線基板を積層することができる多層積層
板の製造方法を提供することを目的とするもので
ある。 [発明の開示] しかし本発明は、熱硬化性樹脂の接着材2を介
して配線基板1a,1b同士を積層接着して多層
積層板を製造するためにあたつて、接着材2を少
なくとも片側の配線基板1a,1bに予め加熱接
着しておき、この接着材2を介して配線基板1
a,1b同士を重ねて加熱加圧することによつて
配線基板1a,1bを積層接着することを特徴と
するものであり、接着材2を予め配線基板1a,
1bに加熱接着させておくことによつて接着材2
の接着樹脂の硬化の度合を進めておき、接着材2
の接着樹脂の溶融粘度を高めておいて流動性が小
さくなるようにしたものであつて、以下本発明を
実施例により詳述する。 まず本発明を一対の配線基板1a,1bの積層
で多層積層板を形成すると共にこの多層積層板を
半導体パツケージの基板に用いるようにした第1
図の実施例について説明する。配線基板1a,1
bは樹脂積層板などによつて形成されるものであ
り、一方側の配線基板1aの表面には銅箔など金
属箔も積層してこれをエツチング加工することに
よつて回路5が設けてある。また配線基板1aの
ほぼ中央部においてその表面に半導体チツプ4を
実装するための凹部6が形成してあり、回路5は
半導体チツプ4と接続するためのボンデイング部
7が凹部6の近傍に位置するように凹部6を中心
とした放射状のパターンで形成するようにしてあ
る。他方側の配線基板1bの片側表面には銅箔な
どの金属箔8が積層接着してあり、そのほぼ中央
部には凹部6よりも大きな開口部3が表裏に貫通
して設けてある。 そしてこの配線基板1a,1bを用いて多層積
層板を製造するにあたつては、まず一方の配線基
板1bに接着材2を予め接着させておく。接着材
2としては、ガラス織布やガラス不織布などを基
材としてこれにエポキシ樹脂やポリイミドなどの
熱硬化性樹脂を含浸させ、加熱乾燥することによ
つて熱硬化性樹脂を半硬化(Bステージ)させた
ボンデイング用のプリプレグを用いることができ
る。もちろんプリプレグの他に熱硬化性樹脂にガ
ラス繊維などを混入して調製した接着材2を用い
ることもできる。このようにプリプレグなどによ
つて形成される接着材2を一方の配線基板1bに
重ねて加熱すると共に必要に応じて加圧すること
によつて、予め一方の配線基板1bに接着させて
おくのである。このとき加熱の温度や時間、圧力
は、接着材2の樹脂が完全に硬化せず、流れ過ぎ
ず、接着性能を大きく損なわない範囲に設定され
る。例えば接着材2の接着樹脂がエポキシ樹脂の
場合は90〜170℃で5〜120分間程度、ポリイミド
の場合は90〜220℃で5〜120分間程度である。圧
力はそれぞれ1〜70Kg/cm2程度である。また、上
記のように配線基板1bに開口部3を形成するに
あたつては、配線基板1bに接着材2を接着させ
たのちに接着材2とともに配線基板1bを穿孔加
工して開口部3を設けるようにするのがよい。 このように配線基板1bに予め接着材2を加熱
接着したのちに、第1図aのように開口部3内に
凹部6と回路5のボンデイング部7とが位置する
ように位置合わせした状態で配線基板1bを配線
基板1aの表面に重ねる。そして次に加熱加圧成
形することによつて接着材2を介して配線基板1
a,1bを積層一体化させ、多層配線板Aを得る
のである。この成形は接着材2の接着樹脂を完全
に硬化させるように加熱条件を設定するものであ
り、例えば接着材2の接着樹脂がエポキシ樹脂の
場合は160〜180℃で50〜120分間程度、ポリイミ
ドの場合は200〜250℃で50〜120分間程度である。
このとき、接着材2の接着樹脂は加熱作用によつ
て一旦溶融したのちに硬化するが、この接着樹脂
は予め配線基板1bに接着される際の加熱で硬化
の度合が進行しており、今回の成形の際に溶融さ
れてもその溶融粘度が高まつているために流動性
は低く、加圧作用で配線基板1a,1bの間から
接着樹脂が大きく流れ出すことを防止することが
でき、多層配線板Aに板厚のばらつきが大きく生
じたり反りが発生したりすることを防止すること
ができる。特にこの多層配線板Aを半導体パツケ
ージに用いる場合に開口部3の内方へ接着樹脂が
はみ出して流れ、接着樹脂で回路5のボンデイン
グ部7が覆われてしまうようなことを防ぐことが
できる。 このようにして得られる多層配線板Aを半導体
パツケージに加工するにあたつては、まず配線基
板1bの金属箔8にエツチング加工などを施して
回路9を形成する。この回路9は開口部3を中心
とする放射状のパターンで形成されるものであ
り、この回路9が外層回路となると共に配線基板
1aに設けた回路5は配線基板1a,1b間に埋
入されて内層回路となる。こののちに、凹部6に
ICチツプなどの半導体チツプ4を搭載して実装
し、さらに第1図bに示すように半導体チツプ4
と回路5のボンデイング部7との間、及び回路9
の開口部3に近接する端部のボンデイング部10
との間に、金線などのワイヤー11をボンデイン
グし、半導体チツプ4と回路5,11とを電気的
に接続させることによつて半導体パツケージとし
て形成するのである。各回路5,11にはそれぞ
れ外部への接続端子部が接続されるが、このの接
続端子部として例えばピンを用いることによつて
半導体パツケージをピングリツドアレイとして形
成することができる。 上記第1図の実施例では接着材2を予め配線基
板1bに接着しておくようにしたが、第2図の実
施例のように配線基板1aの側に接着材2を接着
しておくようにしてもよく、第3図のように配線
基板1a,1bの両方に接着材2を予め接着して
おくようにしてもよい。また第4図の実施例は、
接着材2を予め接着した配線基板1bの開口部3
に対応して配線基板1aにも開口部3を形成した
もの、第5図の実施例は開口部3を形成した配線
基板1aに接着材2を予め接着するようにしたも
の、第6図の実施例は配線基板1a,1bの両方
に予め接着材2を接着するようにしたものを示す
ものであり、さらに第7図の実施例は三枚の配線
基板1a,1b,1cを用いて多層積層板Aを形
成するようにしたものである。また上記各実施例
では配線基板1a,1b,1cのちの少なくとも
一つに開口部3を設けるようにしたが、第8図や
第9図のように開口部3を設けない配線基板1
a,1b,1cを用いて多層積層板Aを作成する
ようにしてもよい。さらに多層積層板Aにスルー
ホールを穿孔加工して設けることもできる。この
ようにスルーホールを設けるにあたつて、上記実
施例のように接着材2として基材が含有されるも
のを用いると、スルーホールの内面に基材が露出
することになり、スルーホールメツキとの接着性
が高まつてスルーホールメツキの剥離を防止する
ことができる。尚、本発明は上記半導体パツケー
ジに適用する他、チツプオンボード基板やプリン
ト配線板などにも適用することができる。 次に本発明を具体的な実施例によつて例証す
る。 実施例 1 配線基板1a,1bとしてそれぞれガラス織布
基材エポキシ樹脂積層板を用い、また接着材2と
してガラス織布基材エポキシ樹脂のプリプレグを
用い、配線基板1bに接着材2を予め接着した
(第1図a)。接着の際の条件を第1表に示す。次
に配線基板1a,1bを重ねて加熱加圧成形する
ことによつて、接着材2を介して配線基板1a,
1bを積層一体化し、多層積層板Aを得た(第1
図b)。このときの成形条件を第1表に示す。 実施例 2〜6 配線基板1a,1bとして第1表に示すものを
用いると共に接着材2として第1表に示すものを
用い、あとは実施例1と同様にして第1表の条件
に従つて多層積層板Aを得た。 比較例 1〜3 配線基板1a,1bとして第1表に示すものを
用いると共に接着材2として第1表に示すものを
用い、接着材2を予め配線基板1a,1bに接着
しておくことなく、接着材2を配線基板1a,1
bの間に挟んだ状態で第1表の条件に従つて成形
をおこなうことによつて、多層積層板Aを得た。 上記実施例1〜6及び比較例1〜3のものにつ
いて、接着材2の接着樹脂の流れと多層積層板A
の厚みのばらつきとを測定した。厚みのばらつき
の測定は縦横300×300mmの試験片についておこな
つた。結果を第1表に示す。
[Technical Field] The present invention relates to a method for manufacturing a multilayer laminate used as a multilayer printed wiring board or the like. [Background Art] Semiconductor package substrates such as pin grid arrays formed of multilayer printed wiring boards have been provided in the past. The manufacturing of such a semiconductor package is carried out as shown in FIG. That is, a recess 6 for mounting the semiconductor chip 4 is formed on the surface of one wiring board 1a, and the recess 6 is centered so that the bonding part 7 for connecting to the semiconductor chip 4 is located near the recess 6. Radial circuit 5
The other wiring board 1b has an opening 3 larger than the recess 6 penetrating the front and back sides thereof, and a metal foil 8 such as copper foil is laminated on the surface. Then, as shown in FIG. 10a, one wiring board 1a is stacked on the other wiring board 1b with alignment such that the recess 6 and the bonding part 7 of the circuit 5 are exposed in the opening 3. At this time, an adhesive material 2 made of prepreg is sandwiched between the wiring board 1a and the wiring board 1b in a portion other than the opening 3, and the first
As shown in Figure 0b, the wiring board 1a,
A multilayer laminate in which 1b is laminated and integrated can be obtained. In the multilayer laminate thus produced, a circuit 9 is formed by etching or the like on the metal foil 8 of the wiring board 1b. This circuit 9
serves as an outer layer circuit, and the circuit 5 provided on the wiring board 1a serves as an inner layer circuit. Thereafter, the semiconductor chip 4 is mounted and mounted in the recess 6 inside the opening 3, and the semiconductor chip 4 is mounted between the semiconductor chip 4 and the bonding part 7 of the circuit 5, and the end of the circuit 9 near the opening 3 is mounted. A wire 11 such as a gold wire is bonded between the bonding part 10 of the semiconductor chip 4 and the circuits 5 and 9, thereby completing a semiconductor package. However, in this case, wiring boards 1a and 1b
By applying heat and pressure to the adhesive resin, the adhesive resin of the adhesive material 2 is melted and then hardened, thereby exerting an adhesive effect and making it possible to bond the wiring boards 1a and 1b in a laminated manner. Due to the pressure action, a large flow of the molten adhesive resin of the adhesive material 2 occurs, which may cause large variations in the thickness of the multilayer laminate or cause warping. Particularly when a multilayer board is used as a substrate for a semiconductor package, if a large flow occurs in the adhesive resin of the adhesive 2, the adhesive resin from between the laminated boards 1a and 1b will protrude, as shown in FIG. There is a risk that the protruding portion 2a of the adhesive resin acts on the bonding portion 7 of the circuit 5, and the bonding portion 4 is covered with the adhesive 2, making it impossible to ensure the reliability of the electrical connection between the semiconductor chip 4 and the circuit 5. There was a problem that there was. . [Objective of the Invention] The present invention has been made in view of the above points, and provides a method for manufacturing a multilayer laminate that allows wiring boards to be stacked without the risk of large flow of adhesive resin of adhesive material. The purpose is to [Disclosure of the Invention] However, in order to manufacture a multilayer laminate by laminating and bonding wiring boards 1a and 1b together via an adhesive 2 made of a thermosetting resin, the adhesive 2 is attached to at least one side of the adhesive 2. The wiring boards 1a and 1b are heated and bonded in advance to the wiring boards 1a and 1b through the adhesive 2.
The wiring boards 1a and 1b are laminated and bonded by stacking the wiring boards 1a and 1b on top of each other and applying heat and pressure.
Adhesive material 2 is bonded to adhesive material 1b by heating.
Advance the degree of curing of the adhesive resin, and then apply adhesive 2.
The adhesive resin has a high melt viscosity and low fluidity.The present invention will be described in detail below with reference to Examples. First, the present invention is applied to a first embodiment in which a multilayer laminate is formed by laminating a pair of wiring boards 1a and 1b, and this multilayer laminate is used as a substrate of a semiconductor package.
The embodiment shown in the figure will be explained. Wiring board 1a, 1
b is formed of a resin laminate or the like, and a circuit 5 is provided by laminating metal foil such as copper foil on the surface of the wiring board 1a on one side and etching this. . Further, a recess 6 for mounting the semiconductor chip 4 is formed on the surface of the wiring board 1a at approximately the center thereof, and a bonding portion 7 for connecting the circuit 5 to the semiconductor chip 4 is located near the recess 6. They are formed in a radial pattern with the recess 6 at the center. A metal foil 8 such as a copper foil is laminated and bonded to one surface of the other wiring board 1b, and an opening 3 larger than the recess 6 is provided approximately in the center thereof, penetrating the front and back sides. When manufacturing a multilayer laminate using these wiring boards 1a and 1b, adhesive material 2 is first bonded to one wiring board 1b in advance. The adhesive material 2 is made of glass woven fabric or glass non-woven fabric as a base material, impregnated with thermosetting resin such as epoxy resin or polyimide, and heated and dried to semi-cure the thermosetting resin (B stage). ) prepreg for bonding can be used. Of course, in addition to prepreg, it is also possible to use the adhesive 2 prepared by mixing glass fiber or the like into a thermosetting resin. In this way, the adhesive material 2 made of prepreg or the like is layered on one wiring board 1b and heated and, if necessary, pressurized to adhere it to the other wiring board 1b in advance. . At this time, the heating temperature, time, and pressure are set within a range that does not completely cure the resin of the adhesive material 2, does not flow too much, and does not significantly impair adhesive performance. For example, when the adhesive resin of the adhesive material 2 is an epoxy resin, the time is about 5 to 120 minutes at 90 to 170°C, and when it is polyimide, it is about 5 to 120 minutes at 90 to 220°C. The pressure is about 1 to 70 kg/cm 2 , respectively. Furthermore, in forming the opening 3 in the wiring board 1b as described above, after adhering the adhesive 2 to the wiring board 1b, the wiring board 1b is punched together with the adhesive 2 to form the opening 3. It is better to provide a After the adhesive 2 is heat-bonded to the wiring board 1b in advance in this way, the recess 6 and the bonding part 7 of the circuit 5 are aligned in the opening 3 as shown in FIG. 1a. The wiring board 1b is stacked on the surface of the wiring board 1a. Then, the wiring board 1 is bonded through the adhesive 2 by heating and pressure molding.
A and 1b are laminated and integrated to obtain a multilayer wiring board A. In this molding, the heating conditions are set so that the adhesive resin of adhesive material 2 is completely cured. For example, if the adhesive resin of adhesive material 2 is epoxy resin, polyimide In this case, the temperature is 200-250℃ for about 50-120 minutes.
At this time, the adhesive resin of the adhesive material 2 is once melted by the heating action and then hardened, but the degree of hardening of this adhesive resin has already progressed due to the heating when it is bonded to the wiring board 1b, and this time Even if it is melted during molding, its fluidity is low due to its high melt viscosity, and it is possible to prevent the adhesive resin from flowing out from between the wiring boards 1a and 1b due to the pressure action. It is possible to prevent the wiring board A from having a large variation in thickness or from being warped. Particularly when this multilayer wiring board A is used in a semiconductor package, it is possible to prevent the adhesive resin from flowing inwardly into the opening 3 and covering the bonding portion 7 of the circuit 5 with the adhesive resin. In processing the thus obtained multilayer wiring board A into a semiconductor package, first, a circuit 9 is formed by etching the metal foil 8 of the wiring board 1b. This circuit 9 is formed in a radial pattern centered on the opening 3, and this circuit 9 serves as an outer layer circuit, and the circuit 5 provided on the wiring board 1a is embedded between the wiring boards 1a and 1b. This becomes an inner layer circuit. After this, in the recess 6
A semiconductor chip 4 such as an IC chip is mounted and mounted, and the semiconductor chip 4 is further mounted as shown in FIG. 1b.
and the bonding part 7 of the circuit 5, and the circuit 9
bonding portion 10 at the end close to the opening 3 of the
A wire 11 such as a gold wire is bonded between the semiconductor chip 4 and the circuits 5 and 11, thereby forming a semiconductor package. Each of the circuits 5 and 11 is connected to a connection terminal portion to the outside, and by using, for example, a pin as the connection terminal portion, the semiconductor package can be formed as a pin grid array. In the embodiment shown in FIG. 1, the adhesive 2 is bonded to the wiring board 1b in advance, but in the embodiment shown in FIG. 2, the adhesive 2 is bonded to the wiring board 1a side. Alternatively, as shown in FIG. 3, adhesive material 2 may be bonded to both wiring boards 1a and 1b in advance. In addition, the embodiment shown in FIG.
Opening 3 of wiring board 1b to which adhesive 2 has been bonded in advance
In the embodiment shown in FIG. 5, an opening 3 is also formed in the wiring board 1a corresponding to the above, and in the embodiment shown in FIG. The embodiment shows an adhesive 2 bonded to both wiring boards 1a, 1b in advance, and the embodiment shown in FIG. 7 uses three wiring boards 1a, 1b, 1c to form a multilayer structure. A laminate A is formed. Further, in each of the above embodiments, the opening 3 is provided in at least one of the wiring boards 1a, 1b, and 1c, but as shown in FIGS. 8 and 9, the wiring board 1 without the opening 3
A, 1b, and 1c may be used to create a multilayer laminate A. Furthermore, through holes can be formed in the multilayer laminate A by drilling. When forming a through hole in this way, if a material containing a base material is used as the adhesive material 2 as in the above embodiment, the base material will be exposed on the inner surface of the through hole, making it difficult to plate the through hole. This increases the adhesion with the through-hole plating and prevents it from peeling off. The present invention can be applied not only to the semiconductor package described above, but also to chip-on-board substrates, printed wiring boards, and the like. The invention will now be illustrated by specific examples. Example 1 Glass woven fabric base epoxy resin laminates were used as the wiring boards 1a and 1b, and a glass woven fabric base epoxy resin prepreg was used as the adhesive 2, and the adhesive 2 was bonded to the wiring board 1b in advance. (Figure 1a). Table 1 shows the conditions for adhesion. Next, by stacking the wiring boards 1a and 1b and molding them under heat and pressure, the wiring boards 1a and 1b are bonded via the adhesive 2.
1b was laminated and integrated to obtain a multilayer laminate A (first
Figure b). The molding conditions at this time are shown in Table 1. Examples 2 to 6 The wiring boards 1a and 1b used are those shown in Table 1, and the adhesive 2 is used as shown in Table 1, and the rest is carried out in the same manner as in Example 1 according to the conditions in Table 1. A multilayer laminate A was obtained. Comparative Examples 1 to 3 The wiring boards 1a and 1b were used as shown in Table 1, and the adhesive 2 was as shown in Table 1, without having to adhere the adhesive 2 to the wiring boards 1a and 1b in advance. , the adhesive 2 is attached to the wiring boards 1a, 1
A multilayer laminate A was obtained by performing molding in accordance with the conditions shown in Table 1 while sandwiching between the two layers. Regarding the above Examples 1 to 6 and Comparative Examples 1 to 3, the flow of adhesive resin of adhesive material 2 and multilayer laminate A
The variation in thickness was measured. The thickness variation was measured on test pieces measuring 300 mm x 300 mm in length and width. The results are shown in Table 1.

【表】 第1表にみられるように、接着材2を予め配線
基板1bに接着しておくようにした各実施例のも
のでは、接着樹脂の流れが小さくなつていると共
板厚のばらつきが小さくなつて板厚精度が高まる
ことが確認される。 [発明の効果] 上述のように本発明にあつては、接着材を配線
基板に予め加熱接着しておき、この接着材を介し
て配線基板同士を重ねて加熱加圧することによつ
て配線基板を積層接着するようにしたので、接着
樹脂は予め配線基板に接着される際の加熱で硬化
の度合が進行しており、積層する際にこの接着樹
脂が溶融されても溶融粘度が高まつていて、接着
樹脂が大きく流れることを防止することができる
ものである。
[Table] As shown in Table 1, in each of the examples in which the adhesive 2 is bonded to the wiring board 1b in advance, if the flow of the adhesive resin becomes small, the plate thickness will vary. It is confirmed that the plate thickness accuracy increases as the value decreases. [Effects of the Invention] As described above, in the present invention, an adhesive is heat-bonded to a wiring board in advance, and the wiring boards are stacked on top of each other via the adhesive and heated and pressurized to form a wiring board. Since the adhesive resin is laminated and bonded, the degree of hardening of the adhesive resin is progressing due to heating when it is bonded to the wiring board in advance, and even if this adhesive resin is melted during lamination, the melt viscosity increases. This makes it possible to prevent the adhesive resin from flowing significantly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本発明の一実施例の一部切欠断
面図、第2図乃至第9図はそれぞれ本発明の他の
実施例の一部の縮小断面図、第10図a,bは従
来例の断面図、第11図は従来例の一部の斜視図
である。 1は配線基板、2は接着材、3は開口部、4は
半導体チツプである。
FIGS. 1a and 1b are partially cutaway sectional views of one embodiment of the present invention, FIGS. 2 to 9 are partially reduced sectional views of other embodiments of the present invention, and FIGS. 10a and b 11 is a sectional view of a conventional example, and FIG. 11 is a perspective view of a part of the conventional example. 1 is a wiring board, 2 is an adhesive, 3 is an opening, and 4 is a semiconductor chip.

Claims (1)

【特許請求の範囲】 1 熱硬化性樹脂の接着材を介して配線基板同士
を積層接着して多層積層板を製造するにあたつ
て、接着材を少なくとも片側の配線基板に予め加
熱接着しておき、この接着材を介して配線基板同
士を重ねて加熱加圧することによつて配線基板を
積層接着することを特徴とする多層積層板の製造
方法。 2 接着材はボンデイング用のプリプレグである
ことを特徴とする特許請求の範囲第1項記載の多
層積層板の製造方法。 3 積層する少なくとも一つの配線基板には貫通
する開口部が設けられており、この開口部の内方
に半導体チツプが実装されるようにした特許請求
の範囲第1項又は第2項記載の多層積層板の製造
方法。
[Scope of Claims] 1. When manufacturing a multilayer laminate by laminating and bonding wiring boards to each other via a thermosetting resin adhesive, the adhesive is heat-bonded to at least one wiring board in advance. 1. A method for manufacturing a multilayer laminate, characterized in that the wiring boards are laminated and bonded by stacking the wiring boards on top of each other via the adhesive and applying heat and pressure. 2. The method for manufacturing a multilayer laminate according to claim 1, wherein the adhesive is a prepreg for bonding. 3. The multilayer according to claim 1 or 2, wherein at least one wiring board to be laminated is provided with a penetrating opening, and a semiconductor chip is mounted inside the opening. Method of manufacturing laminates.
JP62242046A 1987-09-26 1987-09-26 Manufacture of multi-layer laminate Granted JPS6485740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242046A JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242046A JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Publications (2)

Publication Number Publication Date
JPS6485740A JPS6485740A (en) 1989-03-30
JPH0427021B2 true JPH0427021B2 (en) 1992-05-08

Family

ID=17083463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242046A Granted JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Country Status (1)

Country Link
JP (1) JPS6485740A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016108228B4 (en) * 2016-05-03 2020-08-06 Lisa Dräxlmaier GmbH Method and device for welding components
CN106714476A (en) * 2017-02-15 2017-05-24 昆山大洋电路板有限公司 Novel four-layer board blind hole/step processing technique

Also Published As

Publication number Publication date
JPS6485740A (en) 1989-03-30

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