JP4622449B2 - Electronic component built-in substrate and manufacturing method thereof - Google Patents

Electronic component built-in substrate and manufacturing method thereof Download PDF

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JP4622449B2
JP4622449B2 JP2004306656A JP2004306656A JP4622449B2 JP 4622449 B2 JP4622449 B2 JP 4622449B2 JP 2004306656 A JP2004306656 A JP 2004306656A JP 2004306656 A JP2004306656 A JP 2004306656A JP 4622449 B2 JP4622449 B2 JP 4622449B2
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insulating layer
electronic component
substrate
support pattern
component built
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JP2006120829A (en
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英司 川本
和彦 本城
敏彦 森
俊行 朝日
康博 菅谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

本発明は、電子部品が埋設された電子部品内蔵基板とその製造方法に関するものである。 The present invention relates to an electronic component an electronic component-embedded substrate that is embedded and its manufacturing how.

従来、この種の電子部品内蔵基板は、図6、図7に示されるような構成を有していた。   Conventionally, this type of electronic component built-in substrate has a configuration as shown in FIGS.

図6、図7に従来の電子部品内蔵基板の製造方法を示す。   6 and 7 show a conventional method for manufacturing an electronic component built-in substrate.

まず図6(a)に示すように下層配線基板11上の接着領域に導電性粒子を配合した異方性または等方性の半導体素子用接着剤19を適用し、次に図6(b)に示すように、下層配線基板11の配線パターンp上の接続部12にベアの半導体素子16の電極端子17を接続し、加熱・加圧して半導体素子16を実装する。そして、図6(c)に示すように、半導体素子16に対応する部分をくり抜いた中間配線基板21の下面にプリプレグ13を適用したものを下層配線基板11に重ね合わせ、更に上層配線基板31の下面にプリプレグ13を適用したものを中間配線基板21の上面に重ね合わせている。   First, as shown in FIG. 6A, an anisotropic or isotropic semiconductor element adhesive 19 in which conductive particles are blended is applied to the adhesion region on the lower wiring substrate 11, and then FIG. 6B. As shown in FIG. 2, the electrode terminal 17 of the bare semiconductor element 16 is connected to the connection portion 12 on the wiring pattern p of the lower wiring substrate 11, and the semiconductor element 16 is mounted by heating and pressing. Then, as shown in FIG. 6C, the lower wiring board 11 is overlaid with the lower wiring board 11 on which the prepreg 13 is applied on the lower surface of the intermediate wiring board 21 in which the portion corresponding to the semiconductor element 16 is hollowed out. A prepreg 13 applied to the lower surface is superposed on the upper surface of the intermediate wiring board 21.

次いで、図7(a)に示すように、減圧雰囲気下において、下層配線基板11、中間配線基板21、上層配線基板31を重ね合わせたものを加熱・加圧してプリプレグを一括硬化させることにより、図7(b)に示すように、半導体素子16を内蔵した多層配線基板100が形成されている。   Next, as shown in FIG. 7 (a), under a reduced pressure atmosphere, by heating and pressurizing a laminate of the lower wiring board 11, the intermediate wiring board 21, and the upper wiring board 31 to collectively cure the prepreg, As shown in FIG. 7B, a multilayer wiring board 100 with a built-in semiconductor element 16 is formed.

なお、この出願の発明に関する先行技術文献情報としては、例えば、特許文献1が知られている。
特開2002−270712号公報
As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP 2002-270712 A

しかしながら、上記のような半導体内蔵基板の構成では、下層配線基板、中間配線基板、上層配線基板を重ね合わせて積層するのであるが、積層時には、下層配線基板の下面側と上層配線基板の上面側から平板状のプレス機で加熱・加圧される。そのため、中間配線基板は中央部がくり抜かれているので、積層時にかかる圧力は、半導体が実装されているエリアにはかからず、中間配線基板の残存領域のみが加圧されることになる。その際、残存している中間配線基板の面積内にある、下層配線基板及び上層配線基板の最外層に形成されている配線パターンの形状が小さいためプレス時の圧力は配線パターン部分に集中することになる。従って、この状態で加熱・加圧を行うと下層配線基板及び上層配線基板は変形し、最終的にはインナービアホールの接続不良を引き起こすことになる。   However, in the configuration of the semiconductor-embedded substrate as described above, the lower layer wiring substrate, the intermediate wiring substrate, and the upper layer wiring substrate are stacked and stacked, but at the time of stacking, the lower surface side of the lower layer wiring substrate and the upper surface side of the upper layer wiring substrate are stacked. To be heated and pressurized by a flat plate press. For this reason, since the central portion of the intermediate wiring board is cut out, the pressure applied at the time of stacking does not apply to the area where the semiconductor is mounted, and only the remaining area of the intermediate wiring board is pressed. At that time, since the shape of the wiring pattern formed on the outermost layer of the lower layer wiring board and the upper layer wiring board within the area of the remaining intermediate wiring board is small, the pressure during pressing is concentrated on the wiring pattern part. become. Therefore, if heating and pressurization are performed in this state, the lower layer wiring substrate and the upper layer wiring substrate are deformed and eventually cause a connection failure of the inner via hole.

また、下層配線基板、中間配線基板、上層配線基板を用い、各基板間に未硬化状態のプリプレグを挟んだ構成で半導体素子を内蔵しているものであるが、プリプレグから導出される樹脂の量は限られているので、中間配線基板の1つのくり抜き部分に2つ以上の素子を内蔵することはできない。なぜなら、2つ以上の半導体素子又はチップ部品を中間配線基板の1つのくり抜き部分に内蔵する場合は、素子同士により形成される空間も存在し、樹脂が供給されるべき体積が大きくなるためである。従って、加熱・加圧後に素子周辺には樹脂未充填の空間が残ることになり、この空間部に配線基板や樹脂からのアウトガスが溜まり易い、空間内に結露を生じ易い等の問題があり、長期間の使用によって不良を引き起こす場合がある。   In addition, a semiconductor device is built in a structure in which a lower wiring board, an intermediate wiring board, and an upper wiring board are used and an uncured prepreg is sandwiched between the boards, but the amount of resin derived from the prepreg Therefore, two or more elements cannot be built in one cut-out portion of the intermediate wiring board. This is because when two or more semiconductor elements or chip components are built in one cut-out portion of the intermediate wiring board, there is a space formed by the elements, and the volume to which the resin is to be supplied increases. . Therefore, a space not filled with resin will remain around the element after heating and pressurization, and there is a problem that outgas from the wiring board and resin tends to accumulate in this space, and condensation tends to occur in the space. Long-term use may cause defects.

本発明は上記従来の問題を解決し、接続信頼性及び量産性に優れた電子部品内蔵基板を提供することを目的としている。   An object of the present invention is to solve the above-mentioned conventional problems and to provide an electronic component built-in substrate excellent in connection reliability and mass productivity.

上記課題を解決するために本発明は、配線パターンである電極と、この電極の外周部を囲むように形成した支持パターンと、ビアとを、予め有する多層配線基板と、前記基板上に実装される少なくとも1つ以上の電子部品と、前記基板の上面に積層されるとともに前記電子部品の外形寸法より大きな空間が形成された織布或いは不織布及び熱硬化性樹脂から成る第1の絶縁層と、前記第1の絶縁層の上面に積層される第2の絶縁層と、前記第2の絶縁層の上面に積層される配線層を有し、前記基板と前記第1の絶縁層と前記第2の絶縁層と前記配線層とを加熱圧着して一体化した電子部品内蔵基板であって、前記基板を挟んで前記第1の絶縁層の織布或いは不織布を形成している部分と反対の位置に前記支持パターン形成され、前記支持パターンに重なる前記第1の絶縁層には、必ず前記織布あるいは前記不織布が設けられている電子部品内蔵基板としたものであり、プレスにより加熱圧着して電子部品を基板内に内蔵する際に、かかる圧力を支持パターンで受けることができるので、圧力による基板の変形を防止することが可能となるため、積層時の歩留りを安定化できるという作用を有する。 In order to solve the above-mentioned problems, the present invention is mounted on a multilayer wiring board having in advance an electrode as a wiring pattern, a support pattern formed so as to surround the outer periphery of the electrode, and a via, and the board. At least one or more electronic components, and a first insulating layer made of a woven or non-woven fabric and a thermosetting resin that is laminated on the upper surface of the substrate and has a space larger than the outer dimensions of the electronic components; A second insulating layer stacked on an upper surface of the first insulating layer; and a wiring layer stacked on an upper surface of the second insulating layer, the substrate, the first insulating layer, and the second An electronic component-embedded substrate in which the insulating layer and the wiring layer are integrated by thermocompression bonding, the position being opposite to the portion where the woven or non-woven fabric of the first insulating layer is formed across the substrate the support pattern is formed on said support path The first insulating layer overlapping the over emissions, which was always electronic component-embedded substrate in which the woven fabric or the nonwoven fabric is provided, when a built-in electronic component in the substrate by thermocompression bonding by a press In addition, since the pressure can be received by the support pattern, it is possible to prevent the deformation of the substrate due to the pressure, so that the yield at the time of stacking can be stabilized.

以上のように本発明によれば、予め配線基板に支持パターンを設けておくことで、プリプレグを使用した電子部品内蔵基板及び電子部品内蔵モジュールを容易に作製することが可能となり、量産性に優れ、低コスト化が可能な電子部品内蔵基板及び電子部品内蔵モジュールを作製することが可能となる。   As described above, according to the present invention, it is possible to easily produce an electronic component built-in substrate and an electronic component built-in module using a prepreg by providing a support pattern on the wiring board in advance, and is excellent in mass productivity. Thus, it is possible to manufacture an electronic component built-in substrate and an electronic component built-in module that can be reduced in cost.

(実施の形態1)
以下、本発明の実施の形態1について、本発明の特に請求項1,3〜15に記載の発明について図面を参照しながら説明する。
(Embodiment 1)
Hereinafter, the first embodiment of the present invention will be described with reference to the drawings.

図1は、本発明の実施の形態1による電子部品内蔵基板の製造工程断面図である。   FIG. 1 is a cross-sectional view of a manufacturing process of an electronic component built-in substrate according to Embodiment 1 of the present invention.

図1(a)において、配線基板101は、表面の電極102と、内層配線パターン104と、インナービアホール103と、裏面に配線パターンである電極105と、この電極105の外周部を囲むように支持パターン107を形成した多層配線基板である。   In FIG. 1A, the wiring substrate 101 is supported so as to surround the electrode 102 on the front surface, the inner layer wiring pattern 104, the inner via hole 103, the electrode 105 that is the wiring pattern on the back surface, and the outer periphery of the electrode 105. This is a multilayer wiring board on which a pattern 107 is formed.

電極102、105や配線パターン104は、電気導電性を有する物質から成り、例えば、Cu箔や導電性樹脂組成物から成る。本発明においてはCu箔を用いている。そして、支持パターン107についても電極105と同一材料で形成し、積層時の圧力による基板の変性を防止するために、支持パターン107の高さは、電極105と同一の高さに形成している。   The electrodes 102 and 105 and the wiring pattern 104 are made of a material having electrical conductivity, for example, a Cu foil or a conductive resin composition. In the present invention, Cu foil is used. The support pattern 107 is also formed of the same material as the electrode 105, and the height of the support pattern 107 is the same as that of the electrode 105 in order to prevent the substrate from being denatured due to the pressure during lamination. .

本発明では、支持パターン107についてもCu箔を用いており、電極105と支持パターン107はフォトリソグラフィーにより同時に形成している。   In the present invention, Cu foil is also used for the support pattern 107, and the electrode 105 and the support pattern 107 are simultaneously formed by photolithography.

また、インナービアホール103は、例えば、金属粒子と熱硬化性樹脂とを混合した導電性樹脂組成物などの熱硬化性の導電性物質から成る。金属粒子としては、Au、AgまたはCuなどを用いることができる。Au、AgまたはCuは導電性が高いために好ましく、Cuは導電性が高くマイグレーションも少なく、また、低コストであるため特に好ましい。熱硬化性樹脂としては、例えば、エポキシ樹脂、フェノール樹脂またはシアネート樹脂を用いることができる。エポキシ樹脂は耐熱性が高いために特に好ましい。   The inner via hole 103 is made of a thermosetting conductive material such as a conductive resin composition in which metal particles and a thermosetting resin are mixed. As the metal particles, Au, Ag, Cu, or the like can be used. Au, Ag, or Cu is preferable because of its high conductivity, and Cu is particularly preferable because of its high conductivity, low migration, and low cost. As the thermosetting resin, for example, an epoxy resin, a phenol resin, or a cyanate resin can be used. Epoxy resins are particularly preferred because of their high heat resistance.

次に、図1(b)に示すように、配線基板101上の所定の位置に、はんだ109を用いて電子部品108a、108bを実装する。電子部品108a、108bは、例えば、トランジスタ、IC、LSIなどの半導体素子である能動部品、および抵抗、コンデンサ、インダクタ、振動子及びフィルタなどの面実装型部品である受動部品から成る。   Next, as shown in FIG. 1B, electronic components 108 a and 108 b are mounted using solder 109 at predetermined positions on the wiring board 101. The electronic components 108a and 108b include, for example, active components that are semiconductor elements such as transistors, ICs, and LSIs, and passive components that are surface-mounted components such as resistors, capacitors, inductors, vibrators, and filters.

はんだ109にはPb−Sn系の共晶はんだやPbフリーはんだ(例えばSn−Ag−Cu系、Au−Sn系またはSn−Zn系)を用いることができるが、何れの場合も融点が230℃以下であるため、非耐熱性部品であっても使用することが可能である。   Pb—Sn eutectic solder or Pb-free solder (for example, Sn—Ag—Cu, Au—Sn, or Sn—Zn) can be used as the solder 109, but in any case, the melting point is 230 ° C. Since it is the following, even a non-heat-resistant component can be used.

また、電子部品108a、108bを実装するためのはんだ109と電子部品内蔵基板130をマザー基板(図示せず)へ実装するためのはんだは同一材料であっても、異なる材料を用いても構わない。しかしながら、近年の環境問題への配慮を考えるとPbフリーはんだを用いる方が望ましい。なお、電子部品108a、108bを実装後、フラックス洗浄を行っておくことは電子部品内蔵基板130の信頼性を満足する上で最も重要な項目の1つである。   Also, the solder 109 for mounting the electronic components 108a and 108b and the solder for mounting the electronic component built-in substrate 130 on the mother substrate (not shown) may be the same material or different materials. . However, in consideration of recent environmental problems, it is preferable to use Pb-free solder. Note that flux cleaning after mounting the electronic components 108 a and 108 b is one of the most important items in satisfying the reliability of the electronic component built-in substrate 130.

次に、図1(c)に示すように、電子部品108a、108bを実装済みの配線基板101の電子部品108a、108bを実装している面に、第1の絶縁層120、第2の絶縁層122、配線層123を所望の位置に重ね合わせる。ここで、均一な圧力で積層を可能にするために、配線層123の面積は、支持パターン107の同一形状以上の面積を有している。   Next, as shown in FIG. 1C, the first insulating layer 120 and the second insulation are formed on the surface of the wiring board 101 on which the electronic components 108a and 108b have been mounted. The layer 122 and the wiring layer 123 are overlaid at desired positions. Here, in order to enable lamination with a uniform pressure, the area of the wiring layer 123 has an area equal to or larger than the same shape of the support pattern 107.

第1の絶縁層120及び第2の絶縁層122は、織布或いは不織布に未硬化状態の熱硬化性樹脂を含浸させたプリプレグで構成されている。プリプレグとしては、ガラスクロスに熱硬化性のエポキシ樹脂を含浸させたガラスエポキシプリプレグ、ガラスクロスに熱硬化性のビスマレイドトリアミド樹脂を含浸させたBTレジンプリプレグ、アラミド不織布に熱硬化性のエポキシ樹脂を含浸させたアラミドプリプレグ等を使用することが可能であるが、織布或いは不織布に熱硬化性樹脂を含浸させた構造であれば、様々な材料を使用することが可能である。なお、第1の絶縁層120と第2の絶縁層122は、基板のそりや変形を防止するために、同一組成の材料であることが望ましい。   The 1st insulating layer 120 and the 2nd insulating layer 122 are comprised with the prepreg which impregnated the thermosetting resin of the uncured state to the woven fabric or the nonwoven fabric. As the prepreg, a glass epoxy prepreg in which a glass cloth is impregnated with a thermosetting epoxy resin, a BT resin prepreg in which a glass cloth is impregnated with a thermosetting bismaleidotriamide resin, and a thermosetting epoxy resin in an aramid nonwoven fabric It is possible to use an aramid prepreg impregnated with, but various materials can be used as long as the structure is obtained by impregnating a thermosetting resin into a woven fabric or a non-woven fabric. Note that the first insulating layer 120 and the second insulating layer 122 are preferably made of materials having the same composition in order to prevent warping or deformation of the substrate.

また、第1の絶縁層120には、電子部品108a、108bと接触しないように空間121が形成されている。この空間121は、図1(c)のような複数個の電子部品108a、108bを実装している場合でも、実装エリアをすべて囲むように1つの空間としている。こうすることで、空間121の加工を単純化することができるため、製造工程の簡略化が可能となる。   A space 121 is formed in the first insulating layer 120 so as not to contact the electronic components 108a and 108b. Even when a plurality of electronic components 108a and 108b as shown in FIG. 1C are mounted, the space 121 is a single space surrounding the entire mounting area. By doing so, the processing of the space 121 can be simplified, so that the manufacturing process can be simplified.

また、第2の絶縁層122が電子部品108a、108bに接触することによって電子部品108a、108bに圧力がかからないように、第1の絶縁層120は、電子部品108a、108bの高さより厚く形成する必要がある。   In addition, the first insulating layer 120 is formed to be thicker than the electronic components 108a and 108b so that the electronic components 108a and 108b are not pressurized when the second insulating layer 122 contacts the electronic components 108a and 108b. There is a need.

一方、第1の絶縁層120を厚くするために特別に厚い材料を作ることは、特注品であるが故の高コスト化を避けることが難しく、また量産性には不向きである。従って、第1の絶縁層120には、通常配線基板を作製する際に使用している一般的な厚み(例えば100μm)のプリプレグを複数枚使用することで、所望の厚みを確保している。   On the other hand, it is difficult to avoid an increase in cost because it is a custom-made product to make the first insulating layer 120 thick, and it is not suitable for mass production. Therefore, a desired thickness is ensured for the first insulating layer 120 by using a plurality of prepregs having a general thickness (for example, 100 μm) that are normally used when manufacturing a wiring board.

また、プリプレグは織布或いは不織布と未硬化状態の熱硬化性樹脂の混合シートであるが、このプリプレグは加熱・加圧することにより、プリプレグから軟化した熱硬化性樹脂が流れ出し、加熱・加圧終了後には初期の厚みより必ず薄くなる。このため、この厚みの減少分を予め考慮して、複数枚使用しているプリプレグ内の織布或いは不織布の総厚を基準にして設計すれば、積層後でも第2の絶縁層122が電子部品108a、108bに接触することを未然に防止することが可能である。そして、更には、プリプレグを複数枚使用することにより、加熱・加圧時にプリプレグから流出する熱硬化性樹脂124の量を十分に確保することができるため、複数の電子部品108a、108bが存在する場合にできる空間121内の隙間を、熱硬化性樹脂124で充填させることが可能となる。   The prepreg is a mixed sheet of woven fabric or non-woven fabric and an uncured thermosetting resin. When this prepreg is heated and pressurized, the softened thermosetting resin flows out of the prepreg, and heating and pressurization are completed. Later, it is always thinner than the initial thickness. For this reason, if the thickness reduction is taken into consideration in advance and the design is made based on the total thickness of the woven fabric or nonwoven fabric in the prepreg used in plural, the second insulating layer 122 can be made into an electronic component even after lamination. It is possible to prevent contact with 108a and 108b. Further, by using a plurality of prepregs, a sufficient amount of the thermosetting resin 124 that flows out from the prepreg during heating and pressurization can be secured, and thus there are a plurality of electronic components 108a and 108b. It is possible to fill the gaps in the space 121 that can be formed with the thermosetting resin 124.

次に、図1(d)に示すように、熱プレスにより加熱・加圧して空間121内に熱硬化性樹脂124を充填させ、電子部品108a、108bを基板内に内蔵する。この積層時において、第1の絶縁層120に空間121が形成されているため、積層時の圧力は第1の絶縁層の残留プリプレグの形状に対応した圧力が、配線基板101及び第2の絶縁層122、配線パターン123にかかることになる。   Next, as shown in FIG. 1D, the space 121 is filled with the thermosetting resin 124 by heating and pressurizing by hot pressing, and the electronic components 108a and 108b are built in the substrate. Since the space 121 is formed in the first insulating layer 120 at the time of lamination, the pressure at the time of lamination corresponds to the shape of the remaining prepreg of the first insulating layer, and the wiring substrate 101 and the second insulation are used. The layer 122 and the wiring pattern 123 are applied.

本発明では、配線基板101に支持パターン107が存在することにより、積層時の圧力を支持パターン107で受け止めることが可能となるので、配線基板101を変形させることなく、積層工程を行うことができるのである。この時、支持パターン107は、空間121を空けた第1の絶縁層120の残っている織布或いは不織布の幅に対して50%以上の形状を有していることが重要である。   In the present invention, since the support pattern 107 is present on the wiring substrate 101, it is possible to receive the pressure at the time of stacking with the support pattern 107, so that the stacking process can be performed without deforming the wiring substrate 101. It is. At this time, it is important that the support pattern 107 has a shape of 50% or more with respect to the width of the woven or non-woven fabric in which the first insulating layer 120 leaving the space 121 remains.

支持パターン107の幅が織布或いは不織布の幅に対して50%より小さくなると、支持パターン107が存在していても、圧力を平面的に受け止めることが不十分となるので、積層工程により配線基板101の変形を生じてしまうおそれがある。   If the width of the support pattern 107 is less than 50% of the width of the woven or non-woven fabric, even if the support pattern 107 is present, it is insufficient to receive the pressure in a plane. 101 may be deformed.

また、図2に示すように、支持パターン107は独立したパターンの集合体であってもよい。支持パターン107を独立パターンの集合体とすることで、配線基板101の表裏面において残銅率の差を小さくし、それによって配線基板101の反りを防止するとともに、支持パターン107としても有効な構造とすることが可能となる。また、支持パターン107の独立パターンの間隔が広すぎると支持パターン107としての効果が発揮できなくなるため、パターンの間隔を200μm以下に設定することも重要である。   Further, as shown in FIG. 2, the support pattern 107 may be an aggregate of independent patterns. By forming the support pattern 107 as an aggregate of independent patterns, the difference in the remaining copper ratio on the front and back surfaces of the wiring board 101 is reduced, thereby preventing warping of the wiring board 101 and effective as the support pattern 107. It becomes possible. In addition, if the distance between the independent patterns of the support pattern 107 is too wide, the effect as the support pattern 107 cannot be exhibited. Therefore, it is important to set the pattern distance to 200 μm or less.

そして、積層完了後、図3に示すように、切断して個別の電子部品内蔵基板130とする。   Then, after completion of the lamination, as shown in FIG.

以上に示すように、本実施の形態1によれば、プレスにより加熱圧着して電子部品を基板内に内蔵する際に、かかる圧力を支持パターンで受けることができるので、圧力による基板の変形を防止することが可能となるため、量産性に優れた電子部品内蔵基板を安定して作製することが可能となる。   As described above, according to the first embodiment, the pressure can be received by the support pattern when the electronic component is built into the substrate by thermocompression bonding with a press, so that the deformation of the substrate due to the pressure is prevented. Therefore, it is possible to stably manufacture a substrate with built-in electronic components that is excellent in mass productivity.

(実施の形態2)
以下、本発明の実施の形態2について、本発明の特に請求項2〜15に記載の発明について図面を参照しながら説明する。
(Embodiment 2)
The second embodiment of the present invention will be described below with reference to the drawings.

図4は、本発明の実施の形態2による電子部品内蔵モジュールの製造工程断面図、図5は、本発明の実施の形態2による電子部品内蔵モジュールの断面図を示している。なお、実施の形態1と同一の構造については、同一番号を付与して説明を省略する。   FIG. 4 is a sectional view of a manufacturing process of an electronic component built-in module according to the second embodiment of the present invention, and FIG. 5 is a sectional view of the electronic component built-in module according to the second embodiment of the present invention. In addition, about the same structure as Embodiment 1, the same number is provided and description is abbreviate | omitted.

実施の形態1と同様に、図1(a)〜(c)に示すように、電子部品108a、108bを実装した配線基板101上に、空間121を形成した第1の絶縁層120と第2の絶縁層122と配線層123を所望の位置に重ね合わせ、加熱・加圧して一体化させる。この時、支持パターン107の存在により配線基板101が変形することなく一体形成が可能となる。   As in the first embodiment, as shown in FIGS. 1A to 1C, the first insulating layer 120 and the second insulating layer 120 each having a space 121 formed on the wiring board 101 on which the electronic components 108a and 108b are mounted. The insulating layer 122 and the wiring layer 123 are overlapped at a desired position and integrated by heating and pressing. At this time, the wiring substrate 101 can be integrally formed without deformation due to the presence of the support pattern 107.

次に、図4(a)に示すように、上下面を貫通するようにスルーホール125を形成する。   Next, as shown in FIG. 4A, a through hole 125 is formed so as to penetrate the upper and lower surfaces.

次に、図4(b)に示すように、めっき126によりスルーホール125を介して上下面の電気的導通を図り、配線層123を所望の配線パターンへ加工する。この時、支持パターン107が配線パターンの一部として使用されても、そうでなくても構わない。そもそも支持パターン107の目的は、積層時に配線基板101にかかる圧力を受け止めるために存在させているのであるが、積層後の基板に対しては、その後は支持パターン107が配線パターンとして使用されてもなんら問題を生じるものではない。   Next, as shown in FIG. 4B, the upper and lower surfaces are electrically connected through the through holes 125 by plating 126, and the wiring layer 123 is processed into a desired wiring pattern. At this time, the support pattern 107 may or may not be used as a part of the wiring pattern. In the first place, the purpose of the support pattern 107 is to receive the pressure applied to the wiring substrate 101 at the time of stacking. However, even if the support pattern 107 is used as a wiring pattern thereafter for the substrate after stacking. It doesn't cause any problems.

次に、図4(c)に示すように、配線基板101の裏面電極105上に電子部品128a、128bを実装する。なお、電子部品128a、128bの実装位置に関しては、配線基板101の裏面電極105上であっても、配線層123から新たに形成した配線パターン上であっても構わない。どちらの面にでも実装可能なように、スルーホール125を介して上下面を導通させているのである。   Next, as shown in FIG. 4C, electronic components 128 a and 128 b are mounted on the back electrode 105 of the wiring substrate 101. The mounting positions of the electronic components 128a and 128b may be on the back electrode 105 of the wiring board 101 or on a wiring pattern newly formed from the wiring layer 123. The upper and lower surfaces are made conductive through the through hole 125 so that they can be mounted on either surface.

また、実装に用いるはんだ129は、内蔵している電子部品108a、108bと同様に、Pb−Sn系の共晶はんだやPbフリーはんだ(例えばSn−Ag−Cu系、Au−Sn系またはSn−Zn系)を用いることができるが、何れの場合も融点が230℃以下であるため、非耐熱性部品であっても使用することが可能である。しかしながら、近年の環境問題への配慮を考えるとPbフリーはんだを用いる方が望ましい。   Also, the solder 129 used for mounting is a Pb—Sn based eutectic solder or Pb free solder (for example, Sn—Ag—Cu based, Au—Sn based, or Sn—), similar to the built-in electronic components 108a and 108b. (Zn-based) can be used, but in any case, since the melting point is 230 ° C. or less, even non-heat-resistant parts can be used. However, in consideration of recent environmental problems, it is preferable to use Pb-free solder.

そして、図5に示すように、実装完了後切断して、電子部品内蔵モジュール131を形成する。   Then, as shown in FIG. 5, the electronic component built-in module 131 is formed by cutting after completion of the mounting.

以上のように、本実施の形態によれば、プレスにより加熱圧着して電子部品を基板内に内蔵する際に、かかる圧力を支持パターンで受け止めることで圧力による基板の変形を防止するだけでなく、支持パターンを配線パターンとして使用し、スルーホール接続を行うことができるようになるので、電子部品内蔵基板として表裏面に部品実装や、別基板への実装が可能となる。   As described above, according to the present embodiment, when the electronic component is built in the substrate by thermocompression bonding using a press, not only the pressure is received by the support pattern but also the deformation of the substrate due to the pressure is prevented. Since the support pattern can be used as a wiring pattern and through-hole connection can be performed, it is possible to mount components on the front and back surfaces of the electronic component-embedded substrate or to be mounted on another substrate.

本発明は、熱ストレスや機械的ストレスを受け難く、かつ低コスト化が可能な、電子部品が埋設された電子部品内蔵基板とその製造方法及び電子部品内蔵基板を用いた電子部品内蔵モジュールに有用である。   INDUSTRIAL APPLICABILITY The present invention is useful for an electronic component built-in substrate in which an electronic component is embedded, a manufacturing method thereof, and an electronic component built-in module using the electronic component built-in substrate, which are less susceptible to thermal stress and mechanical stress and can be reduced in cost. It is.

本発明の実施の形態1における電子部品内蔵基板の製造工程断面図Manufacturing process sectional drawing of the electronic component built-in substrate in Embodiment 1 of this invention 本発明の実施の形態1における電子部品内蔵基板の断面図Sectional drawing of the electronic component built-in substrate in Embodiment 1 of this invention 本発明の実施の形態1における電子部品内蔵基板の断面図Sectional drawing of the electronic component built-in substrate in Embodiment 1 of this invention 本発明の実施の形態2における電子部品内蔵基板の製造工程断面図Manufacturing process sectional drawing of the electronic component built-in substrate in Embodiment 2 of this invention 本発明の実施の形態2における電子部品内蔵モジュールの断面図Sectional drawing of the electronic component built-in module in Embodiment 2 of this invention 従来の電子部品内蔵基板の製造工程断面図Cross-sectional view of the manufacturing process of a conventional substrate with built-in electronic components 従来の電子部品内蔵基板の製造工程断面図Cross-sectional view of the manufacturing process of a conventional substrate with built-in electronic components

101 配線基板
102 電極
103 インナービアホール
104 内層配線パターン
105 電極
107 支持パターン
108a 電子部品
108b 電子部品
109 はんだ
120 第1の絶縁層
121 空間
122 第2の絶縁層
123 配線層
124 熱硬化性樹脂
125 スルーホール
126 めっき
128a 電子部品
128b 電子部品
129 はんだ
DESCRIPTION OF SYMBOLS 101 Wiring board 102 Electrode 103 Inner via hole 104 Inner layer wiring pattern 105 Electrode 107 Support pattern 108a Electronic component 108b Electronic component 109 Solder 120 First insulating layer 121 Space 122 Second insulating layer 123 Wiring layer 124 Thermosetting resin 125 Through hole 126 Plating 128a Electronic component 128b Electronic component 129 Solder

Claims (13)

配線パターンである電極と、この電極の外周部を囲むように形成した支持パターンと、ビアとを、予め有する多層配線基板と、前記基板上に実装される少なくとも1つ以上の電子部品と、前記基板の上面に積層されるとともに前記電子部品の外形寸法より大きな空間が形成された織布或いは不織布及び熱硬化性樹脂から成る第1の絶縁層と、前記第1の絶縁層の上面に積層される第2の絶縁層と、前記第2の絶縁層の上面に積層される配線層を有し、前記基板と前記第1の絶縁層と前記第2の絶縁層と前記配線層とを加熱圧着して一体化した電子部品内蔵基板であって、
前記基板を挟んで前記第1の絶縁層の織布或いは不織布を形成している部分と反対の位置に前記支持パターンが形成され、
前記支持パターンに重なる前記第1の絶縁層には、必ず前記織布あるいは前記不織布が設けられている電子部品内蔵基板。
A multilayer wiring board having in advance an electrode which is a wiring pattern, a support pattern formed so as to surround the outer periphery of the electrode, and a via, at least one electronic component mounted on the board, and A first insulating layer made of a woven or non-woven fabric and a thermosetting resin, which is laminated on the upper surface of the substrate and has a space larger than the outer dimensions of the electronic component, and laminated on the upper surface of the first insulating layer. A second insulating layer and a wiring layer laminated on the upper surface of the second insulating layer, and the substrate, the first insulating layer, the second insulating layer, and the wiring layer are thermocompression bonded. Integrated electronic component built-in board,
The support pattern is formed at a position opposite to the portion where the woven or non-woven fabric of the first insulating layer is formed across the substrate,
The electronic component built-in substrate in which the woven fabric or the non-woven fabric is necessarily provided on the first insulating layer overlapping the support pattern.
支持パターンと配線層とがスルーホールを介して電気的に接続されている請求項1に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the support pattern and the wiring layer are electrically connected through a through hole. 支持パターンが基板の配線パターンと同一の材料で形成されている請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the support pattern is formed of the same material as the wiring pattern of the substrate. 支持パターンが基板の配線パターンと同一の高さである請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the support pattern has the same height as the wiring pattern of the substrate. 支持パターンの幅が前記支持パターンの位置に対応する第1の絶縁層の織布或いは不織布の幅の50%以上を有する請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the width of the support pattern has 50% or more of the width of the woven or non-woven fabric of the first insulating layer corresponding to the position of the support pattern. 積層完了後に、前記支持パターンに重なる位置に設けられた第1の絶縁層の前記織布あるいは前記不織布ごと、個別に切断されてなる請求項1または2に記載の電子部品内蔵基板。 3. The electronic component built-in substrate according to claim 1, wherein the woven fabric or the non-woven fabric of the first insulating layer provided at a position overlapping the support pattern is individually cut after completion of the lamination. 支持パターンが複数の独立したパターンの集合体である請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the support pattern is an assembly of a plurality of independent patterns. 支持パターンの間隔が200μm以下である請求項7に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 7, wherein the interval between the support patterns is 200 μm or less. 第2の絶縁層が第1の絶縁層と同一組成の材料で構成される請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the second insulating layer is made of a material having the same composition as that of the first insulating layer. 第1の絶縁層は複数枚のシート状絶縁層から成る請求項1または2に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein the first insulating layer includes a plurality of sheet-like insulating layers. 第1の絶縁層内の織布或いは不織布の総厚が、電子部品の高さ以上である請求項1,2,10のいずれか一つに記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1, wherein a total thickness of the woven fabric or the nonwoven fabric in the first insulating layer is equal to or greater than a height of the electronic component. 配線層は、基板と第1の絶縁層と第2の絶縁層と前記配線層を加熱圧着して一体化する際には、支持パターンと同一形状以上の面積を有している請求項1または2に記載の電子部品内蔵基板。 The wiring layer has an area equal to or larger than that of the support pattern when the substrate, the first insulating layer, the second insulating layer, and the wiring layer are integrated by thermocompression bonding. 2. The electronic component built-in substrate according to 2. 多層配線基板と、前記基板上に実装される少なくとも1つ以上の電子部品と、前記基板の上面に積層されるとともに前記電子部品の外形寸法より大きな空間が形成された織布或いは不織布及び熱硬化性樹脂から成る第1の絶縁層と、前記第1の絶縁層の上面に積層される第2の絶縁層と、前記第2の絶縁層の上面に積層される配線層を有し、前記基板と前記第1の絶縁層と前記第2の絶縁層と前記配線層を加熱圧着して一体化する電子部品内蔵基板の製造方法であって、
配線パターンである電極と、この電極の外周部を囲むように形成した支持パターンと、ビアとを、予め有する多層配線基板を用意する工程と、
前記基板の、前記基板を挟んで前記第1の絶縁層の織布或いは不織布が形成されている部分と反対の位置に支持パターンを形成する支持パターン形成工程と、
この支持パターン形成工程の後に、加熱加圧することにより前記第1の絶縁層の織布或いは不織布から熱硬化性樹脂を押し出し前記電子部品を前記熱硬化性樹脂で完全に覆うとともに、前記第1の絶縁層の空間をすべて前記熱硬化性樹脂で充填させ、前記支持パターンに重なる前記第1の絶縁層には、必ず前記織布あるいは前記不織布が設けられる熱硬化性樹脂充填工程と、
を有する電子部品内蔵基板の製造方法。
A multilayer wiring board, at least one or more electronic components mounted on the substrate, a woven or non-woven fabric laminated on the upper surface of the substrate and formed with a space larger than the outer dimensions of the electronic components, and thermosetting A first insulating layer made of a conductive resin, a second insulating layer stacked on the top surface of the first insulating layer, and a wiring layer stacked on the top surface of the second insulating layer, And a method of manufacturing an electronic component-embedded substrate in which the first insulating layer, the second insulating layer, and the wiring layer are integrated by thermocompression bonding,
Preparing a multilayer wiring board having in advance an electrode that is a wiring pattern, a support pattern formed so as to surround the outer periphery of the electrode, and a via;
A support pattern forming step of forming a support pattern at a position opposite to the portion of the substrate on which the woven or nonwoven fabric of the first insulating layer is formed across the substrate;
After this support pattern forming step, by applying heat and pressure, the thermosetting resin is extruded from the woven or non-woven fabric of the first insulating layer, and the electronic component is completely covered with the thermosetting resin, and the first all the space of the insulating layer is filled with the thermosetting resin, wherein the first insulating layer overlying the support pattern and the thermosetting resin filling process that is provided is always the woven or the nonwoven fabric,
A method of manufacturing an electronic component built-in substrate having
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