JP2003209357A - Method for manufacturing multilayer board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer board having stronger electric resistance than that of a prior art. <P>SOLUTION: The method for manufacturing the multilayer board comprises the steps of selecting a laminating board 2 having a smaller shrinkage amount than that of a manufacturing board 5, positioning the board 2 on wirings W1 of the board 5, and integrally forming the board 5 positioned at the wirings W1 via prepregs 25a, 26a for mechanically integrating the boards 5 with the board 2. Thus, if the board 5 is shrunk while the board 2 remains positioned on the wirings W1 in association with the integration of the board 5 with the board 2, the board 2 is shrunk in smaller shrinkage amount than that of the board 5, and hence the board 5 can be electrically connected to the board 2 to each other in a state in which the positional deviation of the wirings W1 falls within a range of the shrinkage amount of the board 2. Thus, in the state in which the positional deviation of the board 2 to the board 5 is fallen in a minimum limit, the electric connection can be surely performed. Hence, the electric resistance can be strengthened as compared with prior art. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer substrate, and is suitable for application to, for example, a method for manufacturing a multilayer substrate in which two substrates are laminated to manufacture a multilayer substrate.

[0002]

2. Description of the Related Art Conventionally, in a method of manufacturing a multi-layer substrate, a stacking substrate having substantially the same size and the same material as that of the manufacturing substrate is stacked on the manufacturing substrate of the manufacturing size, A multilayer substrate is manufactured by penetrating through holes substantially perpendicular to one surface of a stacking substrate and connecting layers.

[0003]

By the way, in the method for manufacturing a multilayer substrate, although the manufacturing substrate and the laminating substrate of the same size and the same material are used, the wiring for one surface of the manufacturing substrate and the laminating substrate is used. Since the occupation ratios are different, the shrinkage amount in the organic material of the manufacturing substrate and the shrinkage amount in the organic material of the laminating substrate are significantly different due to the heat treatment or the cooling treatment in the manufacturing process.

Therefore, in the method of manufacturing a multilayer substrate, even if a through hole is formed so as to penetrate substantially perpendicularly to one surface of the manufacturing substrate and the laminating substrate, the through hole is originally formed in the manufacturing substrate and the laminating substrate. Since the formation position of the through hole to be formed is largely displaced due to the difference in the contraction amount, there is a problem that electrical connection cannot be sufficiently performed and electrical resistance is weak.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a multi-layer substrate manufacturing method capable of manufacturing a multi-layer substrate having high electrical resistance by a simpler method than conventional methods. .

[0006]

In order to solve such a problem, in the present invention, a laminating substrate having a shrinkage amount smaller than that of a predetermined manufacturing substrate is selected, and is laminated at a predetermined position of the manufacturing substrate. The substrate is positioned, and the manufacturing substrate and the laminating substrate that are positioned at a predetermined position through the connection intermediary portion that connects the manufacturing substrate and the laminating substrate are cured to be integrally formed,
When the manufacturing substrate, the connection mediation part and the laminating substrate are electrically connected to each other, and the curing causes the laminating substrate to be contracted while the laminating substrate is positioned at a predetermined position, By shrinking the laminating substrate with a smaller amount of shrinkage than the manufacturing substrate, the positional deviation of the laminating substrate with respect to the predetermined position is kept within the range of the amount of shrinkage.

Therefore, in the present invention, even if the manufacturing substrate and the laminating substrate shrink, the positional deviation of the laminating substrate with respect to the predetermined position of the manufacturing substrate falls within the range of the shrinkage amount of the laminating substrate. Therefore, it is possible to reliably perform the electrical connection in a state in which the positional deviation of the stacking substrate with respect to the manufacturing substrate is minimized.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

In the present invention, a method for manufacturing a multilayer substrate 51 to 53 (FIG. 5), which is a finished product, will be described with reference to FIGS.

As a first step (upper part of FIG. 1 (A)), a multi-layer substrate manufacturing apparatus (not shown) uses a glass epoxy material double-sided copper clad plate 1a having a work sheet size (area) for manufacturing a substrate. After being cut into three substrates having an area of ⅓ or less, one surface 2A, 3
Etching resist treatment and wet etching treatment are sequentially applied to A and 4A to form wirings wir1, wir2, and wir3 having one wiring pattern, whereby the laminating substrates 2, 3, and 4 are manufactured.

On the other hand, the multi-layered board manufacturing apparatus has a double-sided copper clad board 1
Wiring wir1 when the laminating substrates 2, 3 and 4 are produced from the double-sided copper-clad plate 1a on one surface 5A of the double-sided copper-clad plate 1b (lower part of FIG. 1 (A)) of the same size and the same material as a wir2 and
Wiring W is performed by applying the same processing as above to the position corresponding to wir3.
1. Manufacturing substrate 5 by forming 1, W2 and W3
To make.

As a result, the multi-layer substrate manufacturing apparatus selects the laminating substrates 2, 3 and 4 having an area which is approximately ⅓ or less of the area of the one surface 5A of the manufacturing substrate 5, and the wiring W1 of the manufacturing substrate 5 is selected. , W2 and W3 can be formed in a state of being isolated from each other for a predetermined period.

The reason why the laminating substrates 2, 3 and 4 are selected to have an area that is approximately 1/3 or less of the area of the one surface 5A of the manufacturing substrate 5 will be described later.

Further, the multi-layer substrate manufacturing apparatus includes a manufacturing substrate 5
By performing the terminal plating process on the wirings W1, W2, and W3, the additional process such as the masking process performed after the stacking substrates 2, 3 and 4 are stacked on the manufacturing substrate 5 can be omitted. Has been done.

As a second step (upper part of FIG. 1B), the multilayer substrate manufacturing apparatus is provided with a bare chip 11 composed of a semiconductor memory or the like.
The stat bump 12a formed at a predetermined position on the circuit formation surface of a and the wiring wir1 on the inner peripheral side formed on the one surface 2A of the laminating substrate 2 are joined via an anisotropic conductive film 13a (so-called flip-chip mounting). To do.

Similarly, the multilayer substrate manufacturing apparatus is provided with the bare chip 1
The stat bumps 12b and 12c formed at predetermined positions on the circuit forming surfaces of 1b and 11c, and the inner peripheral wirings wir2 and wir3 formed on one surface 3A and 4A of the laminating substrates 3 and 4 are anisotropic conductive films 13b. And 13c for flip chip mounting.

As a third step (FIG. 2C), the multi-layer substrate manufacturing apparatus inserts a glass epoxy material having substantially the same area as one surface 2A of the laminating substrate 2 onto the wiring W1 of the manufacturing substrate 5. The prepreg 25a and the cover prepreg 26a are sequentially laminated, and the lamination substrate 2 on which the bare chip 11a is mounted is laminated with the wiring wir1 facing the wiring W1 and being positioned.

Similarly, the multi-layer substrate manufacturing apparatus uses the manufacturing substrate 5
One side 3 of the stacking substrates 3 and 4 on the wirings W2 and W3 of
Insertion prepregs 25b and 25c and cover lid prepreg 26 made of glass epoxy material having substantially the same area as A and 4A
b and 26c are sequentially stacked, and the wirings W2 and W
The wiring boards 3 and 4 on which the bare chips 11b and 11c are mounted are stacked with the wirings wir2 and wir3 facing each other and being positioned on the wiring 3.

Here, the interposing prepregs 25a, 25b and 25c are for selecting a predetermined thickness between the manufacturing substrate 5 and the laminating substrates 2, 3 and 4, and have a cover lid. What is the prepreg 26a, 26b and 26c?
It is for covering the bare chips 11a, 11b and 11c.

In this case, the multi-layer substrate manufacturing apparatus is designed so that the thickness of the interposing prepreg 25a, 25b or 25c can be changed appropriately, whereby the laminating substrate 2, 3 or the manufacturing substrate 5 can be changed. The height when 4 is stacked can be made substantially equal to the height required when mounted on a motherboard substrate used as a part of the final product.

Therefore, the multi-layer substrate manufacturing apparatus is provided with the manufacturing substrate 5
The thickness between the stacking substrate 2 and the laminating substrate 2, 3 or 4 can be flexibly dealt with when the height of the mounting device is limited.

In the multi-layer substrate manufacturing apparatus, a part of the cover lid prepreg 26a, 26b or 26c is bare chip 11a,
By removing depending on the volume of 11b or 11c,
The bare chip cover spaces v1, v2, and v3 can be formed.

As a result, the multi-layer substrate manufacturing apparatus uses the bare chip cover spaces v1, v2 and v3 to form the bare chip 11
By accommodating a, 11b, and 11c, the laminating boards 2, 3 and 4 on which the bare chips 11a, 11b and 11c are mounted can be laminated on the cover lid prepregs 26a, 26b and 26c without interfering with each other. Together with the cover lid prepregs 26a and 26b in the laminated state.
Bare chips 11a, 11b when heat curing of 26 and 26c
And 11c can be quickly diffused to the surroundings.

Therefore, in the fourth stage (FIG. 2D), the multi-layer substrate manufacturing apparatus heats the interposing prepregs 25a to 25c and the cover lid prepregs 26a to 26c (FIG. 2C) to a predetermined temperature in a vacuum atmosphere. Then, the insertion prepreg 2
5a to 25c and the cover lid prepregs 26a to 26c cover the periphery of the bare chips 11a to 11c by diffusion at the time of thermosetting, and the laminating substrates 2 to 4 and the manufacturing substrate 5
And the interlayer portions 31, 32, which are integrally formed while maintaining airtightness,
33.

After that, when the multi-layer substrate manufacturing apparatus is returned to room temperature and normal pressure, the thermosetting intercalating prepregs 25a to 25c.
On the contrary to the cover lid prepregs 26a to 26c, the laminating substrates 2, 3, 4 and the manufacturing substrate 5 are the laminating substrate 2,
Since the organic members of the substrates 3 and 4 and the manufacturing substrate 5 are hardened according to their characteristics, they eventually shrink.

In this case, for example, as shown in FIG. 3, since the manufacturing substrate 5 and the laminating substrates 2, 3 and 4 are made of the same material, they have the same shrinkage, but the laminating substrates 2, 3 and 4 is smaller than the other surface 5B of the manufacturing substrate 5 in which the areas of the other surfaces 2B, 3B and 4B are the work size (that is, the stacking substrates 2, 3 and 4 are separated by a predetermined distance sp1 and sp2.
The wirings W1, W2, and W3 are independently configured by separating them from each other), so that the shrinkage amounts sh3 and sh4, sh5 and sh6, sh7, and sh8 of the stacking substrates 2, 3 and 4 are the manufacturing substrate 5. Shrinkage of sh1 and s
It is much less than h2.

In addition to this, the lamination substrates 2, 3 and 4 are
Since the laminated substrates are held on the manufacturing substrate 5, the displacement of the laminating substrates 2, 3 and 4 with respect to the contraction operation of the manufacturing substrate 5 hardly occurs. That is, this is because the manufacturing substrate 5 is contracted while the positional relationship between the laminating substrates 2, 3, and 4 with respect to the manufacturing substrate 5 is substantially maintained.

Therefore, the wirings wir1, wir2 of the laminating substrates 2, 3 and 4 with respect to the wirings W1, W2 and W3 of the manufacturing substrate 5
The deviation amounts of wir3 and wir3 are the shrinkage amounts sh3 and sh4, sh5 and sh6, sh7 and sh of the stacking substrates 2, 3 and 4, respectively.
Therefore, the multi-layer substrate manufacturing apparatus has a stacking substrate 2, 3 and 4 for the manufacturing substrate 5 as a result.
The electrical connection can be performed in a state in which the positional deviation of the is minimized.

Here, in the above-mentioned first step (upper part of FIG. 1 (A)), the lamination substrates 2, 3 and 4 are almost the same as the production substrate 5.
The reason why the area is selected to be / 3 is, from the viewpoint of productivity that a large number of products can be manufactured by laminating at one time on one manufacturing substrate 5 having a work sheet size, the laminating substrate 2, It is desirable to minimize the area of one surface 2A, 3A and 4A of 3 and 4, but bare chips 11a and 11b.
And 11c, the shrinkage amounts sh3 and sh4, sh5 of the laminating substrates 2, 3, and 4 are taken into consideration.
Considering that the shrinkage amount is settled within the range of sh6, sh7, sh8 (FIG. 4), generally at least about 1/3 of the area of one surface 5A of the manufacturing wiring board 5 is required. This is because the area is considered to be ideal.

Therefore, in the multi-layer substrate manufacturing apparatus, in the first step (upper part of FIG. 1A), one surface 2A of the laminating substrates 2, 3 and 4 is
By dividing 3A and 4A so as to have an area that is approximately ⅓ of the area of the one surface 5A of the manufacturing substrate 5, the productivity can be ensured to the necessary maximum, and the laminating substrate for the manufacturing substrate 5 can be secured. The position shifts of 2, 3 and 4 can be minimized.

In this state, the fifth stage (see FIG. 4)
As (E)), the multilayer substrate manufacturing apparatus is used for laminating substrates 2 to 4
After forming a through hole substantially vertically from the predetermined position of the other surface 2B to 4B to the other surface 5B of the manufacturing substrate 5 through the wirings wir1 to wir3 and the wirings W1 to W3 in order, the inner peripheral surface of the through hole is formed. Copper plating is applied to the through holes 35A and 36A, 35B and 36B, 35C and 36C.

As a result, the multi-layer substrate manufacturing apparatus connects the other surfaces 2B to 4B and one surface 2A to 4A of the laminating boards 2 to 4 and the one surface 5A and the other surface 5B of the manufacturing board 5 to the through holes 35.
A and 36A, 35B and 36B, 35C and 36C are connected, and each layer from the other surface 2B to 4B of the laminating substrates 2 to 4 to the other surface 5B of the manufacturing substrate 5 is firmly electrically and mechanically connected. Connect between layers.

As a sixth step (FIG. 4 (F)), the multi-layer substrate manufacturing apparatus uses the other surfaces 2B, 3B of the laminating substrates 2, 3 and 4.
By forming the wirings 41, 42 and 43 having a predetermined pattern on the wiring layers 4 and 4B, the manufacturing multilayer substrate 50 is manufactured.

As a seventh step, as shown in FIG. 5, the multilayer substrate manufacturing apparatus cuts the manufacturing substrate 5 of the manufacturing multilayer substrate 50 (FIG. 4 (F)) at a predetermined position to thereby obtain the multilayer substrate 51. , 52 and 53 can be manufactured.

The multi-layered substrates 51, 52, and 53 are provided with respect to the manufacturing substrate 5 even when the organic materials of the manufacturing substrate 5 and the laminating substrates 2, 3 and 4 shrink due to heat treatment or cooling treatment in the manufacturing process. Laminating Substrates 2, 3 and 4
Through holes 35A and 36A, 35B and 36B, 35C and 36 with the positional deviation of
By being electrically connected via C, electrical resistance is strengthened as a whole.

In the above-described method for manufacturing a multilayer board, the apparatus for manufacturing a multilayer board first prepares the double-sided copper clad board 1a (upper part of FIG. 1A) made of a glass epoxy material having a work sheet size (area) on the manufacturing board 5. By preliminarily manufacturing the laminating substrate 2 by dividing it into an area of about 1/3 of the area of the one surface 5A, the laminating substrate 2 has a shrinkage amount smaller than that of the manufacturing substrate 5. The substrate 2 is selected.

Then, the multi-layer substrate manufacturing apparatus is provided with the manufacturing substrate 5
On the wiring W1 formed on the one surface 5A (FIG. 2C), the wiring circuit board 15 is positioned in a state where the wiring wir1 of the laminating board 2 is positioned so as to be opposed to each other via the interposition prepreg 25a and the cover lid prepreg 26a. Stack.

Here, the multilayer substrate manufacturing apparatus heat-cures the interposing prepreg 25a (FIG. 2 (D)) and the cover lid prepreg 26a to heat the manufacturing substrate 5, the interposing prepreg 25a, the cover lid prepreg 26a, and the laminating substrate 2. When the temperature is returned to room temperature after the integration, the lamination substrate 2 and the production substrate 5 shrink (FIG. 3) when cured according to the characteristics of the organic member.

However, the laminating substrate 2 has the other surface 2
Since B is smaller than the other surface 5B of the manufacturing substrate 5 having the work size, the shrinkage amounts sh3 and sh4 thereof are significantly smaller than the shrinkage amounts sh1 and sh2 of the manufacturing substrate 5, and As a result of the manufacturing substrate 5 contracting while the positional relationship of the laminating substrate 2 is substantially maintained, the deviation amount of the wiring wir1 of the laminating substrate 2 from the wiring W1 of the manufacturing substrate 5 is 2 shrinkage s
It falls within the range of h3 and sh4.

In this state, the multilayer substrate manufacturing apparatus is substantially vertical from the predetermined position of the other surface 2B of the laminating substrate 2 (FIG. 4 (E)) to the other surface 5B of the manufacturing substrate 5 via the wiring wir1 and the wiring W1. The through holes 35A and 36A are formed in.

Therefore, the multi-layer substrate manufacturing apparatus is provided with the manufacturing substrate 5
And even if the laminating substrate 2 shrinks, the wiring W of the manufacturing substrate 5
Since the positional deviation of the wiring wir1 with respect to 1 is within the range of the shrinkage amounts sh3 and sh4 of the laminating substrate 2, the electrical displacement is minimized with respect to the manufacturing substrate 5. Reliable connection can be performed.

Further, the multi-layer substrate manufacturing apparatus includes the manufacturing substrate 5
(FIG. 3) Wirings W2 and W3 are provided on one surface 5A at a predetermined interval sp.
1 and sp2 are separated from each other to be independent, and through holes 35B and 36 are formed by the same process as that for the laminating substrate 2.
B (FIG. 4 (E)), 35C and 36C are formed, so that the deviation amount of the wirings wir1, wir2 and wir3 of the laminating substrates 2, 3 and 4 with respect to the wiring W1 of the manufacturing substrate 5 can be determined. Shrinkage amounts sh3, sh4, sh5 of 2, 3 and 4
, And sh6, sh7, and sh8 can be realized at one time on one manufacturing substrate 5.

According to the method for manufacturing a multilayer circuit board as described above, the manufacturing apparatus for a multilayer board shrinks the manufacturing board 5 and the stacking board 2 due to the characteristics of the organic members of the manufacturing board 5 and the stacking board 2. Even if the deviation amount of the wiring wir1 of the laminating substrate 2 with respect to the wiring W1 of the manufacturing substrate 5 falls within the range of the shrinkage amounts sh3 and sh4 of the laminating substrate 2, The electrical connection can be surely performed with the positional deviation of the substrate 2 kept to a minimum, and thus a multilayer substrate having high electrical resistance can be manufactured by a simpler method than the conventional method. .

In the above-described embodiment, the double-sided copper clad plate is made to have an area of about 1/3 of the area of the one surface 5A of the manufacturing substrate 5 in the first step (upper part of FIG. 1A). Although the case has been described in which the laminating substrates 2, 3 and 4 are preliminarily produced by separating the laminating substrate 1a, the present invention is not limited to this. It is only necessary to use a laminating substrate having a shrinkage amount smaller than that of No. 5, and the point is that the shrinkage amount is smaller than the shrinkage amount of the manufacturing substrate when shifting to the process of the second stage (FIG. 1B). If the laminating substrate consisting of is selected, various other laminating substrates can be widely used.

In the above embodiment, the case where the interposing prepregs 25a to 25c and the cover lid prepregs 26a to 26c (interlayer portions 31 to 33) made of glass epoxy material are used as the connection intermediary portion has been described. The invention is not limited to this, and a connection intermediary portion made of various other materials such as polyphenylene ether or bismaleimide triazine may be used.

In this case, in particular, the connection intermediary portion made of a material having a large content of polyphenylene ether or bismaleimide triazine is used as the cover lid prepregs 26a to 26c and the insertion prepregs 25a to 25c made of a glass epoxy material.
Since the coefficient of thermal expansion is lower than that of, the warpage due to curing after heating can be effectively reduced, and the electrical connection is further improved with the positional deviation of the laminating substrate 2 with respect to the manufacturing substrate 5 further reduced. It can be executed reliably.

Further, in the above-described embodiment, bare chips 11a, 11b and 11c as surface mount components are used.
However, the present invention is not limited to this, and the bare chips 11a, 11 may be mounted.
b and 11c may be mounted on the manufacturing substrate 5. In this case, the same effect as that of the above-described embodiment can be obtained.

Further, in the above-described embodiment, bare chips 11a, 11b and 11c as surface mount components are used.
However, the present invention is not limited to this, and various other surface mount components such as components such as transistors and diodes can be mounted. In this case, the same effect as that of the above-described embodiment can be obtained.

Further, in the above-described embodiment, the case where the thickness of the interposing prepreg 25a, 25b or 25c is changed appropriately has been described, but the present invention is not limited to this, and the interposing prepreg 25a, 25b or 25c. In addition to changing the thickness of the product, the size of the stacking substrate 2, 3 or 4 is selected so as to be almost the same as the mounting area on the final product, and the wiring pattern is mounted on the wiring pattern for mounting the final product. 41, 42 or 43 may be formed.

In this case, the multi-layered board manufacturing apparatus can manufacture the multi-layered boards 51 to 53 as corresponding to the mounting space that can be mounted on the final product before the steps of manufacturing the multi-layered boards 51 to 53, and cut the multi-layered boards 51 to 53. After that, the mounting on the final product can be smoothly performed, and the redundant process at the time of mounting on the final product can be omitted.

Further, in the above-described embodiment, the through holes 35A and 36A, 35B and 36B, 35C.
And 36C, the case where the through hole is formed after the manufacturing substrate 5 and the laminating substrates 2 to 4 are integrated by the interposing prepregs 25a to 25c and the cover lid prepregs 26a to 26c has been described. The invention is not limited to this, and the through hole may be formed before the integration.

In this case, FIG. 2 showing the above-mentioned third stage.
As shown in FIG. 6 in which parts corresponding to those in (C) are denoted by the same reference numerals, the multilayer substrate manufacturing apparatus includes rod-shaped conducting members 62A and 63 made of conductive paste, solder, stud bumps, or the like.
A, 62B and 63B, 62C and 63C are preliminarily provided at the through hole forming positions on the wirings W1, W2 and W3 of the manufacturing substrate 5 and the interposing prepregs 25a to 25a are formed.
5c and the cover lid prepregs 26a to 26c, the conductive members 62A and 63A, 62B and 63B, 62C.
Through holes 64A and 65A, 64B and 65B, 64C and 65C are formed at positions corresponding to 63 and 63C, respectively.

The multi-layer substrate manufacturing apparatus has a through hole 64A.
And 65A, 64B and 65B, 64C and 65C to the conducting members 62A and 63A, 62B and 63B, 62C.
And 63C are inserted to insert the prepregs 25a to 25c.
And the cover lid prepregs 26a to 26c are sequentially laminated, and subsequently the lamination substrates 2, 3 and 4 on which the bare chips 11a, 11b and 11c are mounted are laminated, and then the interposition prepreg 2 is formed.
5a to 25c and the cover lid prepregs 26a to 26c are heated to produce the manufacturing substrate 5 and the laminating substrates 2, 3 and 4
Integrate with.

In this way, the apparatus for manufacturing a multilayer substrate is
The copper plating process in the fifth step (FIG. 4 (E)) described above can be omitted, and the shrinkage amount of the stacking substrate 2 with respect to the manufacturing substrate 5 can be determined by the shrinkage amount s of the stacking substrate 2.
By keeping the displacement within the range of h2, it is possible to further reliably perform the electrical connection in a state in which the positional deviation is further reduced.

Further, in the above-described embodiment, the case where the laminating substrate 2 is laminated on the one surface 5A of the manufacturing substrate 5 via the interposing prepreg 25a and the cover lid prepreg 26a has been described, but the present invention is not limited to this. No, manufacturing substrate 5
A lamination substrate may be laminated on the other surface 5B.

For example, as in the specific example shown in FIG. 7A in which parts corresponding to those in FIG. 4D are designated by the same reference numerals, the multilayer substrate manufacturing apparatus has the other surface 5B of the manufacturing substrate 5 which is turned upside down. The predetermined wiring 70 is formed on the
Flip chip mounting.

Subsequently, the multi-layered board manufacturing apparatus uses the manufacturing board 5
After laminating the insertion prepreg 72 surrounding the mounting portion of the bare chip 71 (a part may be open like a U shape) on the one surface 5B, the wiring 70 and the manufacturing substrate 5 Laminating substrate 73 having a smaller shrinkage amount than the shrinkage amount
The stacking substrate 73 is stacked in a state where the wiring and the wiring are positioned.

In this state, the multi-layer substrate manufacturing apparatus forms the through holes 75A and 75B after the manufacturing substrate 5, the interposed prepreg 72 and the laminating substrate 73 are integrated by heating and curing the interposed prepreg 72. To do.

Further, as in the specific example shown in FIG. 7B in which the same parts as those in FIG. 4D are denoted by the same reference numerals, the multilayer substrate manufacturing apparatus is different from the manufacturing substrate 5 which is turned upside down. Surface 5
A predetermined wiring 80 is formed on the wiring B, and the interposing prepreg 82 is laminated on the wiring 80. Then, the wiring 80 and the laminating substrate 8 having a shrinkage ratio smaller than that of the manufacturing substrate 5 are obtained.
And the wiring 3 is positioned and the lamination substrate 83 is positioned.
Are stacked.

In this state, the multi-layer substrate manufacturing apparatus forms the through hole 85 by integrating the manufacturing substrate 5, the interposed prepreg 82 and the laminating substrate 83 by heating and curing the interposed prepreg 82.

In the case of such a specific example, similarly to the above-described embodiment, the positional relationship between the wirings 70 and 80 of the manufacturing substrate 5 and the wirings of the laminating substrates 73 and 83 contracts while maintaining a substantially held state. As a result, the wiring 70 of the manufacturing substrate 5
Since the amount of wiring deviation of the stacking substrates 73 and 83 with respect to the stacking substrates 73 and 83 falls within the range of shrinkage of the stacking substrates 73 and 83, the multilayer substrate manufacturing apparatus uses the stacking substrate 2 (3, It is possible to surely perform the electrical connection in a state where both the positional deviation of 4) and the positional deviation of the laminating substrates 73 and 83 with respect to the manufacturing substrate 5 are minimized.

In addition to this, one surface of the laminating boards 73 and 83 and the areas of the interposing prepregs 72 and 82 are selected as sizes for mounting on the final product (mother board).
The thickness of the interposing prepregs 72 and 82 should be selected so that the height when the laminating substrate 73 or 83 is laminated on the manufacturing substrate 5 is substantially the same as the height when mounting on the final product. Even if the mounting space for the final product is complicated, the corresponding one can be manufactured on one manufacturing substrate 5, and as a result, the mounting on the final product can be smoothly performed, and at the same time, the final product can be mounted. It is possible to omit a redundant process at the time of mounting on.

[0063]

As described above, according to the present invention, a stacking substrate having a shrinkage amount smaller than that of a predetermined manufacturing substrate is selected, and the stacking substrate is positioned at a predetermined position of the manufacturing substrate.
The manufacturing substrate and the laminating substrate, which are positioned at predetermined positions via the connection intermediary portion that connects the manufacturing substrate and the laminating substrate, are cured and integrally formed to form the manufacturing substrate, the connection intermediary portion, and the laminating substrate. When the manufacturing substrate shrinks while the lamination substrate is positioned at a predetermined position due to the electrical connection to each other, the lamination substrate is less than the production substrate. By shrinking with the shrinkage amount, the positional deviation of the laminating substrate with respect to the predetermined position falls within the shrinkage amount range.

Therefore, in the present invention, even if the manufacturing substrate and the laminating substrate shrink, the positional deviation of the laminating substrate with respect to the predetermined position of the manufacturing substrate falls within the range of the shrinkage amount of the laminating substrate. Therefore, the electrical connection can be surely performed with the positional deviation of the stacking substrate with respect to the manufacturing substrate kept to a minimum, and thus, the multilayer wiring device having higher electrical resistance than the conventional one. Can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process (1) of a multilayer substrate.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process (2) of a multilayer substrate.

FIG. 3 is a schematic cross-sectional view showing the state of contraction in each substrate.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process (3) of a multilayer substrate.

FIG. 5 is a schematic cross-sectional view showing a multilayer substrate.

FIG. 6 is a schematic cross-sectional view showing formation of a through hole according to another embodiment.

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a multilayer substrate according to another embodiment.

[Explanation of symbols]

2, 3, 4, 73, 83 ... Laminating substrate, 5 ... Manufacturing substrate, 11a, 11b, 11c, 71 ... Bare chip,
15, 16, 17 ... Circuit board for stacking, 25a, 25
b, 25c ... Cover prepreg, 26a, 26b, 26
c, 72, 82 ... Interposition prepreg, 31, 32, 33
...... Interlayer part, 35A, 35B, 35C, 36A, 36
B, 36C, 75A, 75B, 85 ... through hole,
50 ... Multilayer substrate for manufacturing, 51, 52, 53 ... Multilayer substrate, 62A, 62B, 62C, 63A, 63B, 63C
... Conduction member, 64A, 64B, 64C, 65A, 6
5B, 65C ... through holes.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tomoyasu Gunji             19 Clover Den, 573 Toiso, Eniwa, Hokkaido             Child Industry Co., Ltd. (72) Inventor Toshihiro Murayama             Sony 6-735 Kitashinagawa, Shinagawa-ku, Tokyo             Within the corporation (72) Inventor Masayuki Yasuda             Sony 6-735 Kitashinagawa, Shinagawa-ku, Tokyo             Within the corporation F-term (reference) 5E346 AA05 AA12 AA15 AA22 AA24                       AA26 AA42 AA53 AA60 BB01                       CC08 CC31 DD02 DD32 EE02                       EE06 EE07 EE09 EE15 FF04                       FF45 GG22 GG26 GG28 HH11

Claims (2)

[Claims] 1. A selection step of selecting a stacking substrate having a shrinkage amount smaller than that of a predetermined manufacturing substrate, a positioning step of positioning the stacking substrate at a predetermined position of the manufacturing substrate, A curing step of curing and integrally forming the manufacturing substrate and the laminating substrate positioned at the predetermined position via a connection intermediary portion that connects the manufacturing substrate and the laminating substrate; A step of electrically connecting the connection mediation part and the stacking substrate to each other, wherein the curing step involves curing the manufacturing substrate and the stacking substrate positioned at the predetermined position. Thus, when the manufacturing substrate shrinks while the laminating substrate is positioned at the predetermined position, the laminating substrate shrinks with a smaller shrinkage amount than the manufacturing substrate. By so doing, the positional deviation of the stacking substrate with respect to the predetermined position is set to fall within the range of the shrinkage amount. 2. The laminating substrate having the same material as that of the manufacturing substrate and having an area which is approximately 1/3 or less of an area of one surface of the manufacturing substrate is selected in the selecting step. The method of manufacturing a multilayer substrate according to claim 1.