JP4137451B2 - Multilayer substrate manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer substrate manufacturing method, and is suitable for application to a multilayer substrate manufacturing method in which, for example, two substrates are laminated to manufacture a multilayer substrate.
[0002]
[Prior art]
Conventionally, in a multilayer substrate manufacturing method, a substrate for stacking having the same size and the same material as that of the manufacturing substrate is stacked on a manufacturing substrate having a manufacturing size, and one surface of the manufacturing substrate and the stacking substrate is stacked. On the other hand, a multilayer substrate is manufactured by forming through-holes substantially perpendicularly to each other and connecting the layers.
[0003]
[Problems to be solved by the invention]
By the way, in such a multilayer substrate manufacturing method, although the manufacturing substrate and the lamination substrate having the same size and the same material are used, the wiring occupancy ratio on one surface of the manufacturing substrate and the lamination substrate is different, so that the manufacturing process is in progress. The amount of shrinkage in the organic material of the substrate for production and the amount of shrinkage in the organic material of the substrate for lamination are greatly different due to the heat treatment and the cooling treatment.
[0004]
Therefore, in the multilayer substrate manufacturing method, even if the through hole is formed so as to penetrate substantially perpendicularly to one surface of the manufacturing substrate and the laminated substrate, the through hole that should be originally formed on the manufacturing substrate and the laminated substrate is used. Since the formation position of the hole is greatly shifted due to the difference in contraction amount, there is a problem that the electrical connection cannot be sufficiently performed and the electrical resistance is weak.
[0005]
The present invention has been made in consideration of the above points, and an object of the present invention is to propose a multilayer substrate manufacturing method capable of manufacturing a multilayer substrate having high electrical resistance by a simpler method than in the past.
[0006]
[Means for Solving the Problems]
  In order to solve this problem, the present invention provides:A bonding step of bonding an electronic component to the first substrate, and a prepreg lamination in which a plate-shaped prepreg provided with an accommodation space for the electronic component is stacked on a second substrate having a larger area than the first substrate. A step of laminating the first substrate to which the electronic component is bonded to the second plate-shaped prepreg so that the electronic component is accommodated in the accommodating space, and a heating step of heating the plate-shaped prepreg. A multilayer substrate manufacturing method with
[0007]
  ThereforeThis multilayer substrate manufacturing methodThen1st by heating in the heating processSubstrate andSecondEven if the substrate shrinks,SecondAgainst the substrateFirstThe substrate displacement isFirstWithin the shrinkage range of the boardIt becomes possible toFor,ConcernedMisalignmentDue to the firstSubstrate andA decrease in electrical resistance of the second substrate can be suppressed.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0009]
In this invention, the multilayer substrate manufacturing method for manufacturing the multilayer substrates 51-53 (FIG. 5) which are finished products is demonstrated using FIGS.
[0010]
As the first stage (upper stage in FIG. 1A), a multilayer board manufacturing apparatus (not shown) has a glass epoxy double-sided copper clad 1a having a worksheet size (area) for board manufacturing of approximately 1/3. After dividing into three substrates having the following areas, wiring is formed by one wiring pattern by sequentially performing etching resist processing and wet etching processing on the surfaces 2A, 3A, and 4A of the three substrates. By forming wir1, wir2 and wir3, the laminated substrates 2, 3 and 4 are produced.
[0011]
On the other hand, the multi-layer substrate manufacturing apparatus has a double-sided copper-clad plate 1a to a laminated substrate 2 from one side 5A of a double-sided copper-clad plate 1b having the same size and the same material as the double-sided copper-clad plate 1a (lower stage in FIG. The manufacturing substrate 5 is manufactured by forming the wirings W1, W2, and W3 by performing the same processing as described above at the positions corresponding to the wirings wir1, wir2, and wir3 when the 3 and 4 are manufactured.
[0012]
As a result, the multilayer substrate manufacturing apparatus selects the stacking substrates 2, 3 and 4 having an area of approximately 1/3 or less of the area of the one surface 5 </ b> A of the manufacturing substrate 5, and the wirings W <b> 1, W <b> 2 of the manufacturing substrate 5 and W3 can be formed in a state of being separated from each other by a predetermined distance.
[0013]
The reason why the stacking substrates 2, 3, and 4 are selected to be approximately 1/3 or less of the area of the one surface 5 </ b> A of the manufacturing substrate 5 will be described later.
[0014]
In addition, the multi-layer substrate manufacturing apparatus performs terminal plating on the wirings W1, W2, and W3 of the manufacturing substrate 5, thereby stacking the stacking substrates 2, 3, and 4 on the manufacturing substrate 5. Additional steps such as a masking process to be performed can be omitted.
[0015]
As the second stage (upper stage in FIG. 1B), the multilayer substrate manufacturing apparatus is formed on the surface 2A of the lamination substrate 2 and the stat bumps 12a formed at predetermined positions on the circuit formation surface of the bare chip 11a made of a semiconductor memory or the like. The inner peripheral wiring wir1 is joined (so-called flip chip mounting) via the anisotropic conductive film 13a.
[0016]
Similarly, the multi-layer substrate manufacturing apparatus includes stat bumps 12b and 12c formed at predetermined positions on the circuit formation surfaces of the bare chips 11b and 11c, inner wirings wir2 formed on one surface 3A and 4A of the substrates 3 and 4 for lamination, and Wir3 is flip-chip mounted via anisotropic conductive films 13b and 13c.
[0017]
As a third stage (FIG. 2C), the multilayer substrate manufacturing apparatus includes an insertion prepreg 25a made of a glass epoxy material having substantially the same area as the one surface 2A of the substrate for lamination 2 on the wiring W1 of the substrate for manufacturing 5. The cover prepreg 26a is sequentially laminated, and the lamination substrate 2 on which the bare chip 11a is mounted is laminated in a state where the wiring wir1 is positioned facing the wiring W1.
[0018]
Similarly, the multi-layer substrate manufacturing apparatus has glass epoxy material insertion prepregs 25b and 25c and a cover prepreg having substantially the same area as the surfaces 3A and 4A of the substrates 3 and 4 on the wirings W2 and W3 of the substrate 5 for manufacturing. 26b and 26c are sequentially stacked, and the stacked substrates 3 and 4 on which the bare chips 11b and 11c are mounted are stacked in a state where the wirings wir2 and wir3 are positioned facing the wirings W2 and W3.
[0019]
Here, the inserted prepregs 25a, 25b and 25c are for selecting a predetermined thickness between the manufacturing substrate 5 and the stacking substrates 2, 3 and 4, and the cover prepreg 26a, 26b and 26c are for covering the bare chips 11a, 11b and 11c.
[0020]
In this case, the multilayer substrate manufacturing apparatus can appropriately change the thickness of the interposed prepregs 25a, 25b, or 25c, whereby the stacking substrate 2, 3 or 4 is stacked on the manufacturing substrate 5. Thus, the height can be made to substantially coincide with the height required when mounted on a motherboard used as a part of the final product.
[0021]
Therefore, the multilayer substrate manufacturing apparatus can flexibly cope with the height restriction when the thickness between the manufacturing substrate 5 and the stacking substrate 2, 3 or 4 is mounted on the mounting device. Yes.
[0022]
Further, the multilayer substrate manufacturing apparatus can form the bare chip cover spaces v1, v2, and v3 by removing a part of the cover prepreg 26a, 26b, or 26c according to the volume of the bare chip 11a, 11b, or 11c. Yes.
[0023]
As a result, the multilayer substrate manufacturing apparatus can accommodate the bare chips 11a, 11b, and 11c via the bare chip covering spaces v1, v2, and v3, so that the stacking substrates 2, 3, and the bare chips 11a, 11b, and 11c mounted thereon can be accommodated. 4 can be stacked on the cover prepregs 26a, 26b and 26c without interfering with each other, and when the cover prepregs 26a, 26b and 26c are thermally cured in the stacked state, the cover prepregs 26a, 26b and 26c It is made to be able to diffuse.
[0024]
Accordingly, as the fourth stage (FIG. 2D), the multilayer substrate manufacturing apparatus heats the insertion prepregs 25a to 25c and the cover prepregs 26a to 26c (FIG. 2C) to a predetermined temperature in a vacuum atmosphere. The periphery of the bare chips 11a to 11c is covered by diffusion when the insertion prepregs 25a to 25c and the cover prepregs 26a to 26c are thermally cured, and the stacking substrates 2 to 4 and the manufacturing substrate 5 are integrated with keeping airtightness. The formed interlayer portions 31, 32, and 33 are formed.
[0025]
After that, when the multilayer substrate manufacturing apparatus returns to room temperature and normal pressure, the laminated substrates 2, 3, 4 and the manufacturing substrate 5 are opposite to the thermosetting insertion prepregs 25 a to 25 c and the cover lid prepregs 26 a to 26 c. Since the organic member of the laminated substrates 2, 3, 4 and the manufacturing substrate 5 is cured according to the characteristics, the organic member is eventually contracted.
[0026]
In this case, for example, as shown in FIG. 3, the production substrate 5 and the lamination substrates 2, 3, and 4 are made of the same material and have the same shrinkage rate, but the lamination substrates 2, 3, and 4 are The areas of the other surfaces 2B, 3B and 4B are smaller than the other surface 5B of the manufacturing substrate 5 having the work size (that is, the wiring substrates W1, W2 and W2 are separated by separating the lamination substrates 2, 3 and 4 by a predetermined interval sp1 and sp2, respectively. W3 is an independent configuration), and the shrinkage amounts sh3 and sh4, sh5 and sh6, sh7 and sh8 of the multilayer substrates 2, 3 and 4 are much higher than the shrinkage amounts sh1 and sh2 of the manufacturing substrate 5. Less.
[0027]
In addition to this, since the lamination substrates 2, 3 and 4 are held in a state of being laminated on the production substrate 5, the positions of the lamination substrates 2, 3 and 4 with respect to the contraction operation of the production substrate 5. Almost no deviation occurs. That is, the manufacturing substrate 5 is contracted while the positional relationship of the stacking substrates 2, 3 and 4 is substantially maintained with respect to the manufacturing substrate 5.
[0028]
Accordingly, the shift amounts of the wirings wir1, wir2 and wir3 of the lamination substrates 2, 3 and 4 with respect to the wirings W1, W2 and W3 of the production substrate 5 are the shrinkage amounts sh3 and sh4 and sh5 of the lamination substrates 2, 3 and 4. As a result, the multilayer substrate manufacturing apparatus is electrically connected with the positional deviation of the stacked substrates 2, 3 and 4 with respect to the manufacturing substrate 5 being minimized. A connection can be made.
[0029]
Here, the reason why the laminating substrates 2, 3, and 4 are selected to be approximately 1/3 the area of the manufacturing substrate 5 in the first stage (the upper stage in FIG. 1A) is 1 that is a worksheet size. From the viewpoint of productivity in which a large number of products can be manufactured by laminating on a single manufacturing substrate 5, the area of one side 2A, 3A and 4A of the laminating substrates 2, 3 and 4 should be made as small as possible. However, the shrinkage amounts sh3 and sh4, sh5 and sh6, sh7 and sh8 (FIG. 4) of the laminated substrates 2, 3 and 4 are taken into account while considering the necessity of mounting the bare chips 11a, 11b and 11c. Considering that the amount of shrinkage can be accommodated in the inside, it is generally considered that an area of at least about 1/3 with respect to the area of one surface 5A of the manufacturing wiring board 5 is ideal. is there.
[0030]
Therefore, in the first stage (the upper stage in FIG. 1A), the multilayer substrate manufacturing apparatus is configured so that the surfaces 2A, 3A, and 4A of the lamination substrates 2, 3, and 4 are approximately 1/3 of the area of the surface 5A of the manufacturing substrate 5. By cutting the area so as to have an area, the productivity can be ensured to the maximum necessary, and the misalignment of the laminated substrates 2, 3 and 4 with respect to the manufacturing substrate 5 can be minimized. Yes.
[0031]
In this state, as the fifth stage (FIG. 4E), the multilayer substrate manufacturing apparatus sequentially passes the wirings wir1 to wir3 and the wirings W1 to W3 from predetermined positions on the other surfaces 2B to 4B of the stacking substrates 2 to 4. After a through hole is formed almost vertically over the other surface 5B of the manufacturing substrate 5, copper plating is performed on the inner peripheral surface of the through hole to form through holes 35A and 36A, 35B and 36B, 35C and 36C. To do.
[0032]
Thereby, the multilayer substrate manufacturing apparatus includes the other surfaces 2B to 4B and the other surfaces 2A to 4A of the stacking substrates 2 to 4 and the one surface 5A and the other surface 5B of the manufacturing substrate 5 to the through holes 35A and 36A, 35B and 36B, The layers from the other surfaces 2B to 4B of the stacking substrates 2 to 4 to the other surface 5B of the manufacturing substrate 5 are firmly and electrically connected to each other via 35C and 36C.
[0033]
As a sixth stage (FIG. 4F), the multilayer substrate manufacturing apparatus forms wirings 41, 42, and 43 having a predetermined pattern on the other surfaces 2B, 3B, and 4B of the laminated substrates 2, 3, and 4, A multilayer board 50 for manufacturing is produced.
[0034]
As a seventh stage, as shown in FIG. 5, the multilayer substrate manufacturing apparatus cuts the manufacturing substrate 5 of the manufacturing multilayer substrate 50 (FIG. 4F) at a predetermined position, so that the multilayer substrates 51, 52 and 53 can be manufactured.
[0035]
The multilayer substrates 51, 52 and 53 are laminated substrates for the production substrate 5 even when the organic material of the production substrate 5 and the lamination substrates 2, 3 and 4 is shrunk by heat treatment or cooling treatment during the production process. The electrical resistance is enhanced as a whole by being electrically connected through the through holes 35A and 36A, 35B and 36B, 35C and 36C in a state where the positional deviation of 2, 3, and 4 is minimized. Has been.
[0036]
In the multilayer substrate manufacturing method described above, the multilayer substrate manufacturing apparatus first uses a glass epoxy material double-sided copper-clad plate 1a (upper stage in FIG. 1A) having a worksheet size (area) on one surface 5A of the manufacturing substrate 5. The lamination substrate 2 is cut in advance so as to have an area that is approximately 1/3 of the area, whereby the lamination substrate 2 having a smaller shrinkage amount than the shrinkage amount of the production substrate 5 is obtained. Select.
[0037]
Then, the multilayer substrate manufacturing apparatus causes the wiring wir1 of the lamination substrate 2 to face the wiring W1 formed on the one surface 5A (FIG. 2C) of the manufacturing substrate 5 via the insertion prepreg 25a and the cover prepreg 26a. Then, the laminated circuit board 15 is laminated in the positioned state.
[0038]
Here, the multilayer substrate manufacturing apparatus heats and cures the insertion prepreg 25a (FIG. 2D) and the cover prepreg 26a, and integrates the manufacturing substrate 5, the insertion prepreg 25a, the cover prepreg 26a, and the lamination substrate 2. Then, when the temperature is returned to room temperature, the lamination substrate 2 and the production substrate 5 shrink (FIG. 3) when cured according to the characteristics of the organic member.
[0039]
However, since the laminated substrate 2 is smaller than the other surface 5B of the manufacturing substrate 5 whose other surface 2B is a workpiece size, the shrinkage amounts sh3 and sh4 are much smaller than the shrinkage amounts sh1 and sh2 of the manufacturing substrate 5. The wiring of the stacking substrate 2 with respect to the wiring W1 of the manufacturing substrate 5 is reduced by shrinking the manufacturing substrate 5 while the positional relationship of the stacking substrate 2 with respect to the manufacturing substrate 5 is substantially maintained. The shift amount of wir1 falls within the range of the shrinkage amounts sh3 and sh4 of the laminated substrate 2.
[0040]
In this state, the multilayer substrate manufacturing apparatus has a through-hole substantially perpendicularly extending from a predetermined position on the other surface 2B of the lamination substrate 2 (FIG. 4E) to the other surface 5B of the manufacturing substrate 5 via the wiring wir1 and the wiring W1. 35A and 36A were formed.
[0041]
Accordingly, in the multilayer substrate manufacturing apparatus, even if the manufacturing substrate 5 and the lamination substrate 2 are contracted, the displacement of the wiring wir1 with respect to the wiring W1 of the manufacturing substrate 5 is within the range of the contraction amounts sh3 and sh4 of the stacking substrate 2. Therefore, electrical connection can be reliably performed in a state where the positional deviation of the laminated substrate 2 with respect to the manufacturing substrate 5 is minimized.
[0042]
Further, the multilayer substrate manufacturing apparatus has a configuration in which the wirings W2 and W3 are separated from each other by a predetermined interval sp1 and sp2 on one surface 5A of the manufacturing substrate 5 (FIG. 3), and through-holes are formed by the same process as the stacking substrate 2. By forming 35B and 36B (FIG. 4E), 35C and 36C, the shift amounts of the wirings wir1, wir2 and wir3 of the lamination substrates 2, 3 and 4 with respect to the wiring W1 of the production substrate 5 are laminated. The shrinkage amounts sh3 and sh4, sh5 and sh6, sh7 and sh8 of the production substrates 2, 3 and 4 can be realized on one manufacturing substrate 5 at a time.
[0043]
According to the multilayer circuit board manufacturing method as described above, the multilayer board manufacturing apparatus is configured such that even if the manufacturing board 5 and the lamination board 2 contract due to the characteristics of the organic members of the production board 5 and the lamination board 2, Since the shift amount of the wiring wir1 of the lamination substrate 2 with respect to the wiring W1 of the production substrate 5 falls within the range of the shrinkage amounts sh3 and sh4 of the lamination substrate 2, the lamination substrate 2 with respect to the production substrate 5 Electrical connection can be reliably performed with the positional deviation kept to a minimum, and thus a multilayer substrate having high electrical resistance can be manufactured by a simpler method than in the past.
[0044]
In the above-described embodiment, the double-sided copper-clad plate 1a is cut in the first stage (the upper stage in FIG. 1A) so that the area of the one surface 5A of the manufacturing substrate 5 is approximately 1/3. However, the present invention is not limited to this, and the present invention is not limited to this. It is only necessary to use a laminated substrate with a small amount of shrinkage, and the point is that the amount of shrinkage is smaller than the amount of shrinkage of the production substrate when the process proceeds to the second stage (FIG. 1B). If a substrate for use is selected, a variety of other laminated substrates can be used widely.
[0045]
In the above-described embodiment, the case where the insertion prepregs 25a to 25c and the cover prepregs 26a to 26c (interlayer portions 31 to 33) made of glass epoxy material are used as the connection mediating portion is described. In addition to the above, a connection mediating portion made of various other materials such as polyphenylene ether or bismaleimide triazine may be used.
[0046]
In this case, in particular, the connection mediating portion made of a material having a high content of polyphenylene ether or bismaleimide triazine has a lower coefficient of thermal expansion than the cover prepregs 26a to 26c and the interposed prepregs 25a to 25c made of glass epoxy material. Therefore, the warp due to curing after heating can be effectively reduced, so that the electrical connection can be more reliably performed in a state in which the positional deviation of the lamination substrate 2 with respect to the production substrate 5 is further reduced.
[0047]
Furthermore, in the above-described embodiment, the case where the bare chips 11a, 11b, and 11c as the surface mounting components are mounted on the lamination substrates 2, 3, and 4 has been described. However, the present invention is not limited to this, and the bare chips 11a, 11b are mounted. And 11c may be mounted on the manufacturing substrate 5. In this case, the same effect as that of the above-described embodiment can be obtained.
[0048]
Further, in the above-described embodiment, the case where the bare chips 11a, 11b, and 11c as the surface mounting components are mounted has been described. However, the present invention is not limited to this, and various other surfaces including components such as transistors and diodes. A mounting component can be mounted. In this case, the same effect as that of the above-described embodiment can be obtained.
[0049]
Furthermore, in the above-mentioned embodiment, although the case where the thickness of the insertion prepreg 25a, 25b or 25c was changed suitably was described, this invention is not limited to this, The thickness of the said insertion prepreg 25a, 25b or 25c In addition to the above change, the size of the laminated substrate 2, 3 or 4 is selected so as to be approximately the same as the area for mounting on the final product, and the wiring 41, 42 is mounted on the wiring pattern for mounting the final product, respectively. Alternatively, 43 may be formed.
[0050]
In this case, the multilayer substrate manufacturing apparatus can be manufactured as a device corresponding to a mounting space that can be mounted on the final product before the step of manufacturing the multilayer substrates 51 to 53, and after being cut as the multilayer substrates 51 to 53, Mounting on the final product can be performed smoothly, and redundant steps when mounting on the final product can be omitted.
[0051]
Further, in the above-described embodiment, when the through holes 35A and 36A, 35B and 36B, 35C and 36C are formed, the interposing prepregs 25a to 25c and the cover prepregs are interposed between the production substrate 5 and the lamination substrates 2 to 4. Although the case where the through holes are formed after being integrated by 26a to 26c has been described, the present invention is not limited thereto, and the through holes may be formed before the integration.
[0052]
In this case, as shown in FIG. 6 in which the same reference numerals are assigned to the parts corresponding to FIG. 2C showing the third stage described above, the multilayer substrate manufacturing apparatus is made of conductive paste, solder, stud bumps, or the like. The rod-like conducting members 62A and 63A, 62B and 63B, 62C and 63C are projected in advance at the through-hole forming positions on the wirings W1, W2 and W3 of the manufacturing substrate 5, and the insertion prepregs 25a to 25c and Through holes 64A and 65A, 64B and 65B, 64C and 65C are formed in the cover prepregs 26a to 26c at positions corresponding to the conducting members 62A and 63A, 62B and 63B, 62C and 63C, respectively.
[0053]
The multilayer board manufacturing apparatus inserts the conducting members 62A and 63A, 62B and 63B, 62C and 63C through the through holes 64A and 65A, 64B and 65B, 64C and 65C, and inserts the prepregs 25a to 25c and the cover prepregs 26a to 26c. 26c are sequentially stacked, and subsequently, the stacking substrates 2, 3 and 4 on which the bare chips 11a, 11b and 11c are mounted are stacked, and then the interposing prepregs 25a to 25c and the cover prepregs 26a to 26c are heated. The substrate 5 and the lamination substrates 2, 3 and 4 are integrated.
[0054]
In this way, the multilayer substrate manufacturing apparatus can eliminate the copper plating process in the fifth stage (FIG. 4E) and can reduce the shrinkage amount of the stacking substrate 2 relative to the manufacturing substrate 5. The electrical connection can be more reliably performed in a state where the positional deviation is further reduced as the stacking substrate 2 falls within the shrinkage sh2.
[0055]
Further, in the above-described embodiment, the case where the lamination substrate 2 is laminated on the one surface 5A of the production substrate 5 via the insertion prepreg 25a and the cover prepreg 26a has been described. However, the present invention is not limited thereto, and the production is not limited thereto. A lamination substrate may be laminated on the other surface 5B of the production substrate 5.
[0056]
For example, as in the specific example shown in FIG. 7A in which the same reference numerals are assigned to the parts corresponding to FIG. 4D, the multilayer substrate manufacturing apparatus has a predetermined surface on the other surface 5B of the manufacturing substrate 5 turned upside down. A wiring 70 is formed, and a bare chip 71 is flip-chip mounted on the formation portion.
[0057]
Subsequently, the multilayer board manufacturing apparatus laminates an insertion prepreg 72 that surrounds the mounting portion of the bare chip 71 on the surface 5B of the manufacturing board 5 (a part may be vacant like a U-shape). Thereafter, the lamination substrate 73 is laminated in a state where the wiring 70 and the wiring of the lamination substrate 73 having a smaller shrinkage amount than the shrinkage amount of the manufacturing substrate 5 are positioned.
[0058]
In this state, the multilayer board manufacturing apparatus heats the insertion prepreg 72 to form the through holes 75 </ b> A and 75 </ b> B after integrating the manufacturing board 5, the insertion prepreg 72, and the lamination board 73.
[0059]
Further, for example, as in the specific example shown in FIG. 7B in which the same reference numerals are given to the corresponding parts to FIG. 4D, the multilayer substrate manufacturing apparatus is arranged on the other surface 5B of the manufacturing substrate 5 turned upside down. After forming the predetermined wiring 80 and laminating the insertion prepreg 82 on the wiring 80, the wiring 80 and the wiring of the lamination substrate 83 having a smaller shrinkage rate than the shrinkage rate of the manufacturing substrate 5 In this state, the lamination substrate 83 is laminated.
[0060]
In this state, the multilayer substrate manufacturing apparatus heats and cures the insertion prepreg 82, thereby forming the through hole 85 after integrating the manufacturing substrate 5, the insertion prepreg 82, and the lamination substrate 83.
[0061]
In the case of such a specific example, as in the above-described embodiment, the positional relationship between the wirings 70 and 80 of the manufacturing substrate 5 and the wirings of the lamination substrates 73 and 83 is contracted while being substantially held. Since the amount of displacement of the wiring of the lamination substrates 73 and 83 with respect to the wiring 70 and 80 of the production substrate 5 falls within the range of the contraction amount of the lamination substrates 73 and 83, the multilayer substrate production apparatus is provided with the production substrate 5 The electrical connection is reliably executed in a state where both the positional deviation of the laminated substrate 2 (3, 4) with respect to the substrate and the positional deviation of the laminated substrates 73 and 83 with respect to the manufacturing substrate 5 are kept to a minimum. be able to.
[0062]
In addition, the area of one side of the laminating substrates 73 and 83 and the area of the interposing prepregs 72 and 82 is selected as a size for mounting on the final product (mother substrate), and the laminating substrate with respect to the manufacturing substrate 5 If the thickness of the insertion prepregs 72 and 82 is selected so that the height when the layers 73 and 83 are stacked substantially matches the height when mounted on the final product, the mounting space on the final product is complicated. Even in this case, the corresponding product can be manufactured on one manufacturing substrate 5, and as a result, the mounting to the final product can be performed smoothly and the redundant process at the time of mounting to the final product can be omitted. can do.
[0063]
【The invention's effect】
  As described above, the present inventionA bonding step of bonding an electronic component to the first substrate, and a prepreg lamination in which a plate-shaped prepreg provided with an accommodation space for the electronic component is stacked on a second substrate having a larger area than the first substrate. A step of laminating the first substrate to which the electronic component is bonded to the second plate-shaped prepreg so that the electronic component is accommodated in the accommodating space, and a heating step of heating the plate-shaped prepreg. A multilayer substrate manufacturing method with
[0064]
  ThereforeThis multilayer substrate manufacturing methodThen1st by heating in the heating processSubstrate andSecondEven if the substrate shrinks,SecondAgainst the substrateFirstThe substrate displacement isFirstWithin the shrinkage range of the boardIt becomes possible toFor,ConcernedMisalignmentDue to the firstSubstrate andA reduction in electrical resistance of the second substrate can be suppressed, and thus a multilayer substrate manufacturing method having high electrical resistance can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a manufacturing step (1) of a multilayer substrate.
FIG. 2 is a schematic cross-sectional view showing a manufacturing step (2) of the multilayer substrate.
FIG. 3 is a schematic cross-sectional view showing a state of contraction in each substrate.
FIG. 4 is a schematic cross-sectional view showing a manufacturing step (3) of the multilayer substrate.
FIG. 5 is a schematic cross-sectional view showing a multilayer substrate.
FIG. 6 is a schematic cross-sectional view showing formation of a through hole according to another embodiment.
FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process of a multilayer substrate according to another embodiment.
[Explanation of symbols]
2, 3, 4, 73, 83... Laminating substrate, 5... Manufacturing substrate, 11a, 11b, 11c, 71... Bare chip, 15, 16, 17 .. Laminating circuit substrate, 25a, 25b, 25c …… Cover prepreg, 26a, 26b, 26c, 72, 82 …… Interpolated prepreg, 31, 32, 33 …… Interlayer part, 35A, 35B, 35C, 36A, 36B, 36C, 75A, 75B, 85 …… Through Hall, 50 ... multilayer substrate for manufacturing, 51, 52, 53 ... multilayer substrate, 62A, 62B, 62C, 63A, 63B, 63C ... conductive member, 64A, 64B, 64C, 65A, 65B, 65C ... Through hole.

Claims (2)

A bonding step of bonding electronic components to the first substrate;
A prepreg laminating step of laminating a plate-shaped prepreg provided with an accommodation space for the electronic component on a second substrate having a larger area than the first substrate;
A substrate laminating step of laminating the first substrate to which the electronic component is bonded to the plate-shaped prepreg so that the electronic component is accommodated in the accommodating space;
Multilayer substrate manufacturing method characterized by obtaining ingredients and heating step of heating the plate-shaped prepreg. In the prepreg lamination process,
A plate-like prepreg for height adjustment and a plate-like prepreg provided with a housing space for the electronic component are sequentially laminated on the second substrate,
In the heating step,
2. The method for producing a multilayer substrate according to claim 1, wherein the plate-like prepreg for adjusting the height and the plate-like prepreg provided with a housing space for the electronic component are heated .

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