JPH098175A - Shelf formation method and bonding of multilayer printed-circuit board - Google Patents

Shelf formation method and bonding of multilayer printed-circuit board

Info

Publication number
JPH098175A
JPH098175A JP7171391A JP17139195A JPH098175A JP H098175 A JPH098175 A JP H098175A JP 7171391 A JP7171391 A JP 7171391A JP 17139195 A JP17139195 A JP 17139195A JP H098175 A JPH098175 A JP H098175A
Authority
JP
Japan
Prior art keywords
bonding
circuit board
shelf
resin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7171391A
Other languages
Japanese (ja)
Inventor
Tadashi Hirakawa
董 平川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jtekt Column Systems Corp
Original Assignee
Fuji Kiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Kiko Co Ltd filed Critical Fuji Kiko Co Ltd
Priority to JP7171391A priority Critical patent/JPH098175A/en
Publication of JPH098175A publication Critical patent/JPH098175A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: To obtain a shelf formation method in which a prinetd-circuit board with a multistage bonding shelf can be manufactured easily, in which a printed- wiring board used to mount a semiconductor chip or the like can be manufactured with high accuracy and at low costs and in which a printed-circuit board, for a pin-grid array, with a bonding shelf and a printed-circuit board for a ball-grid array can be manufactured with high accuracy and at low costs by making use of it. CONSTITUTION: In a shelf formation method for bonding of a multilayer printed- circuit board, a bonding terminal 15 is formed in advance in a multilayer printed-circuit board which has formed a circuit 7 at the inside, a resin layer 8 which is situated at the upper part of the terminal 15 in an inner layer 2 is then removed, an opening is formed, and a bonding shelf 12 in which the terminal 15 is exposed is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層構造のプリント基
板の回路端子即ちボンディング端子を、半導体チップ等
の電子部品(以下半導体チップ等という)とワイヤーボ
ンディングするため、内層のボンディング端子が露出し
たボンディング用棚を形成する方法に関する。
BACKGROUND OF THE INVENTION The present invention wire-bonds a circuit terminal or bonding terminal of a printed circuit board having a multi-layer structure to an electronic component such as a semiconductor chip (hereinafter referred to as a semiconductor chip), so that the bonding terminal of the inner layer is exposed. A method of forming a bonding shelf.

【0002】[0002]

【従来の技術】近年、プリント基板の多様化・高級化に
伴い、プリント基板を多層化してその一部を開口し、該
開口部に半導体チップ等を搭載して、プリント基板との
間でワイヤーボンディングする実装方法が増加してい
る。特にマルチチップモジュール、ボールグリッドアレ
イ、放熱フラットバック等のパッケージでは、これら半
導体チップ等とプリント基板とをワイヤーボンディング
することが多い。
2. Description of the Related Art In recent years, with the diversification and high quality of printed circuit boards, the printed circuit boards are multi-layered and a part of the printed circuit board is opened, and a semiconductor chip or the like is mounted in the opening, and a wire is connected to the printed circuit board. Mounting methods for bonding are increasing. In particular, in a package such as a multi-chip module, a ball grid array, or a heat dissipation flat bag, these semiconductor chips and the like are often wire-bonded to a printed board.

【0003】さらに、半導体チップ等が高密度化・多ピ
ン化したことにより、これらと接続するボンディング用
ワイヤーの必要本数も増加するので、プリント基板の1
面だけではボンディング端子の本数を充分に確保できな
い。そこで、プリント基板も高密度化・多層化する必要
があり、各層でボンディング端子が露出する階段状のボ
ンディング用棚を形成することが行われてきた。例え
ば、米国特許第5235211号で、先行技術を示す図
1に描かれているのがこれである。
Further, since the semiconductor chips and the like have a higher density and a larger number of pins, the required number of bonding wires for connecting to them also increases.
It is not possible to secure a sufficient number of bonding terminals with only the surface. Therefore, it is necessary to increase the density and the number of layers of the printed circuit board, and step-like bonding shelves in which the bonding terminals are exposed have been formed in each layer. This is the case, for example, in US Pat. No. 5,352,211 depicted in FIG. 1 which illustrates the prior art.

【0004】そして、プリント基板にボンディング用棚
を形成する従来手段は、例えば特公平2−5014号公
報に示されている。イ)その1つは、同公報で従来例を
示す第2図AとBに描かれているものであり、これを簡
略化して示すと本願の図9ないし図13の如くになる。
A conventional means for forming a bonding shelf on a printed circuit board is disclosed in, for example, Japanese Patent Publication No. 2-5014. B) One of them is illustrated in FIGS. 2A and 2B showing the conventional example in the publication, and it can be simplified as shown in FIGS. 9 to 13 of the present application.

【0005】即ち、回路27が形成された基材26の基
板25と、それ以外に予め、大きさが異なる開口30,
31が形成され、かつ回路32,33を形成されたた複
数枚の基材28,29─を用意し、上記基板25上に開
口30,31の小さい基材28から順次、接着シートま
たはプリプレグ34により貼り付けて積層・多層化す
る。これで中央部寄りに、開口が階段状となって形成さ
れるので、最下段の開口をキャビティ部にして、各開口
30,31周辺の各段部をボンディング端子37,38
が露出したボンディング用棚35,36が形成される。
なお各回路27,28,28はスルホール又はブライン
ドヴィアホール(図示略)で導通される。
That is, the substrate 25 of the base material 26 on which the circuit 27 is formed, and the other openings 30 having different sizes in advance,
A plurality of base materials 28 and 29 on which the circuits 31 and 31 and the circuits 32 and 33 are formed are prepared, and an adhesive sheet or a prepreg 34 is sequentially formed on the substrate 25 from the base material 28 having the smaller openings 30 and 31. To be laminated to form a multi-layer. As a result, the opening is formed in a stepwise shape near the central portion, so that the opening at the bottom is used as a cavity and the steps around the openings 30 and 31 are bonded to the bonding terminals 37 and 38.
Bonding shelves 35 and 36 having exposed portions are formed.
The respective circuits 27, 28, 28 are conducted by through holes or blind via holes (not shown).

【0006】ロ)また、上記特公平2−5014号公報
に記載の発明は、上記イ)との相違点を中心に述べる
と、上記イ)と同様な基板の上に複数枚の基材を積層し
多層化するとともに、該基材上面に開口の無い上基材を
積層して内部を密閉し、積層されたこれら基材にスルホ
ールとメッキを施し、最後に上基材に開口を形成するよ
うにしたものである。
(B) Further, the invention described in Japanese Patent Publication No. 2-5014 mentioned above mainly describes the difference from the above-mentioned a), and a plurality of base materials are provided on the same substrate as the above-mentioned a). In addition to stacking and forming multiple layers, an upper base material having no opening is stacked on the upper surface of the base material to seal the inside, and through holes and plating are applied to these stacked base materials, and finally an opening is formed in the upper base material. It was done like this.

【0007】[0007]

【発明が解決しようとする課題】ところで、上記従来の
ボンディング用棚を形成する手段の内、イ)で述べたも
のは、スルホールに無電解銅メッキ等を施す際に、基板
上の銅箔やボンディング用棚のボンディング端子、さら
にはボンディング棚の壁面や回路の絶縁物等にメッキが
析出してしまう、という問題点があった。
By the way, among the above-mentioned conventional means for forming a shelf for bonding, the one described in (a) is a method for forming a copper foil or a copper foil on a substrate when electroless copper plating or the like is applied to a through hole. There is a problem that plating deposits on the bonding terminals of the bonding shelf, and further on the wall surface of the bonding shelf and the insulator of the circuit.

【0008】他方、ロ)で述べたものは、最後に上板に
開口を形成するので、不要な無電解メッキが基板上の銅
箔やボンディング端子に付着するのを阻止できる。しか
し上記イ)と同様に、各基材を貼り付けるのに、接着シ
ートやプリプレグを用いて、高圧プレスで圧着・熱キュ
アされているため、次のような問題点が残っている。
On the other hand, in the one described in (b), since the opening is finally formed in the upper plate, it is possible to prevent unnecessary electroless plating from adhering to the copper foil or the bonding terminal on the substrate. However, similarly to the above-mentioned a), since the adhesive sheets and the prepregs are used for bonding the respective base materials, they are pressure-bonded and heat-cured by a high-pressure press, so that the following problems remain.

【0009】a)上記接着シートやプリプレグが、高圧
プレスで圧着・熱キュアする際に樹脂が各段部で開口側
へ滲み出てきて、ボンディング端子の接触不良の原因と
なる場合がある。 b)樹脂の滲み出しを避けるため圧着時の圧力を下げる
と、樹脂のフローが不十分となり、各層間の回路を埋め
るだけ行きわたらず、品質上・信頼性に問題が生じる場
合がある。 c)また予め回路や開口を形成した各基材を積層・多層
化するので、貼り付ける際に高い位置精度が要求され、
位置決めピン等を用いて積層しているが、導体チップ等
やプリント基板が高密度化し、更に厳しい位置精度が要
求されるようになり、必要な位置精度を得られず、歩留
りが低下してきている。
A) When the above-mentioned adhesive sheet or prepreg is pressure-bonded and heat-cured by a high-pressure press, the resin may exude to the opening side at each step, which may cause a contact failure of the bonding terminal. b) If the pressure at the time of crimping is reduced in order to prevent the resin from seeping out, the flow of the resin becomes insufficient and the circuit between layers is not filled up, which may cause problems in terms of quality and reliability. c) In addition, since each base material on which circuits and openings are formed in advance is laminated / multi-layered, high positioning accuracy is required when pasting,
Although they are stacked using positioning pins, etc., the density of conductor chips, etc. and printed circuit boards has increased, and more stringent positioning accuracy has been required, and the required positioning accuracy cannot be obtained, and the yield is decreasing. .

【0010】本発明は、上記従来の多層プリント基板の
ボンディング用棚形成方法がもつ問題点を解決しようと
するものである。即ち本発明の目的は、多段のワイヤー
ボンディング棚を有するプリント基板を容易に製造可能
とし、半導体チップ等を搭載するプリント基板を高精度
・低コストで製造できるようにし、もって多段ボンディ
ング用棚を有するピングリッドアレイ用プリント基板
や、ボールグリッドアレイ用プリント基板をも高精度・
低コストで製造できるようにすることにある。
The present invention is intended to solve the problems of the conventional method for forming a shelf for bonding a multilayer printed circuit board. That is, an object of the present invention is to make it possible to easily manufacture a printed circuit board having multi-stage wire bonding shelves and to manufacture a printed circuit board on which semiconductor chips and the like are mounted with high precision and low cost, and thus to have a multi-stage bonding shelf. High precision for pin grid array printed boards and ball grid array printed boards.
It is to be able to manufacture at low cost.

【0011】[0011]

【課題を解決するための手段】本発明に係る多層プリン
ト基板のボンディング用棚形成方法は、内部に回路7─
を形成した多層プリント基板において、多層構造の内部
に予めボンディング用端子15─を形成しておき、その
後に内層2─の端子15─の上部にある樹脂層8─を除
去し開口することにより、端子15─が露出したボンデ
ィング用棚12─を形成するようにしたものである。
A method for forming a shelf for bonding a multilayer printed circuit board according to the present invention includes a circuit 7-
In the multi-layer printed circuit board on which the bonding layer 15 is formed, the bonding terminals 15- are formed in advance inside the multilayer structure, and then the resin layer 8- on the terminals 15- of the inner layer 2- is removed and opened. The bonding rack 12 is formed so that the terminal 15 is exposed.

【0012】上記構成において、多層は図示実施例の3
層構造に限らず、2層でも4層以上としてもよい。また
多層化は、基板1上に順次各層2─を形成し積層しても
よいし(ビルドアップ法)、あるいはプリプレグ等を用
いて従来の多層板の形成法により予め積層形成してもよ
い。
In the above structure, the multi-layer structure is the same as that of the illustrated embodiment.
The layer structure is not limited to two and may be four or more. Further, in the case of forming a multilayer, the layers 2 may be sequentially formed and laminated on the substrate 1 (build-up method), or may be previously laminated by a conventional method for forming a multilayer board using a prepreg or the like.

【0013】内層2の樹脂層8─は後の除去を容易にす
るため、ガラス繊維を含まず有機繊維を含む繊維−樹脂
複合体とすることが望ましい。しかしこれに限らず、各
種熱硬化性・熱可塑性の樹脂の単体又は複合体を用いた
ものでも良く、フィルム状やシート状としてもよい。さ
らにこれらの樹脂には、後の除去工程に支承のない程度
で、無機質の充填材を含むことができる。
The resin layer 8-of the inner layer 2 is preferably a fiber-resin composite containing organic fibers instead of glass fibers in order to facilitate later removal. However, the present invention is not limited to this, and a simple substance or a composite of various thermosetting / thermoplastic resins may be used, and a film or sheet may be used. Further, these resins may contain an inorganic filler to the extent that they are unsupported in the subsequent removal step.

【0014】樹脂層8─の形成は、例えば樹脂の塗付・
積層・コーティング・貼り合わせ等によればよい。積層
の場合の回路7─の形成は、上面へ銅箔を同時に積層す
ればよいが、他の場合は後のメッキや貼り付けによって
導通層を形成してもよい。
The resin layer 8-is formed, for example, by applying resin.
Lamination, coating, laminating and the like may be used. In the case of stacking, the circuit 7- may be formed by simultaneously stacking a copper foil on the upper surface, but in other cases, the conductive layer may be formed by subsequent plating or pasting.

【0015】多層化後に内層2─のボンディング端子1
5─の上部の樹脂層8─を除去し、相対位置のボンディ
ング端子15─との間に開口10─を形成するするが、
この樹脂層8─の除去・開口方法は、例えば機械加工、
化学エッチング、レーザー加工あるいはプラズマ加工等
で行えばよい。基板1にも開口を設ける場合は、その一
部を上記方法によって除去してもよいが、それほど精度
を要求されないので、切削やパンチング加工で行っても
よい。
Bonding terminal 1 of inner layer 2 after multi-layering
The resin layer 8-on the upper part of 5- is removed and an opening 10-is formed between it and the bonding terminal 15-in the relative position.
The method of removing and opening the resin layer 8-is, for example, by machining or
It may be performed by chemical etching, laser processing, plasma processing, or the like. When the substrate 1 is also provided with the opening, a part thereof may be removed by the above-mentioned method, but cutting or punching may be carried out since accuracy is not so required.

【0016】ボンディング端子15─の上部の樹脂層8
─を除去し開口10─が形成されることで、該ボンディ
ング端子15が露出したボンディング用棚12─が形成
される。
The resin layer 8 above the bonding terminal 15
Is removed and an opening 10 is formed to form a bonding shelf 12 with the bonding terminal 15 exposed.

【0017】図において、4は基板1の基材で、5はそ
の上面の回路、6は内層2の樹脂層で、7はその上面の
回路、8は上層3の樹脂層を示す。9はその上面の銅箔
で、後に回路やボンディング端子16が形成されるもの
を示すが、樹脂の除去をエッチング等で行う場合は、除
去が完了するまでの間、これは銅箔のまま残され、マス
キング材として使用することができる。この場合には、
ボンディング用棚7や最下段の銅箔5は、エッチングが
それより下へ行かぬためのマスクング材ともなる。レー
ザーやプラズマ加工でエッチングするする場合にその作
用が著しい。また、これらの棚を形成すべく樹脂を取り
除いた後、ボンディング用棚等の仕上げのため、金メッ
キ等を施せばよい。10,11は樹脂層8─を除去して
生じる開口を示す。なお最下段の開口は後に半導体チッ
プ13等を搭載するキャビティ部とすることができ、こ
のため最後にパンチング等で開口してもよい。
In the figure, 4 is a base material of the substrate 1, 5 is a circuit on its upper surface, 6 is a resin layer of the inner layer 2, 7 is a circuit on its upper surface, and 8 is a resin layer of the upper layer 3. Reference numeral 9 denotes a copper foil on the upper surface of which the circuit and the bonding terminal 16 will be formed later. However, when the resin is removed by etching or the like, this is left as the copper foil until the removal is completed. And can be used as a masking material. In this case,
The bonding shelf 7 and the lowermost copper foil 5 also serve as a masking material for preventing etching below. The effect is remarkable when etching by laser or plasma processing. Further, after removing the resin to form these shelves, gold plating or the like may be applied to finish the shelves for bonding or the like. Reference numerals 10 and 11 denote openings formed by removing the resin layer 8-. The lowermost opening can be used as a cavity for mounting the semiconductor chip 13 or the like later. Therefore, the opening may be finally formed by punching or the like.

【0018】[0018]

【作用】本発明に係る多層プリント基板のボンディング
用棚形成方法は、上記の如く内部に回路7─を形成した
多層プリント基板において、多層構造の内部に予めボン
ディング用端子15─を形成しておき、その後に内層2
の端子15─の上部にある樹脂層8─を除去して開口す
ることにより、端子15─が露出したボンディング用棚
12─を形成するようにしたものである。
According to the method for forming a bonding shelf for a multilayer printed circuit board according to the present invention, in the multilayer printed circuit board having the circuit 7 formed therein as described above, the bonding terminal 15 is previously formed inside the multilayer structure. , Then inner layer 2
The resin layer 8-on the terminal 15-is removed and opened to form a bonding shelf 12-exposed of the terminal 15-.

【0019】そのため、従来のものが予め透孔を形成し
た各層を、プリプレグや接着シートを間に加熱・加圧し
て積層化するのと異なり、樹脂が各段部で開口10─側
へ滲み出して、ボンディング端子15─の接触不良を生
じるようなことが無くなる。
Therefore, unlike the prior art in which each layer in which through holes are previously formed is laminated by heating and pressurizing a prepreg or an adhesive sheet therebetween, the resin exudes to the opening 10-side at each step. As a result, contact failure of the bonding terminal 15 can be prevented.

【0020】また、従来のように樹脂の滲み出しを避け
るため圧着時の圧力を下げる必要もないので、樹脂はフ
ローが充分に行われ各回路5,7─を埋めるだけ充分に
行き渡り、品質上・信頼性の高いものが得られる。
Further, unlike the conventional case, it is not necessary to lower the pressure at the time of crimping in order to avoid resin exudation, so that the resin is sufficiently flowed to fill each circuit 5, 7-, and the quality is improved.・ Highly reliable products can be obtained.

【0021】更に、従来の回路や開口を予め形成し基材
等を積層・多層化するのと異なり、内層2─のボンディ
ング端子15の上部の部脂層8─を除去して開口10─
を形成するため、積層・多層化時の位置決め・位置精度
で苦労する必要が無くなり、製造が容易で歩留りも向上
し、コスト低減をもたらしている。
Further, unlike the conventional method of forming a circuit and an opening in advance and laminating and laminating a base material and the like, the part-fat layer 8-above the bonding terminal 15 of the inner layer 2-is removed to form the opening 10-.
Since it is formed, there is no need to worry about positioning / positioning accuracy when stacking / multilayering, manufacturing is easy, yield is improved, and cost is reduced.

【0022】なお、樹脂層8─として、上記の如く有機
繊維を含む繊維−樹脂複合体を用いるのが望ましいが、
有機繊維としてアラミド繊維を用いた場合には、樹脂と
の接着性がより良くなる。特にポリパラフェニレンオキ
シジフェニルエーテルアミド繊維を用いた場合には、高
純度でかつ樹脂との接着性が一層優れたものが形成され
る。
Although it is desirable to use a fiber-resin composite containing organic fibers as the resin layer 8-,
When aramid fiber is used as the organic fiber, the adhesiveness with the resin is improved. In particular, when polyparaphenylene oxydiphenyl ether amide fiber is used, a product having high purity and further excellent adhesiveness with a resin is formed.

【0023】樹脂層8─を除去・開口するには、上記の
如く例えば機械加工、化学エッチング、レーザー加工あ
るいはプラズマ加工等を用いればよいが、化学エッチン
グ、レーザー加工あるいはプラズマ加工なら高精度に開
口10─が形成される。特にレーザー加工として、エキ
シマレーザーや、炭酸ガスレーザーの中でもインパクト
レーザーと称される高エネルギーレーザーを用いた場合
は、開口10─の加工深さの制御が容易となり、壁面の
損傷も少なく一層高精度に仕上がる。
In order to remove and open the resin layer 8-, for example, mechanical processing, chemical etching, laser processing or plasma processing may be used as described above, but chemical etching, laser processing or plasma processing can be performed with high precision. 10- are formed. In particular, when a high energy laser called an impact laser among carbon dioxide lasers is used as the laser processing, it is easy to control the processing depth of the opening 10-, and the wall surface is less damaged and the accuracy is higher. Is finished.

【0024】[0024]

【実施例】図1ないし図5は、上記本発明に係る多層プ
リント基板のボンディング用棚形成方法の実施例であ
り、基板1を含む3層構造のものを示している。
1 to 5 show an embodiment of a method for forming a shelf for bonding a multilayer printed board according to the present invention, which shows a three-layer structure including a board 1.

【0025】このプリント基板は、回路5付き基材4の
基板1と、樹脂層6に回路7およびボンディング端子1
5を形成された内層2と、同様に樹脂層8に後に回路や
ボンディング端子16が形成される上層3とからなり
(図1参照)、それらが積層・多層化されている(図2
参照)。上記の回路形成は、積層・多層化の前でなくそ
の後にパターンエッチングで形成してもよく、また通常
のサブトラクト法あるいはアディティブ法で行えばよい
が、後でメッキや貼り付けにより銅からなる導電層を形
成してもよい。
This printed circuit board comprises a substrate 1 having a base material 4 with a circuit 5, a resin layer 6, a circuit 7 and a bonding terminal 1.
5 and an upper layer 3 on which a circuit and a bonding terminal 16 are similarly formed later on the resin layer 8 (see FIG. 1), which are laminated / multi-layered (FIG. 2).
reference). The above-mentioned circuit formation may be performed by pattern etching not before lamination / multilayering but after it, and may be performed by an ordinary subtraction method or an additive method. You may form a layer.

【0026】上記内層2のボンディング端子15上部の
樹脂層8、即ち上層3の樹脂層8や、内層2の樹脂層6
は、ガラス繊維を含まず有機繊維を含む繊維−樹脂複合
体とすることが望ましい。有機繊維としてはアラミド繊
維、ポリベンツイミダゾール繊維、ポリエーテルエーテ
ルケトン繊維、あるいはポリエステル繊維等が使用でき
る。しかし、樹脂との接着性の良さからアラミド繊維が
望ましく、更に高純度と樹脂との接着性から、ポリパラ
フェニレンオキシジフェニルエーテルアミド繊維を用い
るのが最適である。
The resin layer 8 above the bonding terminal 15 of the inner layer 2, that is, the resin layer 8 of the upper layer 3 and the resin layer 6 of the inner layer 2.
Is preferably a fiber-resin composite containing organic fibers without glass fibers. As the organic fiber, aramid fiber, polybenzimidazole fiber, polyetheretherketone fiber, polyester fiber or the like can be used. However, aramid fiber is desirable because of its good adhesiveness to resin, and it is optimal to use polyparaphenyleneoxydiphenyletheramide fiber because of its high purity and adhesiveness to resin.

【0027】また該樹脂層8,6は、上記と異なり繊維
を含まぬ構造で、例えばフィルム状やシート状のものと
してもよく、各種の熱硬化性樹脂、熱可塑性樹脂の単
体、あるいはそれらの複合体としたものでもよい。この
場合の樹脂の組成としては、例えばエポキシ樹脂、ポリ
イミド樹脂あるいはポリシラン樹脂等を用いればよい。
Further, unlike the above, the resin layers 8 and 6 have a structure not containing fibers, and may be, for example, in the form of a film or a sheet, and various thermosetting resins or thermoplastic resins alone, or a combination thereof. It may be a complex. As the resin composition in this case, for example, an epoxy resin, a polyimide resin, a polysilane resin, or the like may be used.

【0028】上記の如く積層・多層化した後に、内層2
のボンディング端子15上部の樹脂層8─を除去し開口
する。ここでは、続いて内層2の樹脂層6も、該ボンデ
ィング端子15より中央寄り部分を除去して開口する。
この場合に上段の層の樹脂層ほど大きい面積で除去・開
口し、上・下の開口11,10の周辺部が階段状に形成
しておく。なお内層2の樹脂層6の除去で生じた開口1
0は、後にここでは半導体チップ等13を搭載するキャ
ビティ部になる。
After laminating / multilayering as described above, the inner layer 2
The resin layer 8-above the bonding terminal 15 is removed and opened. Here, subsequently, the resin layer 6 of the inner layer 2 is also opened by removing the central portion from the bonding terminal 15.
In this case, the resin layer in the upper layer is removed and opened in a larger area, and the peripheral portions of the upper and lower openings 11 and 10 are formed in a staircase shape. The opening 1 formed by removing the resin layer 6 of the inner layer 2
0 will be a cavity portion in which a semiconductor chip or the like 13 will be mounted later.

【0029】上記樹脂層8,6の除去し開口する手段
は、例えば切削やパンチング等の機械加工、化学エッチ
ング、あるいはレーザー加工やプラズマ加工で行うこと
ができるが、化学エッチングやレーザー加工あるいはプ
ラズマ加工等によれば、精度の高い加工を行える。レー
ザー加工としては、エキシマレーザー、YAG(イット
リウム・アルミニウム・ガーネット)レーザー、炭酸ガ
スレーザー等が用いられるが、特に加工深さの制御や壁
面の損傷を小さくする上から、エキシマレーザーまたは
炭酸ガスレーザーでインパクトレーザーと称される高エ
ネルギーレーザーを用いるのが最適である。この場合
も、化学エッチングと同様に通常のマスキング法を採用
して行うのがよい。
The means for removing and opening the resin layers 8 and 6 may be mechanical processing such as cutting or punching, chemical etching, laser processing or plasma processing, and chemical etching, laser processing or plasma processing. According to the above, highly accurate processing can be performed. As the laser processing, an excimer laser, a YAG (yttrium aluminum garnet) laser, a carbon dioxide gas laser or the like is used. In particular, an excimer laser or a carbon dioxide gas laser is used in order to control the processing depth and reduce the damage on the wall surface. It is best to use a high energy laser called an impact laser. Also in this case, it is preferable to adopt an ordinary masking method similarly to the chemical etching.

【0030】上記内層2のボンディング端子15上部の
樹脂層8の除去・開口により、内層2のボンディング端
子15が露出したボンディング用12が形成されること
になり、ボンディング用棚付きの多層プリント基板が形
成される。その後は、上層3の銅箔9にも回路およびボ
ンディング端子16を形成するとともに、図6で示す如
く、半導体チップ等13を搭載し、露出したボンディン
グ用端子15,16と、半導体チップ等13の端子部と
の間でワイヤー17によるボンディングをし、封止樹脂
18を充填すればよい。
By removing and opening the resin layer 8 above the bonding terminal 15 of the inner layer 2, the bonding terminal 12 with the bonding terminal 15 of the inner layer 2 exposed is formed, and a multilayer printed board with a shelf for bonding is formed. It is formed. After that, the circuit and the bonding terminal 16 are formed also on the copper foil 9 of the upper layer 3, and as shown in FIG. 6, the semiconductor chip or the like 13 is mounted and the exposed bonding terminals 15 and 16 and the semiconductor chip or the like 13 are formed. Bonding with the wire 17 may be performed between the terminals and the sealing resin 18 may be filled.

【0031】次に、図6ないし図8は、上記本発明に係
る多層プリント基板のボンディング用棚形成方法を応用
した実施例を示す。ここでも、基板を含めると3層構造
になるもので説明する。
Next, FIGS. 6 to 8 show an embodiment to which the method for forming a shelf for bonding a multilayer printed circuit board according to the present invention is applied. In this case as well, description will be made assuming that a three-layer structure is formed when the substrate is included.

【0032】ここで用いる多層プリント基板も、上記本
発明の第1で説明したのと同様のもので、回路5付き基
材4の基板1と、樹脂層6に回路7およびボンディング
端子15を形成された内層2と、同様に樹脂層8に後に
回路やボンディング端子16が形成される上層3とから
なり、それらが積層・多層化したものである(上記図1
・図2参照)。
The multilayer printed circuit board used here is also the same as that described in the first embodiment of the present invention. The circuit board 5 with the circuit 5 and the circuit board 7 and the bonding terminals 15 are formed on the resin layer 6. The inner layer 2 and the upper layer 3 on which the circuit and the bonding terminals 16 are to be formed later on the resin layer 8 are laminated and formed into a multilayer structure (see FIG. 1 above).
-See Figure 2.)

【0033】この場合も、上記の如く積層・多層化した
後に、内層2のボンディング端子15上部の樹脂層8を
除去し開口11を形成することで、内層2のボンディン
グ端子15が露出したボンディング用棚12が形成され
る。この樹脂層8を除去・開口する手段は上記と同様で
よい。ここでは続いて、内層2の樹脂層6をそのボンデ
ィング端子15より中央寄り部分で除去し、開口10を
形成するとともに、更に基板1に内層2の開口10より
やや小さい開口19を形成する(図6参照)。
Also in this case, after the above-mentioned lamination / multi-layering, the resin layer 8 above the bonding terminal 15 of the inner layer 2 is removed and the opening 11 is formed, so that the bonding terminal 15 of the inner layer 2 is exposed. The shelf 12 is formed. The means for removing and opening the resin layer 8 may be the same as described above. Here, subsequently, the resin layer 6 of the inner layer 2 is removed at a portion closer to the center than the bonding terminal 15 to form an opening 10, and further an opening 19 slightly smaller than the opening 10 of the inner layer 2 is formed in the substrate 1 (see FIG. 6).

【0034】上記樹脂層8,6の除去・開口は、先の実
施例で示したのと同様の手段で行えばよいが、基板1に
開口19を形成するには、上記ほどの精度は要求されな
いので、切削やパンチング等の機械加工でもよい。上記
開口10,11,19の周辺部は階段状に形成されてお
り、最下段の開口19は後に半導体チップ等13を搭載
するキャビティ部になる。
The removal and opening of the resin layers 8 and 6 may be carried out by the same means as shown in the previous embodiment, but the above accuracy is required to form the opening 19 in the substrate 1. Since it is not performed, machining such as cutting or punching may be performed. The peripheries of the openings 10, 11, and 19 are formed in a staircase shape, and the opening 19 at the lowermost stage becomes a cavity portion in which the semiconductor chip or the like 13 is mounted later.

【0035】その後、上層3の銅箔9に回路とボンディ
ング端子16、基板1にボンディング端子22を各々形
成するとともに、基板1の裏面から他の基材、例えば有
機材製、セラミック製あるいは金属製等の基材を貼り付
ける。ここでは放熱性のよい銅合金板14を貼り付けて
ある(図7参照)。
After that, the circuit and the bonding terminals 16 are formed on the copper foil 9 of the upper layer 3, and the bonding terminals 22 are formed on the substrate 1, respectively, and from the rear surface of the substrate 1, another substrate such as an organic material, a ceramic material or a metal material is formed. Stick a base material such as. Here, a copper alloy plate 14 having good heat dissipation is attached (see FIG. 7).

【0036】そして上記基板1の開口19内で銅合金板
14上に、半導体チップ等13が搭載し、上記と同様に
各ボンディング端子15,16,20と半導体チップ等
13の端子部とをワイヤーボンディングした後、半導体
チップ等13の周辺を封止樹脂18で充填する。さら
に、上層3に半田パッドに半田ボール21を装着して、
キャビティダウンボールグリッドアレイが形成される。
Then, the semiconductor chip 13 or the like is mounted on the copper alloy plate 14 in the opening 19 of the substrate 1, and each bonding terminal 15, 16, 20 and the terminal portion of the semiconductor chip 13 or the like are wire-connected in the same manner as described above. After the bonding, the periphery of the semiconductor chip 13 is filled with the sealing resin 18. Further, by mounting the solder ball 21 on the solder pad on the upper layer 3,
A cavity down ball grid array is formed.

【0037】[0037]

【発明の効果】以上で明らかなように、本発明に係る多
層プリント基板のボンディング用棚形成方法は、ボンデ
ィング棚付のプリント基板を容易・高精度・低コストに
製造できるようになり、その結果それを用いたピングリ
ッドアレイ用プリント基板・ボールグリッドアレイ用プ
リント基板等を容易・高精度・低コストに製造できるよ
うになる。
As is apparent from the above, the method for forming a bonding shelf for a multilayer printed circuit board according to the present invention allows a printed circuit board with a bonding shelf to be manufactured easily, with high precision and at low cost. A printed circuit board for a pin grid array, a printed circuit board for a ball grid array, etc. using the same can be manufactured easily, with high accuracy, and at low cost.

【0038】即ち、従来のこの種のプリント基板の製造
方法では、予め透孔を設けた基板をプリプレグや熱硬化
性接着シートで高熱・圧着していたため、その際の樹脂
の滲み出して、ボンディング用棚のボンディング端子の
接触不良となったり、樹脂の滲み出しはないが、樹脂の
フローが不十分で回路間を埋めきれず、品質上・信頼性
に問題が生じたり、予め回路や透孔を形成した基板を積
層・多層化するので、半導体チップ等やプリント基板が
高密度化すると、必要な位置精度を得られず歩留りが低
下したりした。
That is, in the conventional method for manufacturing a printed circuit board of this type, since the board having the through holes is previously heated and pressure-bonded with the prepreg or the thermosetting adhesive sheet, the resin oozes out at the time of bonding. There is no contact between the bonding terminals on the shelf and there is no resin bleeding out, but the resin flow is not enough to fill the spaces between the circuits, which causes problems in quality and reliability. Since the substrates on which the layers are formed are laminated / multi-layered, if the density of semiconductor chips or printed boards is increased, the required positional accuracy cannot be obtained and the yield is reduced.

【0039】これに対して、本発明に係る多層プリント
基板のボンディング用棚形成方法では、多層構造の内部
に予めボンディング用端子を形成しておき、その後に内
層の端子の上部にある樹脂層を除去し開口することによ
り、端子が露出したボンディング用棚を形成するもので
ある。
On the other hand, in the method for forming a bonding shelf for a multilayer printed circuit board according to the present invention, bonding terminals are formed in advance inside the multilayer structure, and then the resin layer on the inner terminals is formed. By removing and opening, a bonding shelf with exposed terminals is formed.

【0040】そのため、従来のものとことなり、積層・
多層化時に樹脂が各段部で開口側へ滲み出したり、ボン
ディング端子が接触不良を生じたなするようなことを無
くすことができる。
Therefore, unlike conventional ones,
It is possible to prevent the resin from bleeding out to the opening side at each step and the bonding terminal from causing a contact failure at the time of multilayering.

【0041】また、従来のように樹脂の滲み出しを避け
るため圧着時の圧力を下げる必要もないので、樹脂のフ
ローは充分に行われて各回路間を埋めることができ、品
質上・信頼性の高いものを得ることができる。
Further, unlike the conventional case, there is no need to reduce the pressure at the time of crimping in order to avoid resin exudation, so that the flow of resin can be sufficiently carried out to fill the spaces between the circuits, and in terms of quality and reliability. You can get the high one.

【0042】更に、従来の予め回路や透孔を形成したも
のを積層・多層化するのと異なり、積層後に回路を形成
し、多層化後に樹脂を除去して開口を形成するので、積
層・多層化時の位置決め・位置精度で苦労することが無
くなり、製造が容易で歩留りも向上し、コストを低減す
ることができる。
Further, unlike the conventional method in which a circuit or through holes are previously formed and laminated, the circuit is formed after the lamination, and the resin is removed to form the opening after the lamination, so that the lamination / multilayer is formed. There is no difficulty in positioning and positioning accuracy at the time of production, manufacturing is easy, yield is improved, and cost can be reduced.

【0043】なお、樹脂層として有機繊維を含む繊維−
樹脂複合体、特に有機繊維としてアラミド繊維を用いた
場合には、樹脂との接着性が良いものになる。更にポリ
パラフェニレンオキシジフェニルエーテルアミド繊維を
用いた場合には、高純度でかつ樹脂との接着性が一層優
れた高品質なプリント基板が形成できる。
Fibers containing organic fibers as the resin layer
When aramid fiber is used as the resin composite, especially as the organic fiber, the adhesiveness with the resin becomes good. Further, when polyparaphenylene oxydiphenyl ether amide fiber is used, a high quality printed circuit board having high purity and further excellent adhesiveness with a resin can be formed.

【0044】また積層・多層化後の樹脂の除去に、化学
エッチング、レーザー加工あるいはプラズマ加工等を用
いた場合にば、高精度に開口が形成できる。特にレーザ
ー加工として、エキシマレーザーや炭酸ガスレーザーの
内、インパクトレーザーと称される高エネルギーレーザ
ーを用いた場合にば、加工深さや開口の壁面等が一層高
精度に仕上げることができる。
If chemical etching, laser processing, plasma processing, or the like is used to remove the resin after laminating / multilayering, the opening can be formed with high precision. In particular, when a high-energy laser called an impact laser among excimer lasers and carbon dioxide lasers is used as the laser processing, the processing depth and the wall surface of the opening can be finished with higher accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例で用いた多層プリント基板の一
部の分解拡大縦断面図である。
FIG. 1 is an exploded enlarged vertical sectional view of a part of a multilayer printed circuit board used in an embodiment of the present invention.

【図2】図1で示した多層プリント基板の拡大縦断面図
である。
FIG. 2 is an enlarged vertical sectional view of the multilayer printed circuit board shown in FIG.

【図3】内層のボンディング端子上部の樹脂層を除去し
開口した状態の拡大縦断面図である。
FIG. 3 is an enlarged vertical cross-sectional view showing a state in which a resin layer above an inner layer bonding terminal is removed and opened.

【図4】内層のボンディング端子の中央寄り部分の樹脂
層を除去し開口した状態の拡大縦断面図である。
FIG. 4 is an enlarged vertical cross-sectional view showing a state in which a resin layer in a portion near a center of an inner layer bonding terminal is removed and opened.

【図5】図4で示したものに半導体チップを搭載し、ワ
イヤーボンディング後に樹脂封止した状態の拡大縦断面
図である。
5 is an enlarged vertical cross-sectional view showing a state in which a semiconductor chip is mounted on the structure shown in FIG. 4, and resin sealing is performed after wire bonding.

【図6】本発明を応用した実施例で、基板にも開口を設
けた状態の拡大縦断面図である。
FIG. 6 is an enlarged vertical cross-sectional view showing a state in which an opening is also provided in a substrate in an example to which the present invention is applied.

【図7】図6で示したものに他の基材を貼り付けた状態
の拡大縦断面図である。
FIG. 7 is an enlarged vertical sectional view showing a state in which another base material is attached to the one shown in FIG.

【図8】図7で示したものに半導体チップを搭載し、ワ
イヤーボンディング後に樹脂封止し、ハンダボールを装
着した状態の拡大縦断面図である。
8 is an enlarged vertical cross-sectional view showing a state in which a semiconductor chip is mounted on the structure shown in FIG. 7, resin bonding is performed after wire bonding, and solder balls are mounted.

【図9】従来手段で用いる基板の一部の拡大縦断面図で
ある。
FIG. 9 is an enlarged vertical sectional view of a part of a substrate used in conventional means.

【図10】従来手段で用いる内層としての基材の一部の
拡大縦断面図である。
FIG. 10 is an enlarged vertical sectional view of a part of a base material as an inner layer used in a conventional means.

【図11】図1で示した基板に、図2で示した内層を貼
り付けた状態の拡大縦断面図である。
11 is an enlarged vertical cross-sectional view of a state in which the inner layer shown in FIG. 2 is attached to the substrate shown in FIG.

【図12】従来手段で用いる上層としての基材の一部の
拡大縦断面図である。
FIG. 12 is an enlarged vertical sectional view of a part of a base material as an upper layer used in the conventional means.

【図13】図11で示したものに図12で示した外層を
貼り付けた状態の拡大縦断面図である。
13 is an enlarged vertical cross-sectional view of the state shown in FIG. 11 to which the outer layer shown in FIG. 12 is attached.

【符号の説明】[Explanation of symbols]

1−基板 11−開口 21−
半田ボール 2−内層 12−ボンディング用棚 3−上層 13−半導体チップ等 4−基材 14−基材 5−回路 15−ボンディング端子 6−樹脂層 16−ボンディング端子 7−回路 17−ワイヤー 8−樹脂層 18−封止樹脂 9−銅箔 19−開口 10−開口 20−ボンディング端子
1-Substrate 11-Opening 21-
Solder ball 2-Inner layer 12-Shelving for bonding 3-Upper layer 13-Semiconductor chip etc. 4-Base material 14-Base material 5-Circuit 15-Bonding terminal 6-Resin layer 16-Bonding terminal 7-Circuit 17-Wire 8-Resin Layer 18-Sealing resin 9-Copper foil 19-Opening 10-Opening 20-Bonding terminal

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】内部に回路を形成した多層プリント基板に
おいて、多層構造の内部に予めボンディング用端子を形
成しておき、その後に内層の端子の上部にある樹脂層を
除去し開口することにより、端子が露出したボンディン
グ用棚を形成することを特徴とする、多層プリント基板
のボンディング用棚形成方法。
1. In a multilayer printed circuit board having a circuit formed therein, a bonding terminal is previously formed inside the multilayer structure, and thereafter, a resin layer on the upper terminal of the inner layer is removed and an opening is formed. A method for forming a bonding shelf for a multi-layer printed circuit board, which comprises forming a bonding shelf for which terminals are exposed.
【請求項2】内層の樹脂層が有機繊維を含むようにし
た、請求項1に記載の多層プリント基板のボンディング
用棚形成方法。
2. The method for forming a shelf for bonding a multilayer printed circuit board according to claim 1, wherein the resin layer of the inner layer contains an organic fiber.
【請求項3】樹脂層がアラミド繊維を含むようにした、
請求項1,2に記載の多層プリント基板のボンディング
用棚形成方法。
3. The resin layer contains aramid fibers,
The method for forming a shelf for bonding a multilayer printed circuit board according to claim 1, 2.
【請求項4】樹脂層がフィルムまたはシートからなる、
請求項1に記載の多層プリント基板のボンディング用棚
形成方法。
4. The resin layer comprises a film or sheet,
The method for forming a shelf for bonding a multilayer printed circuit board according to claim 1.
【請求項5】内層の樹脂層の除去を、化学エッチングで
行うようにした、請求項1に記載の多層プリント基板の
ボンディング用棚形成方法。
5. The method for forming a shelf for bonding a multilayer printed board according to claim 1, wherein the resin layer of the inner layer is removed by chemical etching.
【請求項6】内層の樹脂層の除去を、レーザー加工で行
うようにした、請求項1に記載の多層プリント基板のボ
ンディング用棚形成方法。
6. The method for forming a shelf for bonding a multilayer printed circuit board according to claim 1, wherein the resin layer of the inner layer is removed by laser processing.
【請求項7】内層の樹脂層の除去を、プラズマ加工で行
うようにした、請求項1に記載の多層プリント基板のボ
ンディング用棚形成方法。
7. The method for forming a shelf for bonding a multilayer printed circuit board according to claim 1, wherein the resin layer of the inner layer is removed by plasma processing.
JP7171391A 1995-06-14 1995-06-14 Shelf formation method and bonding of multilayer printed-circuit board Pending JPH098175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7171391A JPH098175A (en) 1995-06-14 1995-06-14 Shelf formation method and bonding of multilayer printed-circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7171391A JPH098175A (en) 1995-06-14 1995-06-14 Shelf formation method and bonding of multilayer printed-circuit board

Publications (1)

Publication Number Publication Date
JPH098175A true JPH098175A (en) 1997-01-10

Family

ID=15922299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7171391A Pending JPH098175A (en) 1995-06-14 1995-06-14 Shelf formation method and bonding of multilayer printed-circuit board

Country Status (1)

Country Link
JP (1) JPH098175A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368368A (en) * 2001-06-04 2002-12-20 Hitachi Chem Co Ltd Connection board, multilayered wiring board using the same, semiconductor package board, semiconductor package, method of manufacturing connection board, method of manufacturing multilayer wiring board therethrough, method of manufacturing semiconductor package board, and method of manufacturing semiconductor package
JP2004152883A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Capacitor element, its manufacturing method, semiconductor device, and substrate therefor
JP2004152884A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Semiconductor device, substrate therefor and its manufacturing method
EP1635625A3 (en) * 2004-09-10 2007-07-25 Fujitsu Limited Substrate manufacturing method and circuit board
JP2007266195A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed-wiring board and manufacturing method therefor
JP2008034589A (en) * 2006-07-28 2008-02-14 Dainippon Printing Co Ltd Multilayer printed wiring board and manufacturing method thereof
JP2008306227A (en) * 2008-09-25 2008-12-18 Panasonic Electric Works Co Ltd Uneveness shaped multilayer circuit board module and method of manufacturing the same
JP2010074072A (en) * 2008-09-22 2010-04-02 Nec Corp Semiconductor device and method of manufacturing semiconductor device
JP2011191079A (en) * 2010-03-12 2011-09-29 Hitachi Automotive Systems Ltd Angular rate sensor
JP2013070009A (en) * 2011-09-23 2013-04-18 Samsung Electro-Mechanics Co Ltd Printed circuit board and method for manufacturing the same
JP2019121626A (en) * 2017-12-28 2019-07-22 京セラ株式会社 Method for manufacturing printed-circuit board
CN110739223A (en) * 2018-07-18 2020-01-31 迪睿合株式会社 Method for manufacturing thermally conductive sheet
WO2023149144A1 (en) * 2022-02-02 2023-08-10 日立Astemo株式会社 Semiconductor device

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JPH02206196A (en) * 1989-01-11 1990-08-15 Trw Inc Multilarger printed circuit board
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JPH06244528A (en) * 1993-02-19 1994-09-02 Toppan Printing Co Ltd Manufacture of printed-wiring board
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JPH06318668A (en) * 1993-05-07 1994-11-15 Shinko Electric Ind Co Ltd Multilayered circuit board
JPH06334067A (en) * 1993-05-18 1994-12-02 Cmk Corp Multilayer printed wiring board and production thereof

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Publication number Priority date Publication date Assignee Title
JPH02206196A (en) * 1989-01-11 1990-08-15 Trw Inc Multilarger printed circuit board
JPH04273151A (en) * 1991-02-27 1992-09-29 Sanyo Electric Co Ltd Manufacture of hybrid integrated circuit
JPH06244528A (en) * 1993-02-19 1994-09-02 Toppan Printing Co Ltd Manufacture of printed-wiring board
JPH06302716A (en) * 1993-04-13 1994-10-28 Toshiba Corp Multilayer board and detection of lamination misalignment of multilayer board
JPH06318668A (en) * 1993-05-07 1994-11-15 Shinko Electric Ind Co Ltd Multilayered circuit board
JPH06334067A (en) * 1993-05-18 1994-12-02 Cmk Corp Multilayer printed wiring board and production thereof

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368368A (en) * 2001-06-04 2002-12-20 Hitachi Chem Co Ltd Connection board, multilayered wiring board using the same, semiconductor package board, semiconductor package, method of manufacturing connection board, method of manufacturing multilayer wiring board therethrough, method of manufacturing semiconductor package board, and method of manufacturing semiconductor package
JP2004152883A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Capacitor element, its manufacturing method, semiconductor device, and substrate therefor
JP2004152884A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Semiconductor device, substrate therefor and its manufacturing method
US7223652B2 (en) 2002-10-29 2007-05-29 Shinko Electric Industries Co., Ltd. Capacitor and manufacturing method thereof, semiconductor device and substrate for a semiconductor device
EP1635625A3 (en) * 2004-09-10 2007-07-25 Fujitsu Limited Substrate manufacturing method and circuit board
US7301230B2 (en) 2004-09-10 2007-11-27 Fujitsu Limited Circuit board with a thin-film layer configured to accommodate a passive element
JP2007266195A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed-wiring board and manufacturing method therefor
US8400776B2 (en) 2006-07-28 2013-03-19 Dai Nippon Printing Co., Ltd. Multilayered printed wiring board
JP2008034589A (en) * 2006-07-28 2008-02-14 Dainippon Printing Co Ltd Multilayer printed wiring board and manufacturing method thereof
US8942003B2 (en) 2006-07-28 2015-01-27 Dai Nippon Printing Co., Ltd. Multilayered printed wiring board
KR101497689B1 (en) * 2006-07-28 2015-03-02 다이니폰 인사츠 가부시키가이샤 Multilayered printed wiring board and method for manufacturing the same
JP2010074072A (en) * 2008-09-22 2010-04-02 Nec Corp Semiconductor device and method of manufacturing semiconductor device
US8354298B2 (en) 2008-09-22 2013-01-15 Nec Corporation Semiconductor device and manufacturing method of a semiconductor device
JP2008306227A (en) * 2008-09-25 2008-12-18 Panasonic Electric Works Co Ltd Uneveness shaped multilayer circuit board module and method of manufacturing the same
JP2011191079A (en) * 2010-03-12 2011-09-29 Hitachi Automotive Systems Ltd Angular rate sensor
JP2013070009A (en) * 2011-09-23 2013-04-18 Samsung Electro-Mechanics Co Ltd Printed circuit board and method for manufacturing the same
JP2019121626A (en) * 2017-12-28 2019-07-22 京セラ株式会社 Method for manufacturing printed-circuit board
CN110739223A (en) * 2018-07-18 2020-01-31 迪睿合株式会社 Method for manufacturing thermally conductive sheet
WO2023149144A1 (en) * 2022-02-02 2023-08-10 日立Astemo株式会社 Semiconductor device

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