JPH06318668A - Multilayered circuit board - Google Patents
Multilayered circuit boardInfo
- Publication number
- JPH06318668A JPH06318668A JP5106808A JP10680893A JPH06318668A JP H06318668 A JPH06318668 A JP H06318668A JP 5106808 A JP5106808 A JP 5106808A JP 10680893 A JP10680893 A JP 10680893A JP H06318668 A JPH06318668 A JP H06318668A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit board
- films
- signal
- signal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層回路基板に関する。FIELD OF THE INVENTION This invention relates to multilayer circuit boards.
【０００２】[0002]
【従来の技術】信号層、電源プレーン、接地プレーンを
ポリイミド等の絶縁性フィルムを介在させて積層した多
層リードフレームが知られている。また半導体素子を搭
載するパッケージでは電気的特性に優れるセラミックパ
ッケージが知られている。2. Description of the Related Art A multilayer lead frame is known in which a signal layer, a power plane, and a ground plane are laminated with an insulating film such as polyimide interposed therebetween. Further, as a package for mounting a semiconductor element, a ceramic package having excellent electrical characteristics is known.
【０００３】[0003]
【発明が解決しようとする課題】前記多層リードフレー
ムでは、信号層と別に面積の大きな電源層と接地層をも
っているため、信号層に対してはストリップラインとし
てクロストークを抑えられるうえ、電源系に対してはイ
ンダクタンスが低いためバウンスと呼ばれる一種の電源
雑音を小さくできるメリットがある。しかしながら昨今
では、クロック周波数が数ＧＨｚ以上、あるいは立ち上
がり時間が１ｎｓ以下のデバイスが出現しており、この
ような超高速、超高周波数のデバイスに対しては、上記
多層のリードフレームであっても、信号の反射やロスに
より信号が通らず、またクロストークが大きくなって使
用できないという問題点がある。上記のように、クロッ
ク周波数が数ＧＨｚ以上という超高周波数のデバイスで
は、インピーダンスのマッチングがとれないと使用でき
ないが、基本的に、通常のリードフレームでは、インナ
ーリードとアウターリードの幅を同じくすることは強度
上の点で難点があり、インピーダンス制御（Ｚｏ＝５０
オーム）をすることは非常に難しい。またクロストーク
防止のための同軸構造をとることも構造上から極めて困
難である。このため、上記の超高速、超高周波数のデバ
イスでは、電気的特性に優れるセラミックパッケージを
用いるしかなかったが、セラミックパッケージでは高価
であると共に、メタライズ配線パターンによるため、多
ピン化に限界があるという問題点があった。Since the multi-layer lead frame has a power layer and a ground layer having a large area in addition to the signal layer, crosstalk can be suppressed as a strip line for the signal layer and the power system can be used. On the other hand, since the inductance is low, there is an advantage that a kind of power supply noise called bounce can be reduced. However, in recent years, devices with a clock frequency of several GHz or more or a rise time of 1 ns or less have appeared, and for such ultra-high speed and ultra-high frequency devices, even the above-mentioned multilayer lead frame is used. However, there is a problem that the signal cannot pass due to reflection or loss of the signal and the crosstalk becomes large, so that it cannot be used. As described above, an ultrahigh frequency device having a clock frequency of several GHz or more cannot be used unless impedance matching is obtained, but basically, in a normal lead frame, the inner lead and the outer lead have the same width. However, there is a difficulty in terms of strength, and impedance control (Zo = 50
It's very difficult to play. In addition, it is extremely difficult to take a coaxial structure to prevent crosstalk because of its structure. Therefore, in the above-mentioned ultra-high-speed and ultra-high-frequency devices, it was necessary to use a ceramic package having excellent electrical characteristics, but the ceramic package is expensive, and the metallized wiring pattern limits the number of pins. There was a problem.
【０００４】そこで、本発明は上記問題点を解決すべく
なされたものであり、その目的とするところは、比較的
安価に形成できると共に、多ピン化が可能であり、イン
ピーダンスのマッチングが容易に図れ、さらにクロスト
ークを抑えることができて超高速、超高周波数のデバイ
スを搭載可能となる多層回路基板を提供するにある。Therefore, the present invention has been made to solve the above problems, and the object thereof is to be formed at a relatively low cost, to be able to increase the number of pins, and to easily match impedances. Another object of the present invention is to provide a multi-layer circuit board capable of suppressing crosstalk and mounting an ultra-high speed and ultra-high frequency device.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、ビア付きフィル
ムが信号層を挟んで２層以上の多層に積層され、隣接す
る前記フィルム間の信号層を挾む両フィルムの前記ビア
が導通され、かつ該両フィルムの他面に形成された接地
層に前記ビアが接続されて、前記信号層を囲む断面矩形
の擬似同軸構造が形成されていることを特徴としてい
る。また、単層リードフレームと、該単層リードフレー
ムの、インナーリード側に積層され、搭載される半導体
素子と電気的に接続される端子部を有し、かつ前記単層
リードフレームのアウターリードに導通がとられる多層
回路基板とを具備し、該多層回路基板が、ビア付きフィ
ルムが信号層を挟んで２層以上の多層に積層され、隣接
する前記フィルム間の信号層を挾む両フィルムの前記ビ
アが導通され、かつ該両フィルムの他面に形成された接
地層に前記ビアが接続されて、前記信号層を囲む断面矩
形の擬似同軸構造が形成されている多層回路基板である
ことを特徴としている。前記多層回路基板の回路パター
ンを信号層と、電源層および／または接地層とで構成す
ると好適である。また本発明では、上面に回路パターン
が形成され、該回路パターンにアウターリードが接続さ
れたメタルコアパッケージと、該メタルコアパッケージ
の、半導体素子が搭載されるインナー側に積層され、前
記搭載される半導体素子と電気的に接続される端子部を
有し、かつメタルコアパッケージに導通がとられる多層
回路基板とを具備し、該多層回路基板が、ビア付きフィ
ルムが信号層を挟んで２層以上の多層に積層され、隣接
する前記フィルム間の信号層を挾む両フィルムの前記ビ
アが導通され、かつ該両フィルムの他面に形成された接
地層に前記ビアが接続されて、前記信号層を囲む断面矩
形の擬似同軸構造が形成されている多層回路基板である
ことを特徴としている。前記多層回路基板の回路パター
ンを信号層と、電源層および／または接地層とで構成す
ると好適である。The present invention has the following constitution in order to achieve the above object. That is, a film with a via is laminated in two or more layers sandwiching a signal layer, the vias of both films sandwiching the signal layer between adjacent films are electrically connected, and formed on the other surface of both films. The via is connected to the ground layer to form a pseudo-coaxial structure having a rectangular cross section surrounding the signal layer. Further, the single-layer lead frame has a terminal portion laminated on the inner lead side of the single-layer lead frame and electrically connected to a mounted semiconductor element, and the outer lead of the single-layer lead frame is provided. A multi-layer circuit board having electrical continuity, wherein the multi-layer circuit board is formed by laminating two or more layers of films with vias sandwiching a signal layer, and sandwiching a signal layer between adjacent films. A multilayer circuit board in which the via is electrically connected and the via is connected to a ground layer formed on the other surface of both films to form a pseudo-coaxial structure having a rectangular cross section surrounding the signal layer. It has a feature. It is preferable that the circuit pattern of the multilayer circuit board is configured by a signal layer and a power supply layer and / or a ground layer. Further, according to the present invention, a circuit pattern is formed on an upper surface, and a metal core package having outer leads connected to the circuit pattern and a semiconductor element mounted on the inner side of the metal core package on which a semiconductor element is mounted, A multi-layer circuit board having a terminal portion electrically connected to the metal core package and having electrical continuity in a metal core package. A cross section surrounding the signal layers, wherein the vias of both films laminated and sandwiching the signal layer between the adjacent films are conducted, and the vias are connected to a ground layer formed on the other surface of the both films. It is characterized by being a multilayer circuit board in which a rectangular pseudo-coaxial structure is formed. It is preferable that the circuit pattern of the multilayer circuit board is configured by a signal layer and a power supply layer and / or a ground layer.
【０００６】[0006]
【作用】本発明に係る多層回路基板によれば、比較的安
価に提供できると共に、インピーダンスのマッチングが
容易にとれ、さらに擬似同軸構造が形成できるのでクロ
ストークを効果的に抑えることができ、超高速、超高周
波数のデバイス用に用いることができる。The multilayer circuit board according to the present invention can be provided at a relatively low cost, impedance matching can be easily obtained, and a pseudo coaxial structure can be formed, so that crosstalk can be effectively suppressed. It can be used for high speed and ultra high frequency devices.
【０００７】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。図１は、本発明で基本的に用い
るビア付きフィルム１０を示す。このビア付きフィルム
１０は、熱可塑性のポリイミドフィルム１１にエキシマ
レーザー等により、微細なスルーホールを開口し、片面
に銅箔１２を加圧加熱することによって貼着し、電解銅
めっきを行って、スルーホール内の銅箔上に銅を盛り上
げ、スルーホール内に銅を充填してビア１３を形成す
る。ビア１３の上面はポリイミドフィルム１１上面側に
若干突出して形成される。熱可塑性のポリイミドフィル
ム１１は加熱することによって粘着性を帯び、複数枚重
ねて加熱、加圧することによって積層が可能となる。ス
ルーホールは最小５０μｍピッチ程度の微細なパターン
に形成でき、またスルーホールの孔径も数μｍのものが
可能なので、微細パターンのビア１３を形成できる。ま
た、ポリイミドフィルム１１は数１０〜数１００μｍの
ものが使用できる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a film 10 with a via basically used in the present invention. This via-equipped film 10 is formed by opening a fine through hole in a thermoplastic polyimide film 11 with an excimer laser or the like, and pressing and heating a copper foil 12 on one surface to perform electrolytic copper plating, Copper is piled up on the copper foil in the through hole and filled in the through hole to form the via 13. The upper surface of the via 13 is formed so as to slightly project to the upper surface side of the polyimide film 11. The thermoplastic polyimide film 11 becomes tacky when heated, and can be laminated by stacking and heating a plurality of sheets. Since the through holes can be formed in a fine pattern with a minimum pitch of about 50 μm, and the hole diameter of the through holes can be several μm, the vias 13 with a fine pattern can be formed. The polyimide film 11 having a thickness of several tens to several hundreds of μm can be used.
【０００８】図２は他面に回路パターンを形成したビア
付きフィルム１０を示す。このビア付きフィルム１０
は、上記のようにビア１３を形成したポリイミドフィル
ム１１の他面側に銅箔を貼着し、この銅箔をエッチング
加工して回路パターン（信号層）１４を形成したもので
ある。図３は多層回路基板１６を示し、図１、図２に示
すビア付きフィルム１０、１０のビア１３、１３が互い
に当接するようにして重ね合わせ、加熱、加圧して２層
の回路基板に形成されている。ビア付きフィルム１０、
１０を上記のようにして重ね合わせ、加熱、加圧する
と、熱可塑性のポリイミドフィルム１１が軟化し、上下
のビア付きフィルム１０に形成したビア１３、１３が確
実に当接した状態で、かつ信号層１４がポリイミドフィ
ルム１１中に埋没した状態にて接合される。上下のビア
１３、１３は単に当接している状態であるが、ポリイミ
ドフィルム１１、１１の熱収縮が加わることから強固に
当接し、電気的導通が確実に確保される。図３から明ら
かなように、両ビア付きフィルム１０、１０間の信号層
１４はビア１３によって両側から挟まれ、また上下を銅
箔１２、１２によって挟まれた構造となる。銅箔１２、
１２を接地層に設定すれば、信号層１４はビア１３と銅
箔１２による断面矩形の擬似同軸構造となり、クロスト
ークを防止できる構造となる。また、信号層１４の幅、
ポリイミドフィルム１１の厚さ、ビア１３のピッチを調
整することにより、インピーダンス（Ｚｏ＝５０オー
ム）のマッチングを容易にとることができる。上記実施
例では、２層の回路基板に形成したが、３層以上の多層
の回路基板に形成することもできる。この場合信号層の
みならず電源層や接地層等を形成することによりより電
気的特性に優れる多層回路基板に構成できる。FIG. 2 shows a film 10 with a via having a circuit pattern formed on the other surface. This film with via 10
Is obtained by adhering a copper foil to the other surface of the polyimide film 11 in which the vias 13 are formed as described above, and etching the copper foil to form a circuit pattern (signal layer) 14. FIG. 3 shows a multilayer circuit board 16, which is laminated so that the vias 13 of the via films 10 and 10 shown in FIGS. 1 and 2 are in contact with each other, and is heated and pressed to form a two-layer circuit board. Has been done. Film with vias 10,
When 10 are piled up as described above, and heated and pressed, the thermoplastic polyimide film 11 is softened, and the vias 13 formed in the upper and lower via-formed films 10 are surely in contact with each other, and the signal The layer 14 is bonded while being buried in the polyimide film 11. Although the upper and lower vias 13 and 13 are simply in contact with each other, the polyimide films 11 and 11 are firmly in contact with each other due to the heat shrinkage of the polyimide films 11 and 11, and the electrical conduction is surely secured. As is apparent from FIG. 3, the signal layer 14 between the films 10 and 10 having both vias is sandwiched by the vias 13 from both sides, and the upper and lower sides are sandwiched by the copper foils 12, 12. Copper foil 12,
If 12 is set as a ground layer, the signal layer 14 has a pseudo coaxial structure with a rectangular cross section formed by the via 13 and the copper foil 12, and a structure capable of preventing crosstalk. Also, the width of the signal layer 14,
By adjusting the thickness of the polyimide film 11 and the pitch of the vias 13, impedance (Zo = 50 ohm) matching can be easily achieved. In the above embodiment, the circuit board is formed of two layers, but it may be formed of a multilayer circuit board of three layers or more. In this case, by forming not only the signal layer but also the power supply layer, the ground layer, etc., a multilayer circuit board having more excellent electrical characteristics can be formed.
【０００９】図４は多層リードフレーム２０に形成した
実施例を示す。２１は単層リードフレームであり、素子
搭載部２２、インナーリード２３、アウターリード２４
を有する通常のリードフレーム形状に形成されている。
３０は多層回路基板であり、素子搭載部２２近傍のイン
ナーリード２３上に搭載される。多層回路基板３０は、
前記実施例の多層回路基板１６の例にならって形成され
る。すなわち、上層から接地層３１、信号層３２、電源
層３３、接地層３４に構成されている。また信号層３２
の各信号ラインは、図３に示されるのと同様にビア１３
と上下の接地層３１、３４とで断面矩形状に囲まれる擬
似同軸構造に形成されている。上記の多層回路基板３０
は、素子搭載部２２を囲む枠状に形成され、その内壁側
に半導体素子２９とワイヤにより接続される、接地層３
１のワイヤボンディングエリア、信号層３２のワイヤボ
ンディングエリア、電源層３３のワイヤボンディングエ
リアが階段状に露出する構造となっている。各接地層３
１、信号層３２、電源層３３、接地層３４はビアを介し
てインナーリード２３に接続される。FIG. 4 shows an embodiment formed on the multilayer lead frame 20. Reference numeral 21 is a single-layer lead frame, which includes an element mounting portion 22, an inner lead 23, and an outer lead 24.
Is formed in a normal lead frame shape.
A multilayer circuit board 30 is mounted on the inner leads 23 near the element mounting portion 22. The multilayer circuit board 30 is
It is formed following the example of the multilayer circuit board 16 of the above embodiment. That is, the upper layer includes the ground layer 31, the signal layer 32, the power supply layer 33, and the ground layer 34. Also, the signal layer 32
Each signal line of the via 13 is similar to that shown in FIG.
And the upper and lower ground layers 31, 34 are formed in a pseudo coaxial structure surrounded by a rectangular cross section. The above multilayer circuit board 30
Is formed in a frame shape surrounding the element mounting portion 22 and is connected to the semiconductor element 29 by a wire on the inner wall side thereof.
1 has a structure in which the wire bonding area of 1, the wire bonding area of the signal layer 32, and the wire bonding area of the power supply layer 33 are exposed stepwise. Each ground layer 3
1, the signal layer 32, the power supply layer 33, and the ground layer 34 are connected to the inner leads 23 via vias.
【００１０】上記のようにして多層リードフレーム２０
が形成されている。この多層リードフレーム２０によれ
ば、信号層３２が銅箔をエッチング加工して形成される
ので、信号ラインの多ピン化が可能であり、また線幅を
ほぼ一定にでき、該線幅、ポリイミドフィルム１１の厚
さ等を選択することで、各信号ラインのインピーダンス
のマッチングが図れる。さらに擬似同軸構造により各信
号線路間のクロストークを効果的に抑えることができる
ので、超高速、超高周波数のデバイスに対応できる。も
ちろん、電源層３３、接地層３４を信号層３２と別途構
成して重ねた構造にしているので、前記従来の多層リー
ドフレームの電源ノイズの排除等の特性にも優れてい
る。As described above, the multilayer lead frame 20
Are formed. According to this multilayer lead frame 20, since the signal layer 32 is formed by etching a copper foil, the number of pins of the signal line can be increased and the line width can be made substantially constant. By selecting the thickness or the like of the film 11, the impedance matching of each signal line can be achieved. Further, since the pseudo coaxial structure can effectively suppress the crosstalk between the signal lines, it can be applied to ultra-high speed and ultra-high frequency devices. Of course, since the power supply layer 33 and the ground layer 34 are separately formed and stacked on the signal layer 32, the conventional multi-layered lead frame is also excellent in characteristics such as elimination of power supply noise.
【００１１】図５はメタルコアパッケージ３５に多層回
路基板３６を搭載した多層パッケージ３７の実施例を示
す。メタルコアパッケージ３５は金属製のヒートシンク
３８上に絶縁シート３９を介して回路パターン４０が形
成され、該回路パターン４０に上記の多層回路基板３６
が接続され、またアウターリード４１が接続されてな
る。図５に示す例では、多層回路基板３６は図３に示す
多層回路基板１６、すなわち上下に接地層１２、１２が
形成され、中間の信号層１４がビア１３と接地層１２、
１２で矩形に囲まれた擬似同軸構造のものに形成されて
いる。本実施例では、ヒートシンク３８を有する放熱性
に優れるパッケージに形成されているので、高速、高周
波数のデバイスにより好適に対応できる。また本実施例
でも、多層回路基板は上記に限られず、図４等に示され
る任意の構造の多層回路基板を搭載することにより、種
々の電気的特性を満足できる多層パッケージを提供でき
る。FIG. 5 shows an embodiment of a multi-layer package 37 in which a multi-layer circuit board 36 is mounted on a metal core package 35. In the metal core package 35, a circuit pattern 40 is formed on a metal heat sink 38 via an insulating sheet 39, and the multilayer circuit board 36 is formed on the circuit pattern 40.
And the outer leads 41 are also connected. In the example shown in FIG. 5, the multilayer circuit board 36 has the multilayer circuit board 16 shown in FIG. 3, that is, the ground layers 12 and 12 are formed on the upper and lower sides, and the intermediate signal layer 14 is the via 13 and the ground layer 12.
It is formed in a pseudo coaxial structure surrounded by a rectangle by 12. In this embodiment, since the package having the heat sink 38 and excellent in heat dissipation is formed, it is possible to favorably cope with a high-speed and high-frequency device. Also in this embodiment, the multilayer circuit board is not limited to the above, and by mounting a multilayer circuit board having an arbitrary structure shown in FIG. 4 or the like, it is possible to provide a multilayer package that can satisfy various electrical characteristics.
【００１２】以上本発明につき好適な実施例を挙げて種
々説明したが、本発明はこの実施例に限定されるもので
はなく、発明の精神を逸脱しない範囲内で多くの改変を
施し得るのはもちろんである。Although the present invention has been variously described with reference to the preferred embodiments, the present invention is not limited to these embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.
【００１３】[0013]
【発明の効果】本発明に係る多層回路基板によれば、比
較的安価に提供できると共に、多ピン化が図れ、インピ
ーダンスのマッチングが容易にとれ、さらに擬似同軸構
造を形成したのでクロストークを効果的に抑えることが
でき、超高速、超高周波数のデバイス用に用いることが
できるという著効を奏する。According to the multilayer circuit board of the present invention, it can be provided at a relatively low cost, the number of pins can be increased, the impedance can be easily matched, and the pseudo-coaxial structure is formed. It can be effectively suppressed and can be used for ultra-high speed and ultra-high frequency devices.
【図１】ビア付きフィルムの断面説明図である。FIG. 1 is a cross-sectional explanatory view of a film with a via.
【図２】信号層を形成したビア付きフィルムの断面説明
図である。FIG. 2 is a cross-sectional explanatory view of a film with a via formed with a signal layer.
【図３】擬似同軸構造の多層回路基板の一例を示す断面
説明図である。FIG. 3 is a cross-sectional explanatory view showing an example of a multilayer circuit board having a pseudo-coaxial structure.
【図４】多層リードフレームの実施例を示す断面説明図
である。FIG. 4 is an explanatory cross-sectional view showing an example of a multilayer lead frame.
【図５】多層パッケージの一例を示す断面説明図であ
る。FIG. 5 is a cross-sectional explanatory view showing an example of a multilayer package.
１０ ビア付きフィルム １１ ポリイミドフィルム １２ 銅箔 １３ ビア １４ 信号層 １６ 多層回路基板 ２０ 単層リードフレーム ２９ 半導体素子 ３０ 多層回路基板 ３１ 接地層 ３２ 信号層 ３３ 電源層 ３４ 接地層 ３５ メタルコアパッケージ 10 Film with Via 11 Polyimide Film 12 Copper Foil 13 Via 14 Signal Layer 16 Multilayer Circuit Board 20 Single Layer Lead Frame 29 Semiconductor Element 30 Multilayer Circuit Board 31 Ground Layer 32 Signal Layer 33 Power Layer 34 Ground Layer 35 Metal Core Package
Claims (5)
以上の多層に積層され、隣接する前記フィルム間の信号
層を挾む両フィルムの前記ビアが導通され、かつ該両フ
ィルムの他面に形成された接地層に前記ビアが接続され
て、前記信号層を囲む断面矩形の擬似同軸構造が形成さ
れていることを特徴とする多層回路基板。1. A film with a via is laminated in multiple layers of two or more layers with a signal layer sandwiched therebetween, the vias of both films sandwiching the signal layer between adjacent films are electrically connected, and the other surface of the both films is connected. The multilayer circuit board, wherein the via is connected to the ground layer formed on the substrate to form a pseudo-coaxial structure having a rectangular cross section surrounding the signal layer.
れ、搭載される半導体素子と電気的に接続される端子部
を有し、かつ前記単層リードフレームのアウターリード
に導通がとられる多層回路基板とを具備し、 該多層回路基板が、ビア付きフィルムが信号層を挟んで
２層以上の多層に積層され、隣接する前記フィルム間の
信号層を挾む両フィルムの前記ビアが導通され、かつ該
両フィルムの他面に形成された接地層に前記ビアが接続
されて、前記信号層を囲む断面矩形の擬似同軸構造が形
成されている多層回路基板であることを特徴とする多層
リードフレーム。2. A single-layer lead frame, and a terminal portion laminated on the inner lead side of the single-layer lead frame and electrically connected to a semiconductor element to be mounted, A multi-layer circuit board having electrical continuity with outer leads, wherein the multi-layer circuit board is laminated in two or more layers with a film having a via sandwiching a signal layer, and sandwiching a signal layer between adjacent films. A multilayer circuit board in which the vias of both films are electrically connected, and the vias are connected to a ground layer formed on the other surface of both films to form a pseudo-coaxial structure having a rectangular cross section surrounding the signal layer. A multi-layered lead frame characterized by being present.
層と、電源層および／または接地層とを具備することを
特徴とする請求項２記載の多層リードフレーム。3. The multilayer lead frame according to claim 2, wherein the circuit pattern of the multilayer circuit board comprises a signal layer and a power supply layer and / or a ground layer.
パターンにアウターリードが接続されたメタルコアパッ
ケージと、 該メタルコアパッケージの、半導体素子が搭載されるイ
ンナー側に積層され、前記搭載される半導体素子と電気
的に接続される端子部を有し、かつメタルコアパッケー
ジに導通がとられる多層回路基板とを具備し、 該多層回路基板が、ビア付きフィルムが信号層を挟んで
２層以上の多層に積層され、隣接する前記フィルム間の
信号層を挾む両フィルムの前記ビアが導通され、かつ該
両フィルムの他面に形成された接地層に前記ビアが接続
されて、前記信号層を囲む断面矩形の擬似同軸構造が形
成されている多層回路基板であることを特徴とする多層
パッケージ。4. A metal core package having a circuit pattern formed on an upper surface thereof and outer leads connected to the circuit pattern, and a semiconductor element mounted on the inner side of the metal core package on which a semiconductor element is mounted, the semiconductor element being mounted. A multi-layer circuit board having a terminal portion electrically connected to a metal core package and having electrical continuity in a metal core package, wherein the multi-layer circuit board is a multi-layer circuit having two or more layers with a film having a via sandwiching a signal layer. A cross section surrounding the signal layers, wherein the vias of both films laminated and sandwiching the signal layer between the adjacent films are conducted, and the vias are connected to a ground layer formed on the other surface of the both films. A multi-layer package, which is a multi-layer circuit board in which a rectangular pseudo-coaxial structure is formed.
層と、電源層および／または接地層とを具備することを
特徴とする請求項４記載の多層パッケージ。5. The multilayer package according to claim 4, wherein the circuit pattern of the multilayer circuit board comprises a signal layer and a power supply layer and / or a ground layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10680893A JP3246796B2 (en) | 1993-05-07 | 1993-05-07 | Multilayer package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10680893A JP3246796B2 (en) | 1993-05-07 | 1993-05-07 | Multilayer package and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06318668A true JPH06318668A (en) | 1994-11-15 |
| JP3246796B2 JP3246796B2 (en) | 2002-01-15 |
Family
ID=14443156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10680893A Expired - Fee Related JP3246796B2 (en) | 1993-05-07 | 1993-05-07 | Multilayer package and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3246796B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098175A (en) * | 1995-06-14 | 1997-01-10 | Fuji Kiko Denshi Kk | Shelf formation method and bonding of multilayer printed-circuit board |
| US6555763B1 (en) | 1998-09-18 | 2003-04-29 | Fuchigami Micro Co., Ltd. | Multilayered circuit board for semiconductor chip module, and method of manufacturing the same |
-
1993
- 1993-05-07 JP JP10680893A patent/JP3246796B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098175A (en) * | 1995-06-14 | 1997-01-10 | Fuji Kiko Denshi Kk | Shelf formation method and bonding of multilayer printed-circuit board |
| US6555763B1 (en) | 1998-09-18 | 2003-04-29 | Fuchigami Micro Co., Ltd. | Multilayered circuit board for semiconductor chip module, and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3246796B2 (en) | 2002-01-15 |
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