JPH06244528A - Manufacture of printed-wiring board - Google Patents

Manufacture of printed-wiring board

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Publication number
JPH06244528A
JPH06244528A JP5477493A JP5477493A JPH06244528A JP H06244528 A JPH06244528 A JP H06244528A JP 5477493 A JP5477493 A JP 5477493A JP 5477493 A JP5477493 A JP 5477493A JP H06244528 A JPH06244528 A JP H06244528A
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JP
Japan
Prior art keywords
hole
substrate
wiring board
formed
printed wiring
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5477493A
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Japanese (ja)
Inventor
Toshio Ofusa
Sotaro Toki
Taketo Tsukamoto
荘太郎 土岐
健人 塚本
俊雄 大房
Original Assignee
Toppan Printing Co Ltd
凸版印刷株式会社
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Application filed by Toppan Printing Co Ltd, 凸版印刷株式会社 filed Critical Toppan Printing Co Ltd
Priority to JP5477493A priority Critical patent/JPH06244528A/en
Publication of JPH06244528A publication Critical patent/JPH06244528A/en
Application status is Pending legal-status Critical

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Abstract

PURPOSE:To provide the manufacturing method, of a printed-wiring board, wherein it can form a continuity hole in the board wish good accuracy and its productivity is high. CONSTITUTION:Parts in which a continuity hole is to be formed in metal thin- film layers 4, 5 formed on both faces of a board 1 formed in such a way that a glass cloth 2 has been impregnated with a resin 3 and hardened are removed. Then, the resin 3 on the board is removed by an atmospheric-pressure glow plasma etching operation 6, a hole is worked, a plating operation 7 is executed to the formed hole, and the continuity hole 8 is formed.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はプリント配線基板の製造方法に関するもので、特に基板の表面と裏面との電気的導通を取るための表裏貫通した導通孔または任意の導体層と他の導体層との電気的導通を取るための非貫通の導通孔を形成する方法に関するものである。 The present invention relates to the a method for manufacturing a printed wiring board, in particular the front and back through the through hole or any conductor layer and another conductor layer for electrical conduction between the surface and the back surface of the substrate to a method of forming a non-through conducting hole for electrical conduction between.

【0002】 [0002]

【従来の技術】プリント配線基板では、基板の表面の配線パターンと裏面の配線パターンとの電気的導通を取るための手段として、基板に貫通孔をあけ、これをめっきで導通処理して表裏貫通した導通孔を形成する方法が従来一般に行われている。 BACKGROUND OF THE INVENTION printed wiring board, as a means for electrical conduction between the wiring pattern and the back surface of the wiring pattern on the surface of the substrate, opened a through-hole in the substrate, front and back through conductive treatment to this plating method of forming the through hole is generally performed prior art.

【0003】 [0003]

【発明が解決しようとする課題】ところで、上記の基板に貫通孔をあける方法としては従来はドリルを用いて行なうのが一般的である。 [SUMMARY OF THE INVENTION Incidentally, as a method of drilling a through-hole in said substrate conventionally is generally carried out using a drill.

【0004】しかしながら、このようなドリルを用いた機械的な孔あけによる手法では、加工時に基板にストレスがかかり、また削りかすが発生するため、めっきを行なう前にこれを十分に取り除いておかないと貫通孔内のめっきの不着による断線が生じやすく、信頼性に欠ける結果となる。 However, in the method due to mechanical drilling using such a drill, stress is applied to the substrate during processing, since also shavings occurs Failure to remove sufficient this before performing plating disconnection is likely to occur due to non-delivery of the plating in the through-hole, resulting in unreliable. また、最近の電子機器への高機能化・多機能化・小型化の要求に対応して複数の素子を一つの標準パッケージ内に納めたより高密度の実装が求められており、このような高密度実装を行なうためにはますます小さな径の貫通孔を精度良く形成する必要があるが、ドリルによる機械的な孔あけでは精度上の限界がある。 Also, recent has been required high-density mounting than pay a plurality of elements in one standard package in response to demands for higher functionality and multifunctionality and miniaturization of the electronic apparatus, such high Although in order to perform the density mounting is required to be formed increasingly through hole of smaller diameter precisely, there is a limit on the accuracy of a mechanical drilling with a drill. しかも、1つの基板に何箇所もの貫通孔を形成する場合には、機械的な孔あけではきわめて時間がかかることになる。 Moreover, in the case of forming the well through holes several places in a single substrate it will take very time the mechanical drilling.

【0005】一方、特公平 2-57356号公報には、CF 4 On the other hand, Japanese Patent Kokoku 2-57356, CF 4
及びO 2を含む反応性ガス雰囲気中でプラズマエッチングにより貫通孔を形成する方法が開示されているが、エッチング速度が非常に遅く加工に時間がかかること、サイドエッチ量が大きく貫通孔内の端部のめっきが着きにくくめっき不着による断線が生じやすいこと等の問題がある。 And a method of forming a through hole by plasma etching in a reactive gas atmosphere containing O 2 is disclosed, the end of the etch rate takes time to process very slow, side etching amount is large through hole disconnection due to plating arrive hardly plated non-bonding parts is a problem such that the prone.

【0006】本発明は上記従来の問題に鑑みなされたもので、基板に導通孔を精度良く形成出来、しかも生産性の高いプリント配線基板の製造方法を提供することを目的とする。 [0006] The present invention has been made in view of the conventional problems described above, the through hole in the substrate can precisely formed, moreover an object to provide a method for manufacturing a high productivity printed circuit board.

【0007】 [0007]

【課題を解決するための手段】上記目的を達成するため、本発明は、プリント配線基板を構成する少なくとも一層の基板に表面と裏面との電気的導通を取るための表裏貫通した導通孔または任意の導体層と他の導体層との電気的導通を取るための非貫通の導通孔を形成するプリント配線基板の製造方法において、前記基板に設けた金属薄膜層の導通孔を形成する部分を除去し、次いで大気圧グロープラズマエッチングにより前記基板の孔あけ加工を行ない、しかる後めっきによる導通処理を行なうことにより導通孔を形成することを特徴としている。 To achieve the above object, according to an aspect of the present invention, through hole, or any and sides through for electrical conduction between the surface and the back surface at least one layer of a substrate constituting a printed wiring board in the conductive layer and another non-through method for manufacturing a printed wiring board for forming a through hole in order to make electrical connection between the conductor layer, removing the portion forming the through hole of the metallic thin film layer provided on the substrate , and then subjected to drilling of the substrate by atmospheric pressure glow plasma etching is characterized by forming a through hole by performing conduction treatment by thereafter plating.

【0008】以下、本発明を詳述する。 [0008] In the following, the present invention will be described in detail.

【0009】図1は本発明に係るプリント配線基板の製造方法の一例を工程順に示す断面図である。 [0009] Figure 1 is a cross-sectional views sequentially showing the steps of an example of a method for manufacturing a printed wiring board according to the present invention.

【0010】同図(a)に示すように、使用する基板1 [0010] As shown in FIG. 6 (a), the substrate used 1
はガラスクロス2に例えばエポキシ、ポリイミド等の樹脂3を含浸させ硬化させて出来たもので、これによって必要な材料強度を持たせている。 Are intended made by curing the glass cloth 2 such as epoxy, resin impregnated 3 such as polyimide, which to have a material strength required by. また、基板1の両面にはそれぞれ銅などの導電性の金属薄膜層4,5を有している。 Also, each of the both surfaces of the substrate 1 with a conductive metal thin film layer 4, 5, such as copper. 該金属薄膜層4,5はそれぞれ基板1の表面と裏面の配線パターン等を形成する。 Each the metal thin film layer 4, 5 forms a front surface and a back surface of the wiring pattern board 1 and the like.

【0011】次に、同図(b)に示すように、上記基板1の両面に設けた金属薄膜層4,5の導通孔を形成する部分をフォトエッチングによるパターニングで除去する。 [0011] Next, as shown in FIG. (B), removing a portion forming the through hole of the metal thin film layer 4, 5 provided on both surfaces of the substrate 1 by patterning by photo-etching. すなわち、金属薄膜層4,5の表面に感光性樹脂を塗布又は電着し、次いでパターン露光を行ない、これを現像してレジストパターンを形成し、露出した部分の金属薄膜層をエッチングで除去して、最後にレジストパターンを除去することにより、金属薄膜層4,5をパターニングする。 That is, a photosensitive resin on the surface of the metal thin film layer 4, 5 is applied or electrodeposited and then subjected to pattern exposure, and developing the formed resist pattern, the metal thin film layer of the exposed portion is removed by etching Te, by removing the last resist pattern, to pattern the metal thin film layer 4, 5.

【0012】次いで、同図(c)に示すように、基板1 [0012] Then, as shown in FIG. (C), the substrate 1
の孔あけ加工を行なう。 Perform the drilling. 該孔あけ加工は、先にパターニングした金属薄膜層4,5をマスクにして、大気圧グロープラズマエッチング6により行なう。 Pores drilling is to the metal thin film layer 4, 5 is patterned earlier in a mask, by an atmospheric pressure glow plasma etching 6.

【0013】図4にかかる大気圧グロープラズマエッチングを行なう装置の概略模式図を示した。 [0013] showed a schematic diagram of apparatus for performing such atmospheric pressure glow plasma etching in FIG. 2枚の平行平板電極10,11のうちの少なくとも一方の電極(図4 At least one electrode of the two parallel plate electrodes 10 and 11 (FIG. 4
ではアノード10である)の表面にガラス、セラミックス、プラスチック等の固体誘電体9を配設したもので、 In those glass, ceramics, a solid dielectric 9 such as plastic or the like is disposed on the surface of the anode 10 is)
加工する基板1はカソード11上に設置される。 Substrate 1 to be processed is placed on the cathode 11. また、 Also,
導入ガスとしては希ガスと反応性ガスとの混合ガスが使用され、この混合ガスの導入によってチャンバー内は大気圧に保持される。 The introduced gas is used mixed gas of reactive gas and a rare gas, in the chamber by the introduction of the mixed gas is maintained at atmospheric pressure. 使用する希ガスとしてはHe,N As the rare gas used the He, N
e,Ar等の単体又は混合ガスを任意に用いることが出来るが、特にHeが好ましい。 e, although a single or a mixed gas such as Ar optionally used it is possible, particularly He is preferred. また、反応性ガスとしてはO 2 ,CF 4 ,CHF 3等の単体又は混合ガスを任意に用いることが出来る。 As the reactive gas O 2, CF 4, CHF 3 or the like arbitrarily used it can be a unitary or mixed gas. 希ガスと反応性ガスとの混合比については希ガス濃度を65%以上とすることが好ましい。 It is preferable that the rare gas concentration of 65% or more for the mixing ratio of the reactive gas and a rare gas.

【0014】これによって、2枚の電極10,11間において大気圧下で安定なグロー放電プラズマを生じさせ、生成した活性種により基板1のエッチングが行われる。 [0014] Thus, between the two electrodes 10 and 11 which results in the creation of a stable glow discharge plasma under atmospheric pressure, etching of the substrate 1 is performed by the generated active species.

【0015】この方法によると、エッチング速度が大きく、サイドエッチ量は小さいので、短時間で精度の良い加工を行える。 [0015] According to this method, a large etching rate, since side etching amount is small, a short time can perform a good machining precision. なお、導入ガスの流量、高周波出力等は任意に適当な値に設定される。 The flow rate of the introduced gas, the high frequency output and the like are arbitrarily set appropriate value.

【0016】このような大気圧グロープラズマエッチング6により、基板1を構成する樹脂3は除去され、ガラスクロス2はエッチングされずにそのまま孔加工部分に露出する。 [0016] By such an atmospheric pressure glow plasma etching 6, the resin 3 constituting the substrate 1 is removed, the glass cloth 2 is exposed directly to the hole machining portion without being etched.

【0017】しかる後、同図(d)に示すように、孔あけした部分にめっき膜7を施して導通孔8を形成する。 [0017] Thereafter, as shown in FIG. 2 (d), to form a through hole 8 by plating films 7 in a hole drilled portion.
めっきの方法としては無電解めっきと電解めっきの組合せが特に好適である。 As a method for plating a combination of electroless plating and electroless plating are particularly preferred. なお、上述したように、ガラスクロス2は孔加工部分に露出し残存しているが、縦方向と横方向のガラス繊維の束の間に貫通孔(同図(c)の符号2aで示す部分)が形成されているので、この貫通孔の内部にもめっき膜7が形成され、その結果、基板1の表面と裏面とが電気的に導通する。 As described above, although the glass cloth 2 are exposed in the hole machining portion remaining, vertical and horizontal glass fiber bundles into the through hole of the (portion indicated by reference numeral 2a in FIG. (C)) is because it is formed, the inside of the through holes also plated film 7 is formed, as a result, the surface and the back surface of the substrate 1 are electrically connected.

【0018】図2は本発明に係るプリント配線基板の製造方法の他の例を工程順に示す断面図であり、図1と同一箇所には同一符号を付して適宜重複説明を省略する。 [0018] Figure 2 is a sectional view showing another example of a method for manufacturing a printed wiring board according to the present invention in order of steps, the same portions as FIG. 1 and will not be duplicated will be denoted by the same reference numerals.

【0019】本製造工程においては、前述のガラスクロス2を用いた基板1の代わりに、アラミド繊維2′にエポキシ、ポリイミド等の樹脂3′を含浸させ硬化させて出来た基板1′を使用する(図2(a)参照)。 In the present production process is used in place of the substrate 1 using the glass cloth 2 above, 'epoxy, resin 3 such as polyimide' aramid fibers 2 substrates could be cured impregnated with 1 ' (see FIG. 2 (a)). なお、 It should be noted that,
アラミド繊維でなくても適度な剛性を有するものであれば他の繊維状高分子材料を用いても一向に差支えない。 As long as it has appropriate rigidity without aramid fiber does not at all harm in using other fibrous polymeric materials.

【0020】次に、同図(b)に示すように、前述と全く同様にして、上記基板1′の両面に設けた金属薄膜層4,5の導通孔を形成する部分をフォトエッチングによるパターニングで除去する。 Next, as shown in FIG. (B), in the same manner as described above, patterning by photo-etching the portion forming the through hole of the metal thin film layer 4, 5 provided on both surfaces of the substrate 1 ' in to remove.

【0021】次いで、同図(c)に示すように、前述の大気圧グロープラズマエッチング6により基板1′の孔あけ加工を行なう。 [0021] Then, as shown in FIG. (C), performing drilling of the substrate 1 'by the atmospheric pressure glow plasma etching 6 above. 図示より明らかなように、前述のガラスクロス2を用いた場合と異なり、基板1′を構成する樹脂3′だけでなくアラミド繊維2′も完全にエッチング除去され、貫通孔を形成する。 As is apparent from shown, unlike the case of using a glass cloth 2 above, aramid fibers 2 not only 'resin 3 constituting the' substrate 1 'it is also completely etched away to form a through hole.

【0022】しかる後、同図(d)に示すように、出来た貫通孔に無電解めっき等によるめっき膜7を施して導通孔8を形成する。 [0022] Thereafter, as shown in FIG. 2 (d), to form a through hole 8 plated film 7 by electroless plating or the like in the through hole made.

【0023】このようにアラミド繊維2′等を用いた場合には、上述のエッチングによる孔あけ工程においてアラミド繊維2′等も完全にエッチング除去された貫通孔が形成されるため、前述のガラスクロス2を用いた場合のように例えば孔あけした部分にガラスクロス2の貫通孔2aが存在していないような小径の導通孔8であっても全く問題なく形成できるという利点がある。 [0023] Thus aramid fibers 2 'in the case of using such, aramid fibers 2 in the drilling process by the etching described above' for through-hole which is removed completely even such as etching is formed, the above-mentioned glass cloth there is an advantage that a small-diameter through hole 8 as the through hole 2a of the glass cloth 2 is not present can be formed without any problem even for example holes drilled portions as in the case of using 2.

【0024】また、本発明は上述のような表裏貫通した導通孔だけでなく、複数の導体層のうちの任意の導体層と他の導体層との電気的導通を取るための非貫通の導通孔(一般にVIAホールとも呼ばれている)も形成できる。 Further, the present invention not only the front and back through the through hole as described above, non-penetrating conduction for electrical conduction between any conductor layer and another conductor layer of the plurality of conductive layers holes (commonly also referred to as VIA hole) can be formed. 図3はその一例を示したもので、金属薄膜層4, Figure 3 shows an example thereof, the metal thin film layer 4,
4′,4″において金属薄膜層4と4′及び4′と4″ 4 ', 4 "metal thin film layer 4 in the 4' and 4 'and 4"
のそれぞれの電気的導通を取るための非貫通の導通孔8′を形成した場合を示している。 Shows a case where the forming a non-through conducting hole 8 'for taking each of the electrical continuity.

【0025】 [0025]

【作用】本発明は、基板に導通孔を形成するに際し、大気圧グロープラズマエッチングにより基板の孔あけ加工を行なう。 DETAILED DESCRIPTION OF THE INVENTION The present invention, when forming a through hole in the substrate, performing drilling of the substrate by atmospheric pressure glow plasma etching.

【0026】これによって、小さな径の導通孔であっても精度良く形成出来、しかもエッチング速度が早いため加工に要する時間が少なくて済むようになる。 [0026] Thus, even through hole of smaller diameter precisely it is formed, yet so fewer time required for processing for fast etching rate.

【0027】さらに、孔あけ加工のサイドエッチ量が小さいため、導通孔内のめっき不着による断線等の不具合は生じないので信頼性が非常に高くなる。 Furthermore, since side etching amount of drilling small, reliability is very high because not occur inconvenience such as a break due to plating non-delivery in the through hole.

【0028】 [0028]

【実施例】以下、実施例により本発明を更に具体的に説明する。 EXAMPLES The following further illustrate the present invention through examples.

【0029】実施例−1 ガラスクロスにエポキシ樹脂を含浸させ硬化させてなる厚さ 100μmのガラスエポキシ板の両面にそれぞれ厚さ [0029] Each thickness on both surfaces of the glass epoxy plate having a thickness of 100μm obtained by curing impregnated with epoxy resin in Example 1 Glass cloth
18μmの銅箔層を設けた銅張積層基板の表面及び裏面に感光性樹脂「フォトED P−1000(商品名)」 The front and back surfaces of the copper-clad laminated board provided a copper foil layer of 18μm photosensitive resin "Photo ED P-1000 (trade name)"
(日本ペイント(株)製)を電着により付着させ、これにマスク露光法により所定の円孔のパターンを焼き付け、メタケイ酸ソーダ溶液で現像し、露光した部分の上記感光性樹脂を除去した。 Deposited by electrodeposition (Nippon Paint Co., Ltd.), this baking a pattern of a predetermined circular hole by mask exposure method, developed in sodium metasilicate solution to remove the photosensitive resin of the exposed portion. 次いで、塩化第2鉄溶液で露出部の銅箔をエッチングし、5%水酸化ナトリウム溶液で残存する感光性樹脂を剥離し、水洗、乾燥することによりガラスエポキシ板の両面に導通孔を形成する部分の銅箔を除去した孔径 0.6mmのパターンを形成した。 Then, by etching the copper foil exposed portion with ferric chloride solution, separating the photosensitive resin remaining in a 5% sodium hydroxide solution, washed with water, forming a through hole on both sides of a glass epoxy plate and dried to form a pattern having a pore size of 0.6mm removing the copper foil portion.

【0030】次に、出来た試料を図4に示す構造のプラズマエッチング装置のチャンバー内に設置し、以下の条件でプラズマエッチングによる基板の孔あけ加工を行なった。 Next, can sample was placed in a chamber of a plasma etching apparatus of the structure shown in FIG. 4, was subjected to drilling of the substrate by plasma etching under the following conditions. このときの基板のエポキシ樹脂層のエッチング速度はおよそ 0.5μm/分であった。 Etch rate of the epoxy resin layer of the substrate at this time it was approximately 0.5 [mu] m / min. なお、ガラスクロスはエッチングされないが、ヤーン(ガラス繊維の束)間に約 0.1mm角の貫通孔が複数個形成されていた。 The glass cloth is not etched, the through holes of approximately 0.1mm square between yarns (bundle of glass fibers) have been formed in plural. 処理条件導入ガス :O 2 (流量50SCCM)+He(流量2000 Processing conditions introduced gas: O 2 (flow rate 50SCCM) + He (flow rate 2000
SCCM) 高周波出力:90KHz 50W SCCM) high-frequency output: 90KHz 50W

【0031】しかる後、チャンバー内から試料を取り出し、前処理を実施後、めっき液「スルカップ(商品名)」(上村工業(株)製)に浸漬させて無電解銅めっき(55℃,3分)を行ない、さらに電解銅めっきでめっき厚約30μmの導通孔を形成した。 [0031] Thereafter, the sample was removed from the chamber, after carrying out the pretreatment, plating solution "THRU-CUP (trade name)" electroless copper plating by immersing in (Uemura & Co., Ltd.) (55 ° C., 3 min ) performs, to form a further through hole plating thickness of about 30μm by electrolytic copper plating.

【0032】実施例−2 実施例−1のガラスクロスの代わりにアラミド繊維「ケブラー(商品名)」(デュポン社製)を用いた銅張積層基板の両面に実施例−1と全く同様にして導通孔を形成する部分の銅箔を除去したパターンを形成した。 [0032] Aramid fiber "Kevlar (trade name)" instead of the glass cloth in Example -2 Example -1 in the same manner as in Example 1 on both sides of the copper-clad laminate substrate (manufactured by DuPont) to form a copper foil was removed pattern portions forming the through hole.

【0033】次に、この試料を実施例−1と全く同様の条件にてエッチングを行ない基板の孔あけ加工を行なった。 Next, it was subjected to drilling of the substrate subjected to etching the sample under the same conditions as in Example -1. このときの基板のエッチング速度は約 0.5μm/分であり、アラミド繊維も完全にエッチング除去された貫通孔が形成された。 The etching rate of the substrate at this time was about 0.5 [mu] m / min, a through hole aramid fibers also were completely etched off were formed.

【0034】しかる後、実施例−1と同様に、出来た貫通孔の銅めっきを行ない、導通孔を形成した。 [0034] Thereafter, in the same manner as in Example 1, subjected to copper plating can have through-holes, to form a through hole.

【0035】実施例−3 アラミド繊維(前出)にエポキシ樹脂を含浸させ硬化させて出来たアラミドエポキシ板と銅箔層とを図3に示す如く順次積層し全体が5層からなる銅張積層基板の表面及び裏面のそれぞれに実施例−1と全く同様にして導通孔を形成する部分の銅箔を除去したパターン(表面と裏面のパターンの位置は異なっている)を形成した。 [0035] Example -3 aramid fibers (supra) the copper-clad laminate which overall are sequentially laminated as shown an aramid epoxy board made by curing impregnated with epoxy resin and the copper foil layer 3 is composed of five layers front and back surfaces of example -1 exactly the same way to remove the copper foil portion forming the through hole patterns in the respective substrate (position of the surface and the back surface of the pattern is that different) to form.

【0036】次に、この試料を実施例−1と全く同様の条件にてエッチングを行ない基板の孔あけ加工を行なった。 Next, it was subjected to drilling of the substrate subjected to etching the sample under the same conditions as in Example -1. このとき、基板の表面及び裏面のそれぞれからまん中の銅箔層に到る非貫通孔が形成された(図3参照)。 At this time, the non-through hole extending from each of the front and rear surfaces of the substrate to the copper foil layer of the middle is formed (see FIG. 3).

【0037】しかる後、実施例−1と同様に、出来た孔の銅めっきを行ない、導通孔(VIAホール)を形成した。 [0037] Thereafter, in the same manner as in Example 1, subjected to copper plating can have holes, to form a through hole (VIA hole).

【0038】 [0038]

【発明の効果】以上詳細に説明したように、本発明によれば、基板に設けた金属薄膜層の導通孔を形成する部分を除去し、次いで大気圧グロープラズマエッチングにより前記基板の孔あけ加工を行ない、しかる後めっきによる導通処理を行なうことによって、基板の表面と裏面との電気的導通を取るための導通孔を形成するようにしたので、小さな径の導通孔であっても精度良く形成することが出来る。 As described [Effect Invention above in detail, according to the present invention, to remove the portion forming the through hole of the metallic thin film layer provided on the substrate, followed by drilling of the substrate by atmospheric pressure glow plasma etching the performed, by performing the conduction process by thereafter plating, since so as to form a through hole for electrical conduction between the surface and the back surface of the substrate, also precisely formed a through hole of a small diameter to it can be. 特に最近の高密度実装によりますます小径の導通孔を精度良く形成することが求められており、本発明はこの要求に適う優れた方法である。 And it is required to accurately form an increasingly smaller diameter of the introducing hole by particular recent high-density mounting, the present invention is an excellent method meet this demand.

【0039】しかも、エッチング速度が早いため、基板の孔あけ加工に要する時間が少なくて済むようになり、 [0039] Moreover, since the faster etch rate, now require less time required for drilling the substrate,
生産性が著しく向上する。 Productivity is significantly improved.

【0040】さらに、基板の孔あけ加工のサイドエッチ量が小さいため、導通孔内のめっき不着による断線等の不具合は全く生じないので出来た製品の信頼性が非常に高くなる。 [0040] Further, since side etching amount of drilling of the substrate is small, reliability of products made does not occur at all defects such as disconnection due plating non-delivery in the introducing hole is very high.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明のプリント配線基板の製造方法の一例を工程順に示す断面図である。 1 is a cross-sectional views sequentially showing the steps of an example of a method for manufacturing a printed wiring board of the present invention.

【図2】本発明のプリント配線基板の製造方法の他の例を工程順に示す断面図である。 2 is a sectional view showing another example in the order of steps of a method of manufacturing a printed wiring board of the present invention.

【図3】本発明のプリント配線基板の製造方法のその他の例を工程順に示す断面図である。 3 is a cross-sectional views sequentially showing the steps of another example of a method for manufacturing a printed wiring board of the present invention.

【図4】本発明に使用するプラズマエッチング装置の概略模式図である。 Figure 4 is a schematic view of a plasma etching apparatus used in the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1,1′ 基板 2 ガラスクロス 2′ アラミド繊維 3,3′ 樹脂 4,5 金属薄膜層 6 プラズマエッチング 7 めっき膜 8 導通孔 9 固体誘電体 10 アノード 11 カソード 1,1 'substrate 2 glass cloth 2' aramid fibers 3,3 'resin 4,5 metallic thin film layer 6 plasma etching 7 plated films 8 through hole 9 solid dielectric 10 anode 11 cathode

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 プリント配線基板を構成する少なくとも一層の基板に表面と裏面との電気的導通を取るための表裏貫通した導通孔または任意の導体層と他の導体層との電気的導通を取るための非貫通の導通孔を形成するプリント配線基板の製造方法において、前記基板に設けた金属薄膜層の導通孔を形成する部分を除去し、次いで大気圧グロープラズマエッチングにより前記基板の孔あけ加工を行ない、しかる後めっきによる導通処理を行なうことにより導通孔を形成することを特徴とするプリント配線基板の製造方法。 1. A take electrical conduction between at least one layer of front and back through the through hole, or any conductive layer for electrical conduction between the surface and the back surface of the substrate and the other conductor layer constituting the printed circuit board non in penetrating method for manufacturing a printed wiring board for forming a conducting hole in, to remove the portion forming the through hole of the metallic thin film layer provided on the substrate, followed by drilling of the substrate by atmospheric pressure glow plasma etching for It is carried out for producing a printed wiring board and forming a through hole by performing conduction treatment by thereafter plating.
  2. 【請求項2】 前記基板はガラスクロスに樹脂を含浸させたものを使用することを特徴とする請求項1記載のプリント配線基板の製造方法。 Wherein said substrate manufacturing method of the printed wiring board according to claim 1, wherein the use of those of a glass cloth impregnated with resin.
  3. 【請求項3】 前記基板はアラミド繊維等の繊維状高分子材料に樹脂を含浸させたものを使用することを特徴とする請求項1記載のプリント配線基板の製造方法。 Wherein said substrate manufacturing method of the printed wiring board according to claim 1, wherein the use of impregnated with the resin in the fibrous polymer material such as aramid fibers.
JP5477493A 1993-02-19 1993-02-19 Manufacture of printed-wiring board Pending JPH06244528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5477493A JPH06244528A (en) 1993-02-19 1993-02-19 Manufacture of printed-wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5477493A JPH06244528A (en) 1993-02-19 1993-02-19 Manufacture of printed-wiring board

Publications (1)

Publication Number Publication Date
JPH06244528A true JPH06244528A (en) 1994-09-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP5477493A Pending JPH06244528A (en) 1993-02-19 1993-02-19 Manufacture of printed-wiring board

Country Status (1)

Country Link
JP (1) JPH06244528A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098175A (en) * 1995-06-14 1997-01-10 Fuji Kiko Denshi Kk Shelf formation method and bonding of multilayer printed-circuit board
JP2007059305A (en) * 2005-08-26 2007-03-08 Matsushita Electric Ind Co Ltd Plasma processing method and device or conductor
JP2014135516A (en) * 2008-07-09 2014-07-24 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098175A (en) * 1995-06-14 1997-01-10 Fuji Kiko Denshi Kk Shelf formation method and bonding of multilayer printed-circuit board
JP2007059305A (en) * 2005-08-26 2007-03-08 Matsushita Electric Ind Co Ltd Plasma processing method and device or conductor
JP2014135516A (en) * 2008-07-09 2014-07-24 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device

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