JP2003046243A - Method for manufacturing high density multilayer build- up wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a high density multilayer build-up wiring board which does not cause connection defect and is excellent in reliability. SOLUTION: A core substrate 11 wherein a first wiring layer 12a, a first wiring layer 12b and a throughole 13 are formed is prepared. An insulation layer 14 is formed in both sides of the core substrate 11, and a via hole 15 and an alignment mark double ring hole 16 are formed. Furthermore, desmear treatment, conducting processing and electrolytic copper panel plating are carried ort, and an alignment mark 23 is formed in a filled via 21, a second conductor layer 22 and an alignment mark region. A resist pattern 17 is formed by using the alignment mark 23 for exposure, a second wiring layer 22a, a second wiring layer 22b and a land 22c are formed by performing etching treatment for the second conductor layer 22, and a high density multilayer build-up wiring board is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density multi-layered build-up wiring in which each wiring layer formed through insulating layers on both sides of a core substrate having through holes is electrically connected by filled vias. The present invention relates to a method for manufacturing a plate.

[0002]

2. Description of the Related Art In recent years, there has been a demand for miniaturization and thinning of electronic equipment as represented by personal computers.
The printed wiring boards used therein are required to be compact, thin and highly reliable, as well as to have a high density of wiring. Therefore, there is an increasing need for a semiconductor device substrate having a filled via structure in which wiring layers are electrically connected by filled vias. These semiconductor device substrates are equipped with semiconductor chips and other components, and are used for BGA (ball grid array) or PGA (pin grid grid).
In a form such as an array), it is often mounted on a semiconductor device substrate, which is a parent substrate, and also used as a parent substrate.

In order to realize miniaturization and thinning, there is a demand for high-density wiring in which the wiring layer width is narrow and the spacing is small, the wiring layers are multi-layered, and the diameter of via holes connecting the wiring layers is reduced. There is a demand for a highly reliable semiconductor device that does not cause connection failure or insulation failure even if the density is increased.

A multilayer build-up wiring board using a build-up method is known as a semiconductor device substrate that meets these requirements. This method consists of an insulating layer on the core substrate,
The multilayer build-up wiring board is manufactured by repeating the wiring layer forming process.

An example of a method for forming a multilayer build-up wiring board having a filled via structure will be described. 4 (a)-
(E) is a partial schematic cross-sectional view of a manufacturing process in which a filled via and a wiring layer are formed on a core substrate to manufacture a multilayer buildup wiring board. First, the core substrate 5 that has been impositioned
An exposure alignment mark 52d having a circular pattern is formed on the first wiring layer 52a and the alignment mark region around the core substrate 51 on the substrate 1, and an insulating layer 53 having a predetermined thickness is formed (see FIG. 4A).

Next, the laser beam is aligned with the alignment mark 52d for exposure formed in the alignment mark area of the core substrate 51 to perform laser processing, and the insulating layer on the land portion 52c of the first wiring layer 52 is formed. A via hole 54 is formed in 53 and an alignment mark round hole 55 is formed on the conductor layer 52e in the alignment region around the substrate (see FIG. 4B).

Next, a desmear process is performed to form the via hole 5
4, a thin film conductor layer is formed on the alignment mark round hole 55 and the insulating layer 53 by electroless copper plating, electrolytic copper panel plating is performed using the thin film conductor layer as a cathode, and the filled via 61, the second conductor layer 62, and An exposure alignment mark 63 is formed (see FIG. 4C).

Next, a photoresist layer is formed on the second conductor layer 62, the exposure pattern is aligned using the exposure alignment marks 63 formed in the alignment region around the substrate, and pattern exposure, development, etc. are performed. The resist pattern 56 is formed by performing a series of patterning processes (see FIG. 4D).

Next, the second conductor layer 62 is etched by using the resist pattern 56 as an etching mask, and the resist pattern 56 is removed by a dedicated stripping solution to form a second wiring layer 62a, and the land 52c and the second wiring layer 62a are formed. A multilayer build-up wiring board having a filled via structure in which the two wiring layers 62a are electrically connected by the filled vias 61 is manufactured (FIG. 4).
(See (e)). Furthermore, the insulating layer, the filled via,
By repeating the steps of forming the wiring layer and the alignment mark for exposure a required number of times, it is possible to obtain a multilayer buildup wiring board having a filled via structure with a predetermined number of layers.

[0010]

In the manufacturing process of a multilayer build-up wiring board having a filled via structure as described above, an exposure alignment mark used in the next step when forming a filled via and a conductor layer in an insulating layer is formed at the same time. Since it does not require a patterning treatment step at the time of forming the exposure alignment mark, it is a step that is generally used.
When the filled via and the exposure alignment mark are simultaneously formed on this insulating layer, a defect occurs in the surface shape of the exposure alignment mark.

As described above, the mark shape of the exposure alignment mark is generally a large-diameter circular pattern. When electrolytic copper panel plating for a filled via is performed on the alignment mark round hole formed in the insulating layer, the via hole 54 and the alignment mark round hole 55 are filled with the copper conductor layer, and as shown in FIG. A different alignment mark 63 for exposure is formed. As shown in FIG. 4C, the surface shape of the alignment mark 63 for exposure has a gentle edge around the round hole 55 for the alignment mark, and the recognition rate of the alignment mark for exposure decreases in the alignment work process. It becomes a cause of poor alignment.

This misalignment causes a positional deviation between the filled via and the land when forming a multilayer wiring board having a via-on-via filled via structure, and the diameter of the filled via has become smaller with the recent increase in the density of the multilayer wiring board. Therefore, there is a problem in that the electrical connection between the land and the land occurs, and as a result, the reliability of the multilayer wiring board having a filled via structure is reduced.

The present invention has been devised in view of the above problems, and in a multi-layer printed wiring board having a filled via structure in which wiring layers are interconnected by filled vias, a high-density multi-layer structure which is excellent in reliability and does not cause connection failure. An object is to provide a method for manufacturing a build-up wiring board.

[0014]

In order to solve the above problems in the present invention, first, in claim 1, a plurality of wiring layers are provided on both sides of a core substrate having through holes with insulating layers interposed therebetween. And a multilayer printed wiring board in which the wiring layers are electrically connected by filled vias, and a method for manufacturing a high-density multilayer build-up wiring board characterized by comprising at least the following steps: It was done. (A) A step of forming insulating layers on both surfaces of the core substrate on which the through holes and the wiring layers are formed. (B) A step of forming via holes and alignment mark holes in the insulating layer by laser processing. (C) A step of forming a thin film conductor layer by subjecting the via hole, the alignment mark hole, and the insulating layer to a conductive treatment. (D) A step of performing electrolytic copper panel plating using the thin film conductor layer as a cathode to form a filled via, an alignment mark for exposure, and a conductor layer. (E) A step of forming a photosensitive layer on the conductor layer, performing pattern alignment using the alignment mark for exposure, and performing a series of patterning processes such as pattern exposure and development to form a resist pattern. (F) A step of forming a wiring layer by etching the conductor layer and the thin film conductor layer using the resist pattern as a mask and peeling the resist pattern. (G) A step of producing a high-density multi-layer build-up wiring board having a predetermined number of layers by repeating the above-described insulating layer, filled via, and wiring layer forming steps a necessary number of times.

According to a second aspect of the present invention, when the exposure alignment mark formed on the insulating layer has a double ring shape and the outer shape of the double ring is R _D and the ring width is R _w , R _The method of manufacturing a high-density multilayer buildup wiring board according to claim 1, wherein the conditions of _D ≧ 200 μmφ and R _w ≧ 50 μm are satisfied.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. A method for manufacturing a high-density multilayer buildup wiring board according to the present invention is shown in FIGS. 2 (a) to (f) and 3 (b) to (f).
As shown in, an insulating layer 14 is formed on the core substrate 11 on which the first wiring layer 12a, the first wiring layer 12b, and the through holes 13 are formed, and an alignment mark for exposure is electrolytic copper-plated in an alignment region around the substrate. When the shape of the alignment mark formed on the insulating layer at the time of formation is a double ring-shaped pattern as shown in FIG. 3C, the outer shape of the double ring is R _D , and the ring width is R _W , R _D ≧ 200μ
mφ and R _w ≧ 50 μm are satisfied so that
Further, the alignment mark for pattern exposure of the imposition substrate by projection exposure is performed so that the peripheral edge Re of the alignment mark for exposure (see FIG. 3D) obtained by performing electrolytic copper plating is emphasized. The recognition rate is improved, and the alignment accuracy of the wiring pattern and the like is improved. An example of a high-density multilayer build-up wiring board obtained by using the method for manufacturing a high-density multilayer build-up wiring board of the present invention is shown in FIGS. 1 (a) and 1 (b).

A method of manufacturing the high density multilayer buildup wiring board of the present invention will be described. 2 (a) to 2 (f) are schematic partial configuration sectional views showing an embodiment of a method for manufacturing a high-density multilayer buildup wiring board of the present invention. FIG. 3 (b)-
FIG. 2F is a schematic partially enlarged structural sectional view of the area A and a schematic partially enlarged structural sectional view of the alignment mark for exposure in the alignment mark area in FIGS. First,
The core substrate 11 on which the first wiring layer 12a, the first wiring layer 12b, and the through holes 13 are formed is manufactured (FIG. 2A).
reference). As the core substrate 11, a printed wiring board manufactured by laminating an inner layer board on a double-sided wiring board, a printed wiring board manufactured by a build-up method on an insulating base material, and the like are used.

Next, the first wiring layer 12a and the first wiring layer 12
b, a resin solution is formed on both surfaces of the core substrate 11 on which the through holes 13 are formed by screen printing, or
Alternatively, resin films are laminated to form the insulating layer 14 (see FIGS. 2B and 3B).

Next, the alignment mark of the core substrate 11
Use the alignment mark 12d for exposure formed in the area
Position the laser beam of the laser processing machine.
Run the first wiring layer 12a and the first wiring layer 12b.
A via hole 15 is formed in the insulating layer 14 on the contact portion 12c.
Align the insulating layer 14 on the conductor layer 12e in the mark area.
A double ring hole 16 for a mark is formed (see FIG. 2).
(C) and FIG.3 (c)). Where the alignment marker
The double ring hole 16 for the brake_D,
Ring width is R_WAnd then R_D≧ 200μmφ, R_w≧
The condition of 50 μm is satisfied. For example,
A For double hole outer diameter R for hole diameter 50 μm _DIs 20
0 to 500 μm, preferably 400 μm, ring width R_W
Is preferably 50 to 70 μm.

Next, the surface of the via hole 15, the alignment mark double ring hole 16 and the surface of the insulating layer 14 is desmeared, and the insulating layer 14, the via hole 15 and the alignment mark double ring hole 16 are formed. A thin film conductor layer is formed by electroless copper plating, etc., and electrolytic copper panel plating is performed using the thin film conductor layer as a cathode.
An exposure alignment mark 23 is formed in the conductor layer 22 and the alignment mark region (FIGS. 2D and 3).
(See (d)).

Next, a photoresist layer for forming a wiring layer and the like by the subtractive method is formed on the filled via 21 and the second conductor layer 22 and exposed using the exposure alignment mark 23 formed in the alignment region. The exposure mask is aligned by an apparatus, and a series of patterning processes such as exposure and development are performed to form a resist pattern 17 (see FIGS. 2E and 3E).

Next, the second conductor layer 22 and the thin film conductor layer are etched using the resist pattern 17 as an etching mask, the resist pattern 17 is removed by a dedicated stripping solution, and the second wiring layer 22a and the second wiring are formed. The layer 22b and the land portion 22c are formed, and the land portion 12c and the second wiring layer 18 are formed.
It is possible to obtain a high-density multilayer buildup wiring board 100 in which a, the second wiring layer 18b, and the land portion 22c are electrically connected by the filled via 21 (see FIGS. 2F and 3F). . Further, by repeating the steps of forming the insulating layer, the filled via, and the wiring layer a required number of times, it is possible to obtain a high-density multilayer buildup wiring board having a desired number of layers.

[0023]

The present invention will be described in detail with reference to the following examples. Example 1 First, the first wiring layer 12a, the first wiring layer 12b, and the land portion 12 each having a conductor layer thickness of 15 μm on both sides.
A core substrate 11 in which c and the through hole 13 were formed was produced (see FIG. 2A).

Next, the first wiring layer 12a and the first wiring layer 1
An epoxy resin is screen-printed on both surfaces of the core substrate 11 on which 2b is formed and dried to form an insulating layer 14 having a thickness of 45 μm.
Was formed (see FIGS. 2B and 3B).

Next, using the alignment mark 12d formed in the alignment mark region of the core substrate 11,
The laser beam of the laser processing machine is aligned, and the insulating layer 14 on the land portion 12c of the first wiring layer is irradiated with an ultraviolet laser having a frequency of 5 KHz and 30 pulses to form a via hole 15 having an upper diameter of 50 μmφ. A frequency of 5 KH is applied to the insulating layer 14 on the conductor layer 12e in the alignment mark area.
trepanning with a 4-pulse ultraviolet laser, the ring width R _W is 50 μm, and the outer diameter R _{D of the} double ring is 20.
Double ring holes 16 for alignment marks of 0, 300, 400 and 500 μmφ were formed respectively (see FIG. 2).
(C) and FIG.3 (c)).

Next, potassium permanganate (58 g /
L) Desmear treatment is performed on the surface of the via hole 15, the alignment mark double ring hole 16 and the insulating layer 14 with a solution, and then, on the insulating layer 14, in the via hole 15 and the alignment mark double ring hole 16 A thin film conductor layer is formed by electroless copper plating or the like, and electrolytic copper panel plating is performed using the thin film conductor layer as a cathode. Filled vias 21 and 15 μm
The outer diameter R _{D of the} double ring is 200, 300, 400 and 500 in the thick second conductor layer 22 and the alignment mark region.
An exposure alignment mark 23 of μmφ was formed (see FIGS. 2D and 3D).

Next, the filled via 21 and the second conductor layer 2
2, a photoresist layer is formed on the substrate 2, and the exposure mask is aligned with an exposure device using the exposure alignment mark 23 formed in the alignment mark region,
A series of patterning treatments such as development were performed to form a resist pattern 17 (see FIGS. 2E and 3E). Here, as a result of confirming alignment visibility of the exposure apparatus with respect to each of the alignment marks 23 for exposure having a ring width R _W of 50 μm and outer shapes R _{D of the} double ring of 200, 300, 400 and 500 μm The visibility was good.

Next, the second conductor layer 22 and the thin film conductor layer are etched by using the resist pattern 17 as an etching mask, the resist pattern 17 is removed by a dedicated stripping solution, and the second wiring layer 22a and the second wiring are formed. Layers 22b and 140
A land portion 22c of μmφ is formed, and the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are formed.
A high-density multilayer buildup wiring board 100 in which and are electrically connected by filled vias 21 is obtained (see FIGS. 2F and 3F). As a result of confirming the alignment accuracy of the filled via 21 and the land portion 22c of the obtained high-density multilayer build-up wiring board 100, the positional deviation is 1
It was within 5 μm.

<Embodiment 2> In the same process as in Embodiment 1, the first wiring layer 12a, the first wiring layer 12b, the land portion 12c, and the through hole 13 each having a conductor layer thickness of 15 μm are formed on both surfaces.
Insulating layers 14 were formed on both surfaces of the core substrate 11 on which the layers were formed (see FIGS. 2A, 2B and 3B).

Next, using the alignment mark 12d formed in the alignment mark region of the core substrate 11,
The laser beam of the laser processing machine is aligned, and the insulating layer 14 on the land portion 12c of the first wiring layer is irradiated with an ultraviolet laser having a frequency of 5 KHz and 30 pulses to form a via hole 15 having an upper diameter of 50 μmφ. A frequency of 5 KH is applied to the insulating layer 14 on the conductor layer 12e in the alignment mark area.
z, 4 external R _D double ring pulse ring width R _W by trepanning with ultraviolet laser of at 70μm 20
Double ring holes 16 for alignment marks of 0, 300, 400 and 500 μmφ were formed respectively (see FIG. 2).
(C) and FIG.3 (c)).

In the same process as in Example 1, desmear treatment,
Electroless copper plating and electrolytic copper plating are performed so that the filled vias 21, the second conductor layer 22 having a thickness of 15 μm, and the outline R _{D of the} double ring in the alignment mark region are 200, 300,
Alignment mark 2 for exposure of 400 and 500 μmφ
3 was formed (see FIGS. 2D and 3D).

Next, the filled via 21 and the second conductor layer 2
2, a photoresist layer is formed on the substrate 2, and the exposure mask is aligned with an exposure device using the exposure alignment mark 23 formed in the alignment mark region,
A series of patterning treatments such as development were performed to form a resist pattern 17 (see FIGS. 2E and 3E). Here, as a result of confirming the alignment visibility of the exposure apparatus for each of the exposure alignment marks 23 having a ring width R _W of 70 μm and outer shapes R _{D of the} double ring of 200, 300, 400 and 500 μm, The visibility was good.

Next, the second conductor layer 22 and the thin film conductor layer are etched using the resist pattern 17 as an etching mask, the resist pattern 17 is removed by a dedicated stripping solution, and the second wiring layer 22a and the second wiring are formed. Layers 22b and 140
A land portion 22c of μmφ is formed, and the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are formed.
A high-density multilayer build-up wiring board 100 'in which and are electrically connected by the filled via 21 was obtained (see FIG. 2 (f) and FIG. 3 (f)). As a result of confirming the alignment accuracy between the filled via 21 and the land portion 22c of the obtained high-density multilayer build-up wiring board 100 ', the positional deviation was within 15 μm.

<Comparative Example> In the same process as in Example 1, the first wiring layer 12a having a conductor layer thickness of 15 μm on both surfaces and the first wiring layer 12a
Insulating layers 14 were formed on both surfaces of the core substrate 11 on which the wiring layer 12b, the land portion 12c, and the through holes 13 were formed (see FIGS. 2A, 2B, and 3B).

Next, using the alignment mark 12d formed in the alignment mark region of the core substrate 11,
The laser beam of the laser processing machine is aligned, and the insulating layer 14 on the land portion 12c of the first wiring layer is irradiated with an ultraviolet laser having a frequency of 5 KHz and 30 pulses to form a via hole 15 having an upper diameter of 50 μmφ. A frequency of 5 KH is applied to the insulating layer 14 on the conductor layer 12e in the alignment mark area.
The hole diameter is 7 by irradiating a z, 30 pulse ultraviolet laser.
Round holes 55 for alignment marks having a diameter of 0, 100, 110, and 120 μm were formed (see FIGS. 2C and 4B).

In the same process as in Example 1, desmear treatment,
By performing electroless copper plating and electrolytic copper plating, the filled vias 21, the second conductor layer 22 having a thickness of 15 μm, and the alignment mark regions have hole diameters of 70, 100, 110, and 120 μ.
An alignment mark 63 for exposure of mφ was formed (see FIG. 2).
(D) and FIG.4 (c)).

Next, the filled via 21 and the second conductor layer 2
2, a photoresist layer is formed on the substrate 2, and the exposure mask is aligned with an exposure device using the exposure alignment mark 63 formed in the alignment mark region,
A series of patterning treatments such as development were performed to form a resist pattern 17 (see FIGS. 2E and 3E). Here, the hole diameters are 70, 100, 110 and 120.
As a result of confirming the alignment visibility of the exposure apparatus for the exposure alignment mark 63 of μmφ, the visibility was poor in all cases, and the alignment operation was unstable.

Next, the second conductor layer 22 and the thin film conductor layer are etched using the resist pattern 17 as an etching mask, the resist pattern 17 is removed by a dedicated stripping solution, and the second wiring layer 22a and the second wiring are formed. Layers 22b and 140
A land portion 22c of μmφ is formed, and the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are formed.
A high-density multilayer build-up wiring board of a comparative example in which and are electrically connected by the filled via 21 is obtained. As a result of confirming the alignment accuracy between the filled via 21 and the land portion 22c of the obtained high-density multilayer buildup wiring board of the comparative example, a positional deviation of 15 μm or more was confirmed.

[0039]

In the method for manufacturing a high-density multilayer build-up wiring board according to the present invention, the alignment accuracy of the exposure mask is adjusted by using the double ring-shaped exposure alignment mark formed on the insulating layer. You can get excellent filled via and land. Further, since the outer diameter R _D ≧ 200 μmφ and the ring width R _w ≧ 50 μm of the double ring of the exposure alignment mark are set within the range, a high-density multilayer build-up wiring board having a via-on-via structure with excellent alignment accuracy is obtained. be able to. Therefore, the present invention provides
In the field of high-density multilayer build-up wiring boards, it has excellent practical effects.

[Brief description of drawings]

FIG. 1 (a) is a schematic partial structural cross-sectional view showing an example of a high-density multilayer build-up wiring board obtained by the method for producing a high-density multilayer build-up wiring board according to the present invention. (B) is A
It is a model partial expanded structure sectional view of a field.

2 (a) to (f) are schematic partial configuration cross-sectional views showing an embodiment of a method for manufacturing a high-density multilayer buildup wiring board according to the present invention.

3 (b) to (f) are schematic partial enlarged configuration cross-sectional views of the area A of FIGS. 2 (b) to (f) and schematic partial enlarged configuration cross-sectional views showing alignment marks in the alignment mark area.

4 (a) to (e) are a schematic partial configuration cross-sectional view showing an example of a manufacturing process of a conventional multilayer build-up wiring board and a schematic partial enlarged configuration cross-sectional view showing an alignment mark in an alignment mark region.

[Explanation of symbols]

11, 51 ... Core substrate 12a, 12b, 52 ... First wiring layer 12c, 22c, 52c ... Land portion 12d, 23 ... Alignment mark for exposure 12e, 52e ... conductor layer 13-through hole 14, 53 ... Insulating layer 15, 54 ... Via holes 16: Double ring hole for alignment mark 17, 56a ... resist pattern 21, 61 …… Filled beer 22, 62 ... Second conductor layer 22a, 22b, 62a ... second wiring layer 23, 63 ... Alignment mark for exposure 100: High-density multilayer build-up wiring board

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/00 H01L 23/12 NF term (reference) 5E346 AA06 AA12 AA15 AA32 AA43 AA51 BB11 BB16 CC04 CC09 CC32 DD02 DD03 DD12 DD32 DD33 EE06 EE07 EE09 EE13 EE31 EE33 EE35 FF01 FF03 FF04 FF07 FF14 GG15 GG17 GG18 GG22 GG28 HH11 HH21

Claims (2)

[Claims] 1. A multilayer printed wiring board in which a plurality of wiring layers are formed on both sides of a core substrate having a through hole via insulating layers, and the wiring layers are electrically connected by filled vias. A method for manufacturing a high-density multi-layer build-up wiring board, comprising at least the following steps. (A) A step of forming insulating layers on both surfaces of the core substrate on which the through holes and the wiring layers are formed. (B) A step of forming via holes and alignment mark holes in the insulating layer by laser processing. (C) A step of forming a thin film conductor layer by subjecting the via hole, the alignment mark hole, and the insulating layer to a conductive treatment. (D) A step of performing electrolytic copper panel plating using the thin film conductor layer as a cathode to form a filled via, an alignment mark for exposure, and a conductor layer. (E) A step of forming a photosensitive layer on the conductor layer, performing pattern alignment using the alignment mark for exposure, and performing a series of patterning processes such as pattern exposure and development to form a resist pattern. (F) A step of forming a wiring layer by etching the conductor layer and the thin film conductor layer using the resist pattern as a mask and peeling the resist pattern. (G) A step of producing a high-density multi-layer build-up wiring board having a predetermined number of layers by repeating the above-described insulating layer, filled via, and wiring layer forming steps a necessary number of times. 2. The exposure alignment mark formed on the insulating layer has a double ring shape, and when the outer shape of the double ring is R _D and the ring width is R _w , R _D ≧ 200 μm
The method of manufacturing a high-density multilayer buildup wiring board according to claim 1, wherein the conditions of φ and R _w ≧ 50 μm are satisfied.