JP2009246144A - Electronic component-incorporating substrate and method of manufacturing the same, and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve an electronic component-incorporating substrate which maintains symmetry of the substrate even while incorporating a passive component while eliminating warpage, and to provide an electronic component-incorporating substrate that achieves stabilized connection reliability by connecting a passive component using a material accompanied by alloy formation. <P>SOLUTION: An electronic component-incorporating substrate incorporating a passive component in a resin substrate having a plurality of layers of wiring wherein the passive component is arranged in an insulating layer existing between a first wiring layer which is electrically connected with the passive component and a second wiring layer which is proximate to the first wiring layer, and the second wiring layer has an opening larger than the mounting area of the passive component. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic component built-in substrate incorporating a passive component, a manufacturing method thereof, and a semiconductor device using the electronic component built-in substrate.

  In recent years, with the increase in functionality of electronic devices, the performance of semiconductor element drive frequencies has been increased. As the frequency increases, switching in a circuit away from the power supply tends to cause a phenomenon that the voltage temporarily decreases due to the coil component or resistance component of the power supply wiring, which causes malfunction of the semiconductor element. Therefore, a decoupling capacitor is disposed between the power supply line and the ground line on the substrate on which the semiconductor element is mounted, thereby ensuring a stable power supply voltage and realizing a normal operation of the semiconductor element. However, in order to maximize the effect of this decoupling capacitor, it must be placed as close as possible to the semiconductor element so as not to be affected by the coil / resistance component of the wiring. Although it has been dealt with by placing capacitors on the mounted substrate and the mother substrate on which it is mounted, it has been decoupled from the semiconductor device even if it is placed around the semiconductor device due to the advancement of device performance. Even the routing of wiring between capacitors has been influential.

  In view of this, an electronic component built-in substrate has been proposed in which capacitor components are embedded in the substrate and short wiring has been attempted.

  Hereinafter, a conventional electronic component built-in substrate will be described with reference to FIG. FIG. 6 is a cross-sectional view of a conventional electronic component built-in substrate.

  In FIG. 6, a conventional electronic component built-in substrate 1 has an electronic component 2 built in an arbitrary insulating layer 4 of a multilayer wiring board, and the built-in electronic component 2 is connected to the wiring layer 5 by a conductive adhesive 3. They are directly connected to the wiring layer 5 by an ultrasonic connection method.

For example, Patent Document 1 and Patent Document 2 are known as prior art document information of this technology.
Japanese Patent Laid-Open No. 11-220262 JP-T-2006-519486

  In the manufacturing process of such a conventional substrate with built-in electronic components, when the built-in electronic component is a chip-type passive component such as a chip capacitor or a chip resistor, the layer in which the passive component is embedded depends on the thickness of the passive component. Although it becomes thicker, a thicker thickness than the passive component is required to completely embed the passive component, and as a result, the thickness of the electronic component built-in substrate also increases, so it is impossible to respond to the thinning required in recent years. It also had the problem of. In addition, for the purpose of making the layer containing the passive component as thin as possible, if a wiring layer that does not mount a nearby passive component is brought close to the passive component, it causes electrical coupling between the passive component and the adjacent wiring layer, In order to cause the problem of deteriorating the electric characteristics as a stray capacitance, the layer containing the passive component cannot be thinned.

  Accordingly, an object of the present invention is to solve the above-described conventional problems, and to provide an electronic component built-in substrate excellent in electrical characteristics and cost / mass productivity, and a semiconductor device using the same.

  To achieve the above object, an electronic component built-in substrate according to the present invention is an electronic component built-in substrate in which a passive component is built in a resin substrate having a plurality of layers of wiring, and the passive component is electrically connected to the passive component and the electric component. Disposed in an insulating layer existing between the first wiring layer connected to the first wiring layer and the second wiring layer adjacent to the first wiring layer, and the second wiring layer is at least larger than the mounting area of the passive component An electronic component-embedded substrate having an opening having an area is provided.

  With the above configuration, by forming a space larger than the mounting area of the passive component in the second wiring layer, the second wiring layer is not in contact with the passive component when the passive component is disposed in the insulating layer. It is possible to reduce the thickness of the insulating layer to approximately the same thickness as that of the passive component without causing electrical coupling between the layer and the passive component. Can be realized.

(Embodiment 1)
Embodiments of an electronic component built-in substrate, a method of manufacturing the same, and a semiconductor device using the same according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of an electronic component built-in substrate according to Embodiment 1 of the present invention.

  In the electronic component built-in substrate 100 of the first embodiment, as shown in FIG. 1, a passive component 103 such as a chip capacitor or a chip resistor is electrically and mechanically connected to a first wiring layer 101 by a mounting material 105. And disposed in an insulating layer 106 sandwiched between the first wiring layer 101 and the second wiring layer 102. However, the passive component 103 is never arranged at a position sandwiched between the first wiring layer 101 and the second wiring layer 102. That is, the wiring pattern is not present in the portion corresponding to the second wiring layer 102 on the upper surface portion of the passive component 103 when viewed from the first wiring layer 101, and only the insulating layer 106 is present. . Therefore, when the passive component 103 is disposed in the insulating layer 106, the second wiring layer 102 and the passive component 103 are not brought into contact with the passive component 103 and the second wiring layer 102 and the passive component 103 are interposed via the insulating layer 106. It is possible to reduce the thickness of the insulating layer 106 to substantially the same thickness as that of the passive component 103 without causing stray capacitance that is not designed to be electrically coupled. Thus, the electronic component has excellent electrical characteristics and is thin. A built-in substrate can be realized.

  The first wiring layer 101 and the second wiring layer 102 are made of a material having electrical conductivity, and are made of, for example, a copper (Cu) foil or a conductive resin composition. In the present invention, the Cu foil is formed by patterning into a desired shape. The insulating material used for the insulating layer 106 includes a glass epoxy prepreg in which a glass woven fabric is impregnated with a thermosetting epoxy resin, a BT resin prepreg in which a glass woven fabric is impregnated with a thermosetting bismaleimide / triazine resin, and an aramid. It is possible to use aramid prepreg with nonwoven fabric impregnated with thermosetting epoxy resin, but various materials should be used as long as it is a structure in which woven fabric or nonwoven fabric is impregnated with thermosetting resin. Is possible. In addition to a prepreg material obtained by impregnating a woven or non-woven fabric with a thermosetting resin, it is also possible to use a mixture of an inorganic filler such as silicon dioxide or alumina and a thermosetting resin.

  The passive component 103 is a chip-type electronic component that is formed in advance with desired characteristics such as a chip capacitor and a chip resistor and has a connection electrode 104 on the outer surface. The mounting material 105 is a material in which at least two kinds of metal elements are blended, and can be electrically and mechanically connected with an alloy connection between the metals, for example, tin (Sn) -silver (Ag) system. , Tin (Sn) -silver (Ag) -copper (Cu), tin (Sn) -zinc (Zn), gold (Au) -zinc (Zn), tin (Sn) -antimony (Sb), etc. However, the present invention is not limited to these materials, and any material can be used as long as it is a material capable of mounting the passive component 103. Further, the melting point of the alloy in the material may be a melting point change type material composition that shifts to a high temperature side after joining.

  The reason why an alloy-connectable material is used for the mounting material 105 is to stably connect the passive component 103 to the first wiring layer 101. That is, in recent years, the electrode 104 of a chip-type electronic component such as a chip capacitor or a chip resistor is mainly made of Sn plating on the outermost surface in consideration of environmental problems. When a conductive adhesive mainly composed of powder is used for the mounting material 105, the connection method of the passive component 103 by the conductive adhesive is only a pressure contact connection by curing shrinkage of the thermosetting resin in the conductive adhesive. Therefore, Ag in the conductive adhesive and Sn of the electrode 104 of the passive component 103 are simply in contact with each other and are electrically connected to each other. However, when the melting point of Sn exceeds 232 ° C., it is easy. Ag is diffused into Sn, Ag in the conductive adhesive disappears, and connection reliability is deteriorated. It is also a very difficult technique to directly connect the electrode 104 on which Sn, which is a relatively low melting point metal, is directly connected to the first wiring layer 101 using ultrasonic waves.

  However, for these connection technologies, by selecting a material that can be connected to the mounting material 105 with Sn on the surface of the electrode 104 and a metal bond, even if it is exposed to a temperature environment exceeding 232 ° C., it is conductive. It is possible to stabilize the connection reliability without causing diffusion to Sn on the electrode 104 side like an adhesive. Then, by blending at least two kinds of metal elements into the mounting material 105, it is possible to realize a desired melting point of the mounting material 105 that cannot be achieved with a single metal in order to mount the passive component 103. It can be done.

  However, any material is required to have poor wettability with respect to the first wiring layer 101. The reason for mounting the passive component 103 on the first wiring layer 101 is that the connection cannot be made unless the mounting material 105 is securely stopped on the first wiring layer 101. It is important that the mounting material 105 is a material that does not contain lead (Pb), which is an environmental pollutant.

  Using the two-layer wiring board composed of the first wiring layer 101, the insulating layer 106, and the second wiring layer 102 as a central material, an insulating layer 107, a surface wiring layer 108, and a back wiring layer 109 are formed on both outer surfaces. Multi-layered. When the layers are formed, the surface wiring layer 108, the first wiring layer 101, the second wiring layer 102, and the back wiring layer 109 are electrically connected through the through holes 110.

  Although the first embodiment shows an example of a four-layer substrate, it is not fixed to the four-layer substrate, and an even number of layers can be formed as required. However, even at that time, the wiring layers are formed simultaneously on both sides with a two-layer wiring board containing the passive component 103 as a central material. The insulating material used for the insulating layer 107 formed on the outside is a glass epoxy prepreg in which a glass woven fabric is impregnated with a thermosetting epoxy resin, and the glass woven fabric is a thermosetting bismaleimide / triazine resin, as with the insulating layer 106. It is possible to use a BT resin prepreg impregnated with an aramid prepreg, an aramid prepreg impregnated with a thermosetting epoxy resin in an aramid non-woven fabric, etc. Various materials can be used. In addition to a prepreg material obtained by impregnating a woven or non-woven fabric with a thermosetting resin, it is also possible to use a mixture of an inorganic filler such as silicon dioxide or alumina and a thermosetting resin.

  In order to prevent warping of the substrate after lamination, it is very important to consider the linear expansion coefficient of each material. Similarly to the first wiring layer 101 and the second wiring layer 102, the surface wiring layer 108 and the back wiring layer 109 are made of a material having electrical conductivity, for example, a Cu foil or a conductive resin composition. In the present invention, a Cu wiring is used as a base, and a Cu plating film deposited when forming the through hole 110 is patterned simultaneously with the base Cu foil to form a desired wiring pattern.

  A solder resist 111 is formed on the surface wiring layer 108 and the back wiring layer 109 as necessary. When forming the solder resist 111, it is important that the solder resist 111 is filled with a conductive material or an insulating material so that no space remains in the through hole 110. In the first embodiment, the through hole 110 is directly filled with the solder resist 111. However, the structure is not limited to the solder resist 111, and various materials can be used as long as the material has a low moisture absorption rate and a low linear expansion coefficient. It is possible to use.

  Next, an embodiment of a method for manufacturing an electronic component built-in substrate according to the present invention will be described with reference to the drawings.

  FIG. 2 is a manufacturing process sectional view of the electronic component built-in substrate according to the first embodiment of the present invention.

  As shown in FIG. 2A, a Cu foil 201 is prepared. It is desirable that at least one side of the Cu foil 201 is appropriately roughened. This is to cause an anchor effect to the insulating material 112 when bonding to the insulating material 112 that forms the insulating layer 106 in the subsequent process. This is because almost no adhesive force can be expected in bonding.

  Next, as shown in FIG. 2B, a mounting material 105 is applied on the roughened surface of the Cu foil 201 at a desired interval using stencil printing, a dispenser, or the like. In addition, in the process of applying the mounting material 105 on the Cu foil 201, if it is difficult to handle the Cu foil 201 alone, reinforcement of a film, a substrate, or the like on the surface of the Cu foil 201 on which the mounting material 105 is not applied. A material (not shown) is attached using an adhesive or the like to stabilize the planarity of the Cu foil 201. However, when a reinforcing material is pasted, the surface of the Cu foil 201 to which the reinforcing material is pasted is preferably a glossy surface state. This is because it is necessary to remove the reinforcing material in a later step, but if this surface is roughened, it is difficult to remove the reinforcing material.

  Next, as shown in FIG. 2C, a passive component 103 such as a chip capacitor or a chip resistor is mounted on a desired position of the mounting material 105 on the Cu foil 201, and the Cu foil 201, The mounting material 105 and the electrode 104 of the passive component 103 are electrically and mechanically connected together with an alloy connection. At this time, the mounting material 105 must be prevented from wetting and spreading from the application position shown in FIG.

  Next, as shown in FIG. 2D, the insulating material 112 in which the space 206 is formed and the Cu foil 202 in which the space 212 is formed are superimposed on a predetermined position on the Cu foil 201 on which the passive component 103 is mounted. At this time, it is important that the space 206 is formed larger than the area where the passive component 103 is mounted so that the insulating material 112 and the passive component 103 do not come into contact with each other. When a plurality of passive components 103 are adjacent to each other, the space 206 may be one large space 206 so as to surround all the adjacent passive components 103. In addition, it is important that the space 212 formed in the Cu foil 202 is formed larger than the area where the passive component 103 is mounted so as not to contact the passive component 103. And the space 212 is good also as the one large space 212 so that all the adjacent passive components 103 may be enclosed similarly to the space 206. FIG. In addition, the thickness of the insulating material 112 is set so that the passive component 103 is completely embedded. However, since the Cu foil 202 disposed on the passive component 103 has a space 212, the passive component 103 and the Cu foil 202 are disposed. It is possible to set the insulating material 112 to a thickness substantially equal to the height of the passive component 103 mounted on the Cu foil 201 from above the Cu foil 201 without contacting them. Note that the insulating material 112 may be formed by stacking one thick material, but a method of securing a desired thickness by stacking a plurality of materials may be employed. Further, similarly to the Cu foil 201, at least one surface side of the Cu foil 202 is appropriately roughened, and the roughened surface side is desirably disposed on the insulating material 112 side. This is to cause an anchor effect to the insulating material 112 when it is bonded to the insulating material 112 in the subsequent process. In the bonding between the glossy surface that is not roughened and the insulating material 112, the adhesive force is low. Because it can hardly be expected.

  Next, as shown in FIG. 2 (e), the superposed material shown in FIG. 2 (d) is pressed and integrated with heating using a hot platen press device (not shown), and the insulating material 112 is integrated. The passive component 103 is embedded in the insulating layer 106 formed by heating and pressing. At this time, the thickness of the insulating layer 106 must be set so that the passive component 103 is completely embedded in the insulating layer 106 after integration, and the pressure condition of a hot platen press apparatus (not shown) must be set. . It is also important to completely cover the passive component 103 with the insulating layer 106 without generating bubbles around the passive component 103. In the case where an auxiliary material (not shown) is pasted on the Cu foil 201, after the passive component 103 shown in FIG. 2C is mounted or the Cu foil 201 and the insulating layer 106 shown in FIG. Later, an auxiliary material (not shown) is peeled from the Cu foil 201.

  Next, as shown in FIG. 2 (f), the Cu foil 201 and the Cu foil 202 are processed into desired shapes to form the first wiring layer 101 and the second wiring layer 102, thereby producing a two-layer wiring board. . In addition, when the single-sided roughened foil is used for the Cu foil 201 and the Cu foil 202, the surfaces facing the outside of the first wiring layer 101 and the second wiring layer 102 are roughened, etc. It is important to adjust the connection to the insulating material 113 so that the connection with the insulating material 113 can be performed satisfactorily.

  Next, as shown in FIG. 3A, the insulating material 113 and the Cu foil 208 are superimposed on the front and back surfaces around the two-layer wiring board produced in FIG. As shown, it is pressed and integrated using a hot platen press (not shown) while heating. In the Cu foil 208 as well, like the Cu foils 201 and 202, it is desirable that at least one side is appropriately roughened and the roughened surface side is disposed on the insulating material 113 side.

  Next, as shown in FIG. 3 (c), a through hole 210 is formed at a desired position, and as shown in FIG. 3 (d), plating 220 is applied. The first wiring layer 101 and the second wiring layer 102 confined in the insulating layer 107 formed by heating and pressing the insulating material 113 are electrically connected.

  Thereafter, as shown in FIG. 4A, the Cu foil 208 having the plating 220 formed on the surface thereof is processed into a desired shape simultaneously with the plating 220 to form the surface wiring layer 108 and the back wiring layer 109, and the electron The component built-in substrate 100 is formed. Further, if necessary, a solder resist 111 may be formed on the front and back surfaces of the electronic component built-in substrate 100 as shown in FIG. However, when the solder resist 111 is formed, it is important that the solder resist 111 is filled with a conductive material or an insulating material so that no space remains in the through hole 110. Note that the material filled in the through hole 110 may be the same material as the solder resist 111 formed on the front and back surfaces.

  Hereinafter, the characteristics of the electronic component built-in substrate and the manufacturing method thereof shown in the first embodiment will be described.

  In the electronic component built-in substrate and the manufacturing method thereof according to the present invention, the second wiring layer is formed when the passive component is disposed in the insulating layer by forming a space larger than the mounting area of the passive component in the second wiring layer. The thickness of the insulating layer is approximately equal to the thickness of the passive component without causing contact with the passive component and without causing a stray capacitance outside the design where the second wiring layer and the passive component are electrically coupled via the insulating layer. It is possible to reduce the thickness to a thickness, and it is possible to realize an electronic component built-in substrate having excellent electrical characteristics and a small thickness. Further, by using the Cu foil 201 as a starting material, the electronic component built-in substrate 100 can be manufactured by a manufacturing process substantially equivalent to that of a general printed wiring board, and the built-in passive component 103 is replaced by the electronic component built-in substrate 100. Since it is arranged in the central insulating layer with respect to the stacking direction, even the electronic component built-in substrate 100 incorporating the passive component 103 maintains the symmetry of the substrate and realizes the electronic component built-in substrate 100 without warping. Furthermore, stable connection reliability can be realized by connecting the passive component 103 with a material accompanied by alloy formation.

(Embodiment 2)
Hereinafter, Embodiment 2 according to the present invention will be described with reference to the drawings. FIG. 5 is a sectional view of a semiconductor device according to the second embodiment of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  As shown in FIG. 5, the semiconductor device 200 according to the second embodiment is formed by sealing the resin 121 after mounting the semiconductor 121 at a desired position on the surface wiring layer 108 of the electronic component built-in substrate 100 manufactured in the first embodiment. 123 covers the semiconductor surface. In the second embodiment, the semiconductor 121 shows a flip chip mounting structure with bumps 122 interposed. However, the mounting method of the semiconductor 121 is not limited to the flip chip mounting. A simple connection method may be used.

  What is important in the semiconductor device 200 shown in the second embodiment is that the first wiring layer 101 to which the passive component 103 of the electronic component-embedded substrate 100 is connected is the first wiring layer 108 on which the semiconductor 121 is mounted. When the total number of layers up to the backside wiring layer 109 is n layers, it is the n / 2th layer from the first layer. In FIG. 5, the second layer corresponds to the four-layer substrate. The n / 2 layer is a layer on which a ground wiring pattern is mainly formed. The second wiring layer 102 which is the (n / 2 + 1) th layer (the third layer in FIG. 5) from the surface layer wiring layer 108 is It is mainly configured as a layer in which a power supply line is formed.

  This makes it possible to arrange the passive component 103 with the shortest wiring with respect to the semiconductor 121 while preventing the warpage of the electronic component built-in substrate 100. When the passive component 103 is a chip capacitor, the semiconductor Effective decoupling can be achieved by reducing the coil and resistance components that come from the wiring length for high-speed switching operation, and avoiding unnecessary electrical coupling between the passive component 103 and the second wiring layer 102. It can function as a capacitor, and the function as the semiconductor device 200 can be improved.

  The reason why the n / 2th layer on which the passive component 103 is mounted is the ground layer and the (n / 2 + 1) th layer is the power supply layer is that the ground layer is an electrically stable reference layer. The formation of an inadvertent disconnection part leads to deterioration of electrical characteristics. Therefore, it is necessary to pay particular attention to the method of forming the wiring turn. On the other hand, as for the power supply layer, there are many recent semiconductors. As functionalization progresses and even a single semiconductor requires a plurality of different drive voltages, a wiring pattern considering a plurality of power supply voltages is required. Therefore, even if the wiring area on the passive component 103 is deleted as in the second wiring layer 102, the deleted portion is used as a disconnection portion for power supply division, so that the power supply characteristics are not deteriorated. Since unnecessary electrical coupling between the passive component 103 and the second wiring layer 102 as a power supply layer can be avoided, the effect is great.

  The electronic component built-in substrate, the semiconductor device using the same, and the method for manufacturing the same according to the present invention are easy to put into practical use because of low cost and excellent mass productivity, and are useful as a semiconductor device that can cope with a higher driving frequency of the semiconductor. .

Sectional drawing of the electronic component built-in substrate in Embodiment 1 of this invention (A)-(f) Manufacturing process sectional drawing of the electronic component built-in board | substrate in Embodiment 1 of this invention. (A)-(d) Manufacturing process sectional drawing of the electronic component built-in board | substrate in Embodiment 1 of this invention. (A), (b) Manufacturing process sectional drawing of the electronic component built-in board in Embodiment 1 of this invention Sectional drawing of the semiconductor device in Embodiment 2 of this invention Sectional view of a conventional electronic component built-in substrate

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Electronic component built-in board 101 1st wiring layer 102 2nd wiring layer 103 Passive component 104 Electrode 105 Mounting material 106 Insulating layer 107 Insulating layer 108 Surface layer wiring layer 109 Back surface wiring layer 110 Through-hole 111 Solder resist 112 Insulating material 113 Insulating material 121 Semiconductor 122 Bump 123 Sealing Resin 200 Semiconductor Device 201 Copper Foil 202 Copper Foil 206 Space 208 Copper Foil 210 Through Hole 212 Space 220 Plating

Claims (17)

An electronic component built-in substrate in which a passive component is built in a resin substrate having a plurality of layers of wiring, wherein the passive component is electrically connected to the first wiring layer and the first wiring layer electrically connected to the passive component. An electronic component built-in substrate disposed in an insulating layer existing between adjacent second wiring layers, wherein the second wiring layer has an opening having an area larger than at least a mounting area of the passive component. The electronic component built-in substrate according to claim 1, wherein the insulating layer is disposed in a central layer of the plurality of layers of the electronic component built-in substrate. 3. The electronic component built-in according to claim 1, wherein the passive component is connected to the first wiring layer using a material in which at least two kinds of metal materials form an alloy and are electrically and mechanically connected. substrate. The electronic component built-in substrate according to claim 1, wherein a thickness of the insulating layer is larger than a thickness of the passive component. The electronic component built-in substrate according to claim 1, wherein the passive component is a chip capacitor. The electronic component built-in substrate according to claim 1, wherein the passive components are a chip capacitor and a chip resistor. The semiconductor device which mounted the semiconductor in the surface wiring layer of the electronic component built-in board | substrate which incorporates the passive component as described in any one of Claims 1-6. The plurality of wiring layers are composed of an even number of n layers. When the surface layer wiring layer for mounting the semiconductor is used as a first layer and the layers are ordered up to the n layer, the passive component is placed on the n / 2th layer. The semiconductor device according to claim 7, wherein: The semiconductor device according to claim 7, wherein the passive component is a chip capacitor. 9. The semiconductor device according to claim 7, wherein the passive components are a chip capacitor and a chip resistor. The semiconductor device according to claim 7, wherein the first wiring layer is a layer in which an electrical ground layer is mainly formed. The semiconductor device according to claim 7, wherein the second wiring layer is a layer in which a power supply line is mainly formed. Applying a passive component mounting material on the copper foil;
Mounting a passive component on the passive component mounting material;
Stacking an insulating material having a larger space than the passive component on the copper foil on which the passive component is already mounted;
Stacking a second copper foil having a space larger than the passive component on the insulating material;
After the copper foil, the insulating material and the second copper foil are pressed and integrated while being heated, the copper foil is processed into a desired first wiring layer and the second copper foil is A method of manufacturing an electronic component built-in substrate comprising: a step of forming a two-layer wiring board by processing into a second wiring layer; and a step of forming a multilayer wiring layer by disposing the two-layer wiring board in a central portion. The method for manufacturing a substrate with built-in electronic components according to claim 13, wherein the multilayer wiring layers are electrically connected by through-hole connection. The method for manufacturing an electronic component-embedded substrate according to claim 13 or 14, wherein the passive component mounting material is a material in which at least two kinds of metal materials are electrically and mechanically connected by forming an alloy. 16. The method of manufacturing an electronic component built-in substrate according to claim 15, wherein the passive component is a chip capacitor. The method for manufacturing a substrate with built-in electronic components according to claim 15, wherein the passive components are a chip capacitor and a chip resistor.

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