JP2019195108A - Multilayer wiring structure and semiconductor device using multilayer wiring structure - Google Patents

Abstract

To provide a multilayer wiring structure having improved resistance to peeling between a wiring layer and an insulating layer.SOLUTION: A multilayer wiring structure includes a plurality of wiring layers and a plurality of insulating layers that insulate the respective wiring layers, and is provided with a multilayer wiring circuit that includes a first region, a second region adjacent to the first region, and a third region adjacent to the second region, and that is provided in the first region. The plurality of insulating layers extend from the first region to the second region, a part of the plurality of wiring layers do not exist in the second region, and the plurality of insulating layers extend from the second region to the third region, and at least a part of the plurality of other wiring layers extending from the first region to the second region do not exist in the third region, and adjacent insulating layers of the plurality of insulating layers are in contact with each other.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a multilayer wiring structure, and one disclosed embodiment relates to a laminated structure of a substrate and a multilayer wiring structure.

  In recent years, with the performance enhancement of integrated circuits, integrated circuits have become more complex, and the number of elements such as transistors constituting the integrated circuit has increased. As the number of elements increases, the arrangement of wirings that connect the elements also becomes complicated, and the area occupied by the wirings in the integrated circuit substrate increases. Therefore, in an integrated circuit board, in order to reduce the occupied area in the plane direction of the wiring as much as possible, development of a multilayer wiring technique in which a plurality of wirings are stacked and the wirings are routed three-dimensionally is being promoted (for example, Patent Document 1). ).

JP 2006-173333 A

  However, there is a difference in the coefficient of thermal expansion of each layer in the thermal cycle (heat treatment process) between the region where the wirings are stacked and the region where only the insulating layers that insulate the stacked wires are not stacked. Occurs. Due to the difference in coefficient of thermal expansion, internal stress is concentrated near the boundary between the region where the wiring is laminated and the region where only the insulating layer is laminated, and there is a problem that cracks are caused by the internal stress.

  The present invention has been made in view of the above-described problems, and provides a multilayer wiring structure in which the generation of cracks is suppressed and a high production yield can be obtained.

  A multilayer wiring structure according to an embodiment of the present invention includes a first region including a plurality of first wiring layers provided on a substrate and a plurality of first insulating layers that insulate each of the plurality of first wiring layers. A second wiring layer adjacent to the first region and having a volume density lower than that of the plurality of first wiring layers, and a plurality of second insulating layers that are the same layer as each of the plurality of first insulating layers. A third region including a second region, a second region, and a plurality of third insulating layers adjacent to the end of the substrate and the same layer as each of the plurality of first insulating layers, each of which is stacked in contact with each other. Area.

  With such a structure, it is possible to provide a multilayer wiring structure in which stress in the insulating layer between the wiring layers is relaxed, cracks are suppressed, and a high production yield can be obtained.

  The second wiring layer of the multilayer wiring structure according to the embodiment of the present invention includes a first wiring extended from the first region.

  With such a structure, it is possible to provide a multilayer wiring structure in which stress in the insulating layer between the wiring layers is relaxed, cracks are suppressed, and a high production yield can be obtained.

  The second wiring layer of the multilayer wiring structure according to the embodiment of the present invention is electrically independent of the multilayer wiring circuit and is disposed in the same layer as at least one of the plurality of first wiring layers. Is further included.

  With such a structure, it is possible to provide a multilayer wiring structure in which stress in the insulating layer between the wiring layers is relaxed, cracks are suppressed, and a high production yield can be obtained.

  The second wiring layer of the multilayer wiring structure according to the embodiment of the present invention is electrically independent of the multilayer wiring circuit and is disposed in the same layer as at least one of the plurality of first wiring layers. It is.

  With such a structure, it is possible to provide a multilayer wiring structure in which stress in the insulating layer between the wiring layers is relaxed, cracks are suppressed, and a high production yield can be obtained.

  In another preferred embodiment, the pseudo wiring layer may be a plurality of discretely arranged wirings.

  With such a structure, it becomes easier to relieve stress in the insulating layer between the wiring layers.

  In another preferred embodiment, the occupation area ratio of the plurality of discretely arranged wiring layers may be 10% or more and 80% or less.

  With such a structure, it becomes easier to relieve stress in the insulating layer between the wiring layers.

  In another preferred embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may include an organic insulating layer.

  By adopting such a structure, the flatness of the insulating layer between the wiring layers is improved, and the resistance to peeling between the insulating layer and the wiring between the wiring layers is improved.

  In another preferred embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may include an inorganic insulating layer.

  With such a structure, diffusion of the conductive material in the wiring layer can be suppressed.

  In another preferred embodiment, the second region may include a region 5 μm from the boundary with the first region.

  With such a structure, the stress in the insulating layer between the wiring layers can be efficiently relaxed.

  In another preferred embodiment, the first wiring layer, the second wiring layer, and the pseudo wiring layer may have a stacked structure including a plurality of conductive layers.

  By adopting such a structure, it is possible to suppress the resistance of the entire wiring by selecting a metal material having a low electric resistance, and further by combining a metal material having a barrier property against the metal material having a low electric resistance, It is possible to prevent diffusion of metal in the multilayer wiring structure.

  A semiconductor device according to an embodiment of the present invention has a multilayer wiring structure according to an embodiment of the present invention.

  Separation hardly occurs between the wiring layer and the insulating layer between the wiring layers, and a semiconductor device having a multilayer wiring structure with improved reliability can be provided.

  ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of a crack can be suppressed and the multilayer wiring structure which can obtain a high production yield can be provided.

It is a schematic diagram which shows the upper surface of the multilayer wiring structure which concerns on one Embodiment of this invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the section of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the plane of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the plane of the multilayer wiring structure concerning one embodiment of the present invention. It is a mimetic diagram showing the plane of the multilayer wiring structure concerning one embodiment of the present invention. It is the example of arrangement | positioning of the pseudo wiring arrange | positioned in the 2nd area | region in the multilayer wiring structure of this invention. It is a schematic diagram which shows the upper surface of the multilayer wiring structure by a comparative example. 5 is a plan photograph showing peeling of a wiring layer and an insulating layer in a multilayer wiring structure according to a comparative example. It is a cross-sectional photograph which shows peeling with a wiring layer and an insulating layer in the multilayer wiring structure by a comparative example. 14B is an enlarged photograph of the cross-sectional photograph of FIG. 14A. It is an example of arrangement | positioning of the wiring arrange | positioned in the 1st area | region in a multilayer wiring structure. It is a figure explaining the structure of the multilayer wiring structure used for the experiment which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention. It is a figure explaining the pattern of the pseudo | simulated broken line of the multilayer wiring structure used for the experiment which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention. It is a figure explaining the multilayer wiring structure used for the experiment which concerns on this invention. It is a figure explaining the multilayer wiring structure used for the experiment which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention. It is a graph explaining the experimental result which concerns on this invention.

  The multilayer wiring structure of the present invention will be described in detail below with reference to the drawings. The multilayer wiring structure of the present invention is not limited to the following embodiments, and can be implemented with various modifications. In all the embodiments, the same components are described with the same reference numerals. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

<First Embodiment>
The configuration of the multilayer wiring structure according to the first embodiment of the present invention will be described below with reference to FIGS.

[Configuration of multilayer wiring structure]
FIG. 1 is a plan view of the multilayer wiring structure according to the first embodiment of the present invention, and shows the vicinity of the end of the substrate 100. The multilayer wiring structure according to the present embodiment is characterized in that three regions are arranged on the plane of the substrate 100, and these regions are referred to as a first region 301, a second region 302, and a third region 303, respectively. The second region 302 is adjacent to the first region, and the third region is adjacent to the second region and the edge of the substrate 100. In other words, the second region 302 is disposed between the first region 301 and the third region 303 and separates the first region 301 and the third region 303. In other words, the second region 302 is disposed between the first region 301 and the third region 303, defines the first region 301 and the third region 303, and separates the first region 301 and the third region 303. ing.

  A multilayer wiring circuit is disposed in the first region 301. In the second area 302, a part of the wiring layer of the multilayer wiring circuit arranged in the first area is extended. In the third region 303, no wiring layer is disposed, and each of a plurality of insulating layers that are the same layer as the first region 301 is laminated in contact therewith.

  2 and 3 are cross-sectional views of the multilayer wiring structure taken along the lines AB and CD of FIG. 1, respectively. A-B in FIG. 1 is the first region 301, and CD extends over the first region 301, the second region 302, and the third region 303. 2 and 3, D1 is one direction in the substrate plane, D2 is one direction in the substrate plane orthogonal to D1, and D3 is the thickness direction of the substrate.

  Referring to the cross-sectional view taken along the line AB in FIG. 2, the first to fifth wiring layers (110, 120, 130, 140, 150) and the wirings of the first to fifth wiring layers are formed on the substrate 100. The first to fourth insulating layers (119, 129, 139, 149) for isolating the layers are connected to the adjacent wiring layers among the first to fifth wiring layers (110, 120, 130, 140, 150). A multilayer wiring structure having first to fourth vias (191, 192, 193, 194) is formed. An insulating base layer 101 that isolates the substrate 100 and the first wiring layer 110 is formed between the substrate 100 and the first wiring layer 110 that is the lowermost wiring layer of the multilayer wiring structure. The layer 110 and the substrate 100 are electrically insulated.

  The fifth wiring layer 150 is connected to the uppermost sixth wiring layer 160 through an opening 185 provided in the fifth insulating layer 159.

  On the other hand, FIG. 3 shows a cross-sectional view along the line CD in FIG. 1, and CD passes through the first region 301, the second region 302, and the third region in the vicinity of the edge of the substrate 100. In the wiring layer and the insulating layer in FIGS. 2 and 3, the same reference numerals are given to the same layers. Referring to FIG. 3, the first region 301 includes first to fifth wiring layers (110, 120, 130, 140, 150) and first to fifth wiring layers (110, 120, 130, 140, 150). ), A multilayer wiring circuit having first to fourth insulating layers (119, 129, 139, 149) for isolating each of the fifth wiring layer 150 and a fifth insulating layer 159 disposed on the fifth wiring layer 150 is disposed. Yes. The first to fifth wiring layers (110, 120, 130, 140, 150) are wirings for supplying a power supply potential and a common potential, for example. In this embodiment, as a preferred example of the layer structure of each wiring layer, a copper (Cu) is used as a wiring material, and a three-layer structure of polyimide / silicon oxide (SiO) / silicon nitride (SiN) is used as an insulating layer. .

  Of the first to fifth wiring layers (110, 120, 130, 140, 150) of the first region 301, the first wiring layer 110 and the second wiring layer 120 are extended in the second region 302. ing. The first to fifth insulating layers (119, 129, 139, 149, 159) extended from the first region 301 are stacked, and the first insulating layer 119 is extended to the first wiring layer 110. In addition, the second wiring layer 120 is isolated.

  In the third region 303, no wiring layer is disposed, and the same insulating layer as each of the first to fifth insulating layers (119, 129, 139, 149, 159) in the first region 301 is in contact. Are stacked.

  In the second region 302, the uppermost fifth insulating layer 159 is formed to be lower than the first region 301 because the number of wiring layers is smaller than that in the first region 301.

  Further, in the third region 303, the wiring layer is not disposed, so that the height of the uppermost fifth insulating layer 159 is lower than that of the second region 302.

  That is, according to the present embodiment, the second region 302 adjacent to the first region 301 in which the multilayer wiring circuit is arranged is provided, the number of wiring layers is smaller than that of the first region 301, and the first region 301 is extended. By disposing the wiring layer, the gradient of the insulating layer due to the height difference between the first region 301 and the third region 303 can be reduced.

  As a result, the stress generated along with the gradient of the insulating layer can be dispersed near the both ends of the second region 302 or in the second region 302 and relaxed. Accordingly, it is possible to provide a multilayer wiring structure and a semiconductor device using the multilayer wiring structure in which cracks are hardly generated between the wiring layer and the insulating layer and a high production yield can be obtained.

  Here, the second region 302 to be secured preferably includes a region of 5 μm from the boundary with the first region 301. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, although the multilayer wiring circuit arrange | positioned in the 1st area | region 301 in this embodiment has five wiring layers (110, 120, 130, 140, 150), it is not limited to this. A multilayer wiring circuit having a plurality of wiring layers and a plurality of insulating layers that insulate each of the plurality of wiring layers can be applied.

  In the present embodiment, the first wiring layer 110 and the second wiring layer 120, which are two wiring layers, are extended from the lowermost layer of the first region 301 to the second region 302. It is not limited. The wiring layer disposed extending to the second region 302 may be disposed so as to reduce the height difference between the first region 301 and the second region 302. That is, the wiring layer disposed in the second region only needs to be smaller than the volume density of the wiring layer disposed in the first region. In addition, the number of wiring layers extended from the first region 301 may be less than the number of wiring layers in the first region 301 and extended from at least one of the layers. Further, the wiring layer extended from the first region 301 does not have to be a combination of wiring layers continuous from the lowermost layer as shown in the present embodiment, and may be an arbitrary combination.

  The configuration of the multilayer wiring structure according to the present embodiment will be described in more detail. In FIG. 2, the first wiring layer 110 has a first conductive layer 111 and a second conductive layer 112. The second conductive layer 112 is preferably a metal material with low electrical resistance. For example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), or the like can be used. Alternatively, an aluminum alloy such as an aluminum-neodymium alloy (Al—Nd) or an aluminum-copper alloy (Al—Cu) can be used. As the first conductive layer 111, it is preferable to use a material having adhesiveness and a barrier property to the second conductive layer 112. For example, when Cu is used as the second conductive layer 112, the first conductive layer 111 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), or the like. Can be used.

  In this embodiment, the laminated structure of two conductive layers is exemplified as the wiring layer. However, the present invention is not limited to this structure, and a single-layer structure of one conductive layer may be used, and three or more conductive layers may be used. A laminated structure of layers may be used.

  In FIG. 2, the first insulating layer 119 includes a first inorganic insulating layer 113, a second inorganic insulating layer 114, and a first organic insulating layer 115. The first inorganic insulating layer 113 is formed so as to cover the first conductive layer 111, the second conductive layer 112, and the exposed underlayer 101. The second inorganic insulating layer 114 is formed so as to cover the first inorganic insulating layer 113, and the first organic insulating layer 115 is further formed thereon. Here, the dielectric constant of the first organic insulating layer 115 is preferably lower than the dielectric constant of each of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Note that the first insulating layer 119 is not limited to the above three-layer structure, and may be configured to include at least one organic insulating layer or inorganic insulating layer.

The first inorganic insulating layer 113 is preferably made of a material having a barrier property with respect to the second conductive layer 112. In other words, the first inorganic insulating layer 113 is preferably made of a material having a slower diffusion rate of the second conductive layer 112 than the second inorganic insulating layer 114 and the first organic insulating layer 115. For example, when Cu is used as the second conductive layer 112, the first inorganic insulating layer 113 includes silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC). Silicon nitride carbide (SiCN), carbon-added silicon oxide (SiOC), or the like can be used. The first inorganic insulating layer 113 is preferably formed under film formation conditions with good coverage. Further, when Cu is used as the second conductive layer 112 and SiN is used as the first inorganic insulating layer 113, it is preferable that the film has a certain thickness or more in order to obtain a Cu diffusion preventing function. Since the ratio is as high as 7.5, it is preferable to set the film thickness to a certain value or less in order to suppress parasitic capacitance between wiring layers. Specifically, the thickness of the SiN film is preferably 10 nm or more and 200 nm or less. More preferably, it is 50 nm or more and 100 nm or less.

  The first inorganic insulating layer 113 preferably prevents the first inorganic insulating layer 113 from being cracked or a region having a rough film at the step formed by the first wiring layer 110. For example, the first inorganic insulating layer 113 is desirably formed under a condition where the deposition temperature is high, and is preferably 200 ° C. or higher. More preferably, it is good at 250 degreeC or more. Further, in order to improve the coverage of the first inorganic insulating layer 113, the end surface of the first wiring layer 110 may have a forward taper shape inclined with respect to the surface of the base layer 101. The taper angle of the first wiring layer 110 is preferably 30 degrees or more and 90 degrees or less. More preferably, it is 30 degrees or more and 60 degrees or less. Here, both the first conductive layer 111 and the second conductive layer 112 included in the first wiring layer 110 do not have to have a forward taper shape, and any one of them may be a forward taper shape.

The second inorganic insulating layer 114 is preferably made of a material having good adhesion to the first inorganic insulating layer 113 and the first organic insulating layer 115 formed thereon. For example, as the second inorganic insulating layer 114, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like can be used. The second inorganic insulating layer 114 is preferably formed under film formation conditions with good coverage. Further, the SiO ₂ film preferably has a film thickness of a certain level or more for adjusting the warpage of the substrate and improving the reliability. If the film thickness is too thick, the polyimide is used as the first organic insulating layer 115. Is less than a certain thickness because it cannot balance the stress with the polyimide. Specifically, the thickness of the SiO ₂ film is preferably 1 μm or more and 8 μm or less. More preferably, it is 2 μm or more and 5 μm or less.

  The first organic insulating layer 115 is made of a material that relaxes or flattens the step formed by the first wiring layer 110 and has a dielectric constant lower than that of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Preferably, it is good to form with resin materials, such as photosensitive polyimide, for example. The film thickness of the first organic insulating layer 115 is preferably at least as thick as the step formed by the first wiring layer 110. Further, in order to reduce the parasitic capacitance between the wiring layers, it is preferable to form it as thick as possible in the coating process. Specifically, the film thickness of the first organic insulating layer is preferably 4 μm or more and 24 μm or less. More preferably, it is 8 μm or more and 20 μm or less. Moreover, photosensitive acrylic, photosensitive siloxane, etc. can be used instead of photosensitive polyimide. In addition, benzocyclobutene having a low dielectric constant and a barrier property against Cu may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyether ether ketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyetherimide, etc. Can be used. The above resins may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  The first insulating layer 119 is provided with an opening 181, and the opening 181 is filled with the first via 191. In FIG. 4, the structure in which the first via 191 is formed by filling a part of the second wiring layer 120 into the opening 181 is illustrated, but the structure is not limited to this structure. For example, as the first via 191, A conductive layer different from the second wiring layer 120 may be used. 2 illustrates the structure in which the opening 181 and the first via 191 have a right-angled shape with respect to the substrate. However, the present invention is not limited to this structure, and the opening 181 and the first via 191 are formed with respect to the substrate. It may have a forward tapered shape, and the opening 181 and the first via 191 may have a reverse tapered shape with respect to the substrate. 1 illustrates a structure in which the opening 181 is filled with a conductive layer, the vias may connect adjacent wiring layers, and a part of the opening 181 may be a cavity.

  As shown in FIG. 2, when the second wiring layer 120 is used as the first via 191, the fourth conductive layer 122 has copper (Cu), silver (Ag), low electrical resistance like the second conductive layer 112, and the like. Gold (Au), aluminum (Al), or the like can be used. Alternatively, an aluminum alloy such as an aluminum-neodymium alloy (Al—Nd) or an aluminum-copper alloy (Al—Cu) can be used. Further, as the third conductive layer 121, it is preferable to use a material having a barrier property with respect to the fourth conductive layer 122 like the first conductive layer 111. For example, when the fourth conductive layer 122 contains Cu, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), or the like is used as the third conductive layer 121. can do.

  The first via 191 is in contact with the second conductive layer 112 of the first wiring layer 110 at the bottom thereof, and the first wiring layer 110 and the second wiring layer 120 are electrically connected. In FIG. 2, the second wiring layers 126 and 127 are not connected to the upper and lower wiring layers, but may be connected to the upper and lower wiring layers at a location different from the cross section shown in FIG.

  A second insulating layer 129 is formed on the second wiring layer 120. The second insulating layer 129 has the same structure as the first insulating layer 119, and includes a third inorganic insulating layer 123, a fourth inorganic insulating layer 124, and a second organic insulating layer 125. In FIG. 2, since the material used for each layer of the second insulating layer 129 is the same as that of each layer of the first insulating layer 119, detailed description thereof is omitted here. However, the material used for each layer of the second insulating layer 129 is not limited to the same material as each layer of the first insulating layer 119, and can be appropriately selected depending on the purpose of the insulating layer.

  Thereafter, the third to fifth wiring layers (130, 140, 150) can be formed in the same manner as the second wiring layer 120. The fifth conductive layer 131 of the third wiring layer 130, the seventh conductive layer 141 of the fourth wiring layer 140, and the ninth conductive layer 151 of the fifth wiring layer 150 may be formed of the same material as the first conductive layer 111, respectively. it can. Further, the sixth conductive layer 132 of the third wiring layer 130, the eighth conductive layer 142 of the fourth wiring layer 140, and the tenth conductive layer 152 of the fifth wiring layer 150 are each formed of the same material as the second conductive layer 112. be able to. However, these conductive layers are not necessarily the same as the first conductive layer 111 or the second conductive layer 112, and can be appropriately selected according to the purpose of the wiring layer.

  Similarly to the second insulating layer 129, third to fifth insulating layers (139, 149, 159) can be formed. The fifth inorganic insulating layer 133 of the third insulating layer 139, the seventh inorganic insulating layer 143 of the fourth insulating layer 149, and the ninth inorganic insulating layer 153 of the fifth insulating layer 159 are made of the same material as the first inorganic insulating layer 113, respectively. Can be formed. The sixth inorganic insulating layer 134 of the third insulating layer 139, the eighth inorganic insulating layer 144 of the fourth insulating layer 149, and the tenth inorganic insulating layer 154 of the fifth insulating layer 159 are the same as the second inorganic insulating layer 114, respectively. Can be made of material. The third organic insulating layer 135 of the third insulating layer 139, the fourth organic insulating layer 145 of the fourth insulating layer 149, and the fifth organic insulating layer 155 of the fifth insulating layer 159 are the same as the first organic insulating layer 115, respectively. Can be made of material. However, these insulating layers are not necessarily the same as the first inorganic insulating layer 113, the second inorganic insulating layer 114, or the first organic insulating layer 115, and may be appropriately selected depending on the purpose of the insulating layer. it can.

  In FIG. 2, the fifth wiring layer 150 is connected to the uppermost sixth wiring layer 160 through an opening 185 provided in the fifth insulating layer 159. The sixth wiring layer 160 includes an eleventh conductive layer 161, a twelfth conductive layer 162, and a thirteenth conductive layer 163. As the eleventh conductive layer 161, it is preferable to use a material having low electrical resistance and good adhesion to the twelfth conductive layer 162. For example, the same material as that of the twelfth conductive layer 162 may be used, and Cu, Ag, Au, Al, Al—Nd, Al—Cu, or the like can be used.

  The thirteenth conductive layer 163 is preferably made of a material that has high corrosion resistance, is not easily oxidized, and has low contact resistance with an external element. For example, Au, platinum (Pt), etc. can be used. The twelfth conductive layer 162 is preferably made of a material having good adhesion to the eleventh conductive layer 161 and the thirteenth conductive layer 163. For example, when the 13th conductive layer 163 is formed by plating, it is preferable to use a material suitable as a seed layer for the 13th conductive layer 163. For example, Ti, nickel (Ni), etc. can be used.

  Here, an example of the arrangement of the wiring layers in the first region 301 will be described. FIG. 15 is a plan view for explaining a wiring layer (any one of the first to fifth wiring layers (110, 120, 130, 140, 150)) in the first region 301. FIG. There are mainly three types of wiring used in the first region 301. When these wirings are stacked and the number of stacked layers increases, peeling occurs at the SiN / Cu interface, and cracks are likely to occur. As described above, by disposing the second region 302 adjacent to the first region 301, peeling of the SiN / Cu interface can be prevented and generation of cracks can be controlled. Planar wiring (FIG. 15A) and mesh wiring (FIG. 15B) covering most of the substrate (or chip) are mainly microstrip structures for impedance matching of power supply, ground wiring, and signal lines. Is used to form A relatively thick wiring (FIG. 15C) having a wiring width of about 100 μm or more is often used as a power supply wiring.

<Comparative example>
As a comparative example, a multilayer wiring structure that does not have the second region 302 described in the first embodiment will be described. FIG. 12 is a plan view of the multilayer wiring structure according to this comparative example, and shows the vicinity of the end of the substrate 100. That is, the multilayer wiring structure of this comparative example includes a first region 301 in which a multilayer wiring circuit is disposed and a third region 303 in which a wiring layer is not disposed on the plane of the substrate 100, and each region is indicated by a white broken line. Indicated. The third region 303 is adjacent to the first region 301 and the edge of the substrate 100.

  FIG. 13 is a plane photograph obtained by producing a multilayer wiring structure according to this comparative example. FIG. 13 shows a first region 301 in which a multilayer wiring circuit is arranged and a third region 303 in which no wiring layer is arranged. In FIG. 13, a shadow 310 is confirmed particularly in the vicinity of the boundary between the region where the multilayer wiring circuit is disposed and the region where the wiring layer is not disposed.

  The shadow confirmed in FIG. 13 will be described. 14A is a cross-sectional photograph taken along the line AB in FIG. The multilayer wiring structure according to this comparative example has an insulating layer (110, 120, 130, 140, 150) and an insulating layer (110, 120, 130, 140, 150) and a five-layer wiring layer (110, 120, 130, 140, 150) isolated from each other. 119, 129, 139, 149, 159). Each of the insulating layers has a three-layer structure. FIG. 14A confirms that the wiring layer 130 and the insulating layer 139 are separated. FIG. 14B is an enlarged cross-sectional photograph of the vicinity of the boundary of the peeled portion in FIG. 14A. The shade 310 confirmed in FIG. 13 is due to this peeling.

  In the multilayer wiring structure shown in FIGS. 13, 14A and 14B, the wiring material is copper (Cu), and the insulating layer is a three-layer structure of polyimide / silicon oxide (SiO) / silicon nitride (SiN). Yes. The aforementioned peeling occurs at the interface between SiN and Cu.

  There are mainly three types of wirings used in the first region 301 as shown in FIG. 15. When a plurality of these wirings are laminated and the number of laminations increases, peeling occurs particularly at the SiN / Cu interface, and cracks are generated. It tends to occur.

  Planar wiring (FIG. 15A) and mesh wiring (FIG. 15B) covering most of the substrate (or chip) are mainly for impedance matching of power supply wiring, ground wiring or signal line. Used to form a microstrip structure. A relatively thick linear wiring (FIG. 15C) having a wiring width of about 100 μm or more is often used as a power supply wiring.

  The area where the multilayer wiring circuit is placed and the area where the wiring layer is not placed have a height difference in the thickness direction of the board due to the presence or absence of multiple wirings that make up the multilayer wiring. Resulting in a gradient. As this gradient increases, stress concentrates near the boundary, and the wiring layer and the insulating layer are more likely to be separated.

  Furthermore, the thermal expansion coefficient of each material constituting the wiring layer is as follows: copper (Cu) is 17.3 ppm, silicon oxide (SiO) is 0.5 ppm, silicon nitride (SiN) is 0.3 ppm, and polyimide is 40 ppm. Different. In the conventional structure, since the material composed of each of the first region 301 and the third region 303 is different, thermal expansion is performed in a direction perpendicular to the substrate at the boundary between the first region 301 and the third region 303. The rate is different and residual stress is generated. In particular, a particularly large residual stress is generated at the end of the Cu wiring covered with SiN at the boundary between the first region 301 and the third region 303. As a result, peeling occurs at the Cu / SiN interface with the weakest adhesion, and cracks in the insulating film occur.

  When the second region 302 in which the pseudo wiring is arranged adjacent to the first region 301 is provided as in the first embodiment described above, the deposition rate at which Cu occupies the space is different in both regions. The constituent materials are the same. Therefore, the difference in thermal expansion coefficient between the first region 301 and the second region 302 in the direction perpendicular to the substrate becomes small, and SiN is covered at the boundary between the first region 301 and the second region 302. Residual stress at the end of the Cu wiring is reduced. As a result, the Cu / SiN interface is unlikely to peel off.

  The second region 302 and the third region 303 are different from each other in that Cu is not disposed in the third region 303, but the proportion of the Cu wiring occupying the space of the second region 302 is different from that in the first region 301. Smaller than that. By providing the second region 302 in this way, the difference in thermal expansion coefficient between the boundary between the second region 302 and the third region 303 can be reduced, and the second region 302 and the third region 303 At the boundary, the residual stress at the end of the Cu wiring covered with SiN becomes small, and peeling of the Cu / SiN interface hardly occurs.

Second Embodiment
Hereinafter, a multilayer wiring structure according to a second embodiment of the present invention will be described in detail with reference to the drawings.

  With reference to FIG. 4, the structure of the multilayer structure wiring body which concerns on the modification of this embodiment is demonstrated in detail. FIG. 4 is a cross-sectional view taken along the line CD in FIG. As shown in FIG. 4, also in the multilayer wiring structure according to the present embodiment, the first region 301, the second region 302 adjacent to the first region 301, the second region 302 and the edge of the substrate 100 are adjacent. 3rd area | region 303 to be included.

  In the cross-sectional view shown in FIG. 4, the first region 301 includes first to fifth wiring layers (110, 120, 130, 140, 150) and first to fifth wiring layers (110, 120, 130, 140). 150), a multilayer wiring circuit having first to fourth insulating layers (119, 129, 139, 149) for isolating each of the fifth wiring layer 150 and a fifth insulating layer 159 disposed above the fifth wiring layer 150 is disposed. Has been. The first to fifth wiring layers (110, 120, 130, 140, 150) are wirings for supplying a power supply potential and a common potential, for example.

  The second region 302 includes first to fourth wiring layers (110, 120, 130, 140) among the first to fifth wiring layers (110, 120, 130, 140, 150) of the first region 301. The second region 302 is extended and arranged. In the present embodiment, the positions of the end portions of the extended wiring are different. The length of the extended wiring is the longest in the first wiring layer 110 at the lowermost layer and is shorter in the upper layer. In other words, as shown in FIG. 4, in the cross-sectional view, a region where wiring is arranged (that is, a region where wiring is arranged in the first region 301 and the second region 302) and a region where wiring is not arranged (that is, In the second region 302, the boundary C1 ′ between the region where no wiring is arranged and the third region 303) is inclined.

  By inclining the boundary C1 ′, the difference in thermal expansion coefficient between the first region 301 and the second region 302 in the D3 direction can be reduced, and the stress concentration on the corners (A1 to A5) of the Cu wiring can be reduced. Can be reduced. This makes it possible to control the peeling of the SiN / Cu interface. FIG. 4 shows a mode in which the lower wiring end in the second region 302 is shortened toward the first region 301 toward the upper layer. On the contrary, the third region 303 side toward the upper layer is shown. Even if it becomes longer, the same effect is produced.

  As will be described later, the boundary of the region may not be the inclined straight line as described above. It is only necessary that the ends of the plurality of wirings extended in the second region 302 are arranged at different positions in plan view, and the ends of the plurality of wirings extended in the second region 302 are randomly arranged, for example. Even if it is, the same effect is produced.

  In the third region 303, no wiring layer is disposed, and the same insulating layer as each of the first to fifth insulating layers (119, 129, 139, 149, 159) in the first region 301 is in contact. Are stacked.

  In the second region 302, the height of the uppermost fifth insulating layer 159 extends from the first region 301 to the third region 303 due to the fact that the closer to the third region 303, the smaller the number of stacked wirings 320. It goes down.

  Further, in the third region 303, the wiring layer is not disposed, so that the height of the uppermost fifth insulating layer 159 is lower than that of the second region 302.

  According to the present embodiment, the second region 302 adjacent to the first region 301 in which the multilayer wiring circuit is disposed is provided, and the number of wiring layers stacked is smaller than that of the first region 301 and extended from the first region 301. By disposing the first to fourth wiring layers (110, 120, 130, 140), the gradient due to the height difference between the first region 301 and the third region 303 can be reduced.

  As a result, the stress accompanying the gradient of the insulating layer can be dispersed near the both ends of the second region 302 or within the second region 302 and relaxed. Therefore, it is possible to provide a multilayer wiring structure and a semiconductor device using the same, in which cracks are unlikely to occur and a high production yield can be obtained.

  Furthermore, since the difference in the thermal expansion coefficient between the first region 301 and the second region 302 and the difference in the thermal expansion coefficient between the second region 302 and the third region 303 can be controlled to be small, the residual at each boundary can be controlled. Stress can be reduced. As a result, separation between the wiring and the insulating layer is less likely to occur, and a multilayer wiring structure and a semiconductor device using the multilayer wiring structure can be provided that can provide a high production yield.

  Here, the second region 302 to be secured preferably includes a region of 5 μm from the boundary with the first region 301. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, although the multilayer wiring circuit arrange | positioned in the 1st area | region 102 in this embodiment has five wiring layers (110, 120, 130, 140, 150), as above-mentioned, it is not limited to this.

  In the present embodiment, the wiring layer extending from the first region 301 has the longest bottom layer and the shortest upper layer. However, the present invention is not limited to this. The wiring layer disposed extending to the second region 302 may be disposed so as to reduce the height difference between the first region 301 and the second region 302. That is, the wiring layer disposed in the second region only needs to be smaller than the volume density of the wiring layer disposed in the first region. Moreover, the wiring layer extended from the 1st area | region 301 should just be arrange | positioned in the 2nd area | region 302, and the position arrange | positioned is not specifically limited.

<Third Embodiment>
Hereinafter, a multilayer wiring structure according to a third embodiment of the present invention will be described in detail with reference to the drawings.

  With reference to FIG. 5, the structure of the multilayer structure wiring body which concerns on the modification of this embodiment is demonstrated in detail. FIG. 5 is a cross-sectional view taken along the line CD in FIG. As shown in FIG. 5, also in the multilayer wiring structure according to the present embodiment, the first region 301, the second region 302 adjacent to the first region 301, the second region 302 and the edge of the substrate 100 are adjacent. 3rd area | region 303 to be included.

  In the cross-sectional view shown in FIG. 5, the first region 301 includes first to fifth wiring layers (110, 120, 130, 140, 150) and first to fifth wiring layers (110, 120, 130, 140). 150), a multilayer wiring circuit having first to fourth insulating layers (119, 129, 139, 149) for isolating each of the fifth wiring layer 150 and a fifth insulating layer 159 disposed above the fifth wiring layer 150 is disposed. Has been. The first to fifth wiring layers (110, 120, 130, 140, 150) are wirings for supplying a power supply potential and a common potential, for example.

  In the second region 302, a plurality of discretely arranged wiring layers 170 are provided in the same layer as the wiring layer of the first region 301 in each wiring layer. The plurality of wiring layers 170 arranged in the second region 302 are electrically independent of the multilayer wiring circuit in the first region 301 and are pseudo wiring layers.

  No wiring layer is disposed in the third region 303, and the first to fifth insulating layers (119, 129, 139, 149, 159) in the first region 301 are stacked in contact with the same insulating layer. Has been.

  In each layer of the first region 301 and the second region 302, the height of the insulating layer from the upper part of the wiring is lower in the second region 302 than in the first region 301. This is because the insulating film material fills the gaps between the plurality of wiring layers 170 when forming the insulating layer.

  Further, in the third region 303, the wiring layer is not disposed, so that the height of the uppermost fifth insulating layer 159 is lower than that of the second region 302.

  According to the present embodiment, the second region 302 adjacent to the first region 102 in which the multilayer wiring circuit is disposed is provided, and the pseudo wiring that is electrically independent from the multilayer wiring circuit disposed in the first region 301 is provided. By disposing the layer 170, the gradient due to the height difference between the first region 301 and the third region 303 can be reduced.

  As a result, the stress accompanying the gradient of the insulating layer can be dispersed near the both ends of the second region 302 or within the second region 302 and relaxed. Therefore, it is possible to provide a multilayer wiring structure and a semiconductor device using the same, in which cracks are unlikely to occur and a high production yield can be obtained.

  Further, unlike the multilayer wiring structure according to the first and second embodiments, the wiring layer (110, 120, 130, 140, 150) in the first region 301 is not extended to the second region 302. The conventional circuit design can be applied without changing the wiring resistance or the like in the circuit.

  Here, the second region 302 to be secured preferably includes a region of 5 μm from the boundary with the first region 301. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, the occupation area ratio of the plurality of discrete wiring layers 170 is preferably 10% or more and 80% or less. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, although the multilayer wiring circuit arrange | positioned in the 1st area | region 102 in this embodiment has five wiring layers (110, 120, 130, 140, 150), as above-mentioned, it is not limited to this.

  In the present embodiment, the pseudo wiring layer 170 is arranged in all the wiring layers in the second region 302. However, the present invention is not limited to this. The pseudo wiring layer 170 in the second region 302 may be disposed so as to reduce the height difference between the first region 301 and the second region 302. That is, the wiring layer disposed in the second region only needs to be smaller than the volume density of the wiring layer disposed in the first region. The pseudo wiring layer 170 disposed in the second region 302 only needs to be disposed in at least one of the layers. Further, the pseudo wiring layer 170 of each wiring layer does not need to have a plurality of intervals as shown in the present embodiment, and may have a continuous shape.

  Here, defects in the multilayer wiring structure according to the conventional example shown in FIG. 12, the second embodiment shown in FIG. 4, and the present embodiment shown in FIG. 5 were observed. As a result, the defect occurrence rate is 100% for the multilayer wiring structure according to the conventional example, 15% for the multilayer wiring structure according to the second embodiment, and 0% for the multilayer wiring structure according to the present embodiment. It has been found that the structure according to the embodiment is most effective for suppressing cracks.

<Fourth embodiment>
Hereinafter, a multilayer wiring structure according to a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  With reference to FIG. 6, the configuration of the multilayer structure wiring body according to the present embodiment will be described in detail. FIG. 6 is a cross-sectional view taken along the line CD in FIG. As shown in FIG. 6, also in the multilayer wiring structure according to the present embodiment, the first region 301, the second region 302 adjacent to the first region 301, the second region 302 and the edge of the substrate 100 are adjacent. 3rd area | region 303 to be included.

  In the cross-sectional view shown in FIG. 6, the first region 301 includes first to fifth wiring layers (110, 120, 130, 140, 150) and first to fifth wiring layers (110, 120, 130, 140). 150), a multilayer wiring circuit having first to fourth insulating layers (119, 129, 139, 149) for isolating each of the fifth wiring layer 150 and a fifth insulating layer 159 disposed above the fifth wiring layer 150 is disposed. Has been. The first to fifth wiring layers (110, 120, 130, 140, 150) are wirings for supplying a power supply potential and a common potential, for example.

  This embodiment corresponds to a multilayer wiring structure in which the first embodiment and the third embodiment are combined. In the present embodiment, the second area 302 is further divided into a fourth area 304 and a fifth area 305. In the fourth region 304, the second wiring layer 120 and the fourth wiring layer 140 are extended from the first region 301. Further, in each wiring layer of the fifth region 305, a plurality of pseudo wiring layers 170 are arranged in the same layer as the wiring layer of the first region 301 with a space therebetween. The plurality of pseudo wiring layers 170 provided in the fifth region 305 are electrically independent from the multilayer wiring circuit in the first region 301.

  No wiring layer is disposed in the third region 303, and the first to fifth insulating layers (119, 129, 139, 149, 159) in the first region 301 are stacked in contact with the same insulating layer. Has been.

  In each layer of the first region 301 and the second region 302, the height of the insulating layer from the upper part of the wiring is lower in the second region 302 than in the first region 301. This is because the number of wiring layers in the fourth region 304 is smaller than that in the first region 301, and in the fifth region 305, gaps between the plurality of pseudo wiring layers 170 are formed during the formation of the insulating layer. This is because the film is filled to form a film and the bulk is lowered.

  Further, in the third region 303, the wiring layer is not disposed, so that the height of the uppermost fifth insulating layer 159 is lower than that of the second region 302.

  According to the present embodiment, the second region 302 adjacent to the first region 301 in which the multilayer wiring circuit is arranged is provided, the number of wirings is smaller than that of the first region 301, and the wiring layer extended from the first region 301 By combining (120, 140) and disposing a pseudo wiring layer 170 that is electrically independent of the multilayer wiring circuit disposed in the first region 301, the first region 301 and The gradient due to the height difference of the third region 303 can be relaxed.

  As a result, the stress accompanying the gradient of the insulating layer can be dispersed near the both ends of the second region 302 or within the second region 302 and relaxed. Therefore, it is possible to provide a multilayer wiring structure and a semiconductor device using the same, in which cracks are unlikely to occur and a high production yield can be obtained.

  Here, the second region 302 to be secured preferably includes a region of 5 μm from the boundary with the first region 301. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, although the multilayer wiring circuit arrange | positioned in the 1st area | region 102 in this embodiment has five wiring layers (110, 120, 130, 140, 150), as above-mentioned, it is not limited to this.

  In the present embodiment, the two wiring layers (120, 140) are extended from the first region 301 to the second region 302, and the pseudo wiring layer 170 is disposed on all the wiring layers in the second region 302. Although the embodiment to be described was shown, it is as above-mentioned that it is not limited to this. Further, the pseudo wiring layer 170 of each wiring layer does not have to have a plurality of intervals as shown in the present embodiment, and may have a single continuous shape.

<Fifth Embodiment>
Hereinafter, a multilayer wiring structure according to a fifth embodiment of the present invention will be described in detail with reference to the drawings.

  The configuration of the multilayer wiring body according to the present embodiment will be described in detail with reference to FIG. FIG. 7 is a cross-sectional view taken along CD in FIG. As shown in FIG. 7, also in the multilayer wiring structure according to the present embodiment, the first region 301, the second region 302 adjacent to the first region 301, the second region 302 and the edge of the substrate 100 are adjacent. 3rd area | region 303 to be included.

  In the cross-sectional view shown in FIG. 7, the first region 301 includes first to fifth wiring layers (110, 120, 130, 140, 150) and first to fifth wiring layers (110, 120, 130, 140). 150), a multilayer wiring circuit having first to fourth insulating layers (119, 129, 139, 149) for isolating each of the fifth wiring layer 150 and a fifth insulating layer 159 disposed on the fifth wiring layer 150 is disposed. Has been. The first to fifth wiring layers (110, 120, 130, 140, 150) are wirings for supplying a power supply potential and a common potential, for example.

  This embodiment is similar to the multilayer wiring structure according to the fourth embodiment, but the wiring layer extended from the first region 301 and the multilayer wiring circuit in the first region 301 are pseudo independent electrically. The wiring layer 170 is different from the wiring layer 170 in that it has a region overlapping in the second region 302.

  No wiring layer is disposed in the third region 303, and the first to fifth insulating layers (119, 129, 139, 149, 159) in the first region 301 are stacked in contact with the same insulating layer. Has been.

  For the same reason as the above-described embodiment, also in this embodiment, the second region 302 is higher in the first region 301 and the second region 302 in terms of the height of the insulating layer from the upper part of the wiring. It can be formed lower than 301.

  Further, in the third region 303, the wiring layer is not disposed, so that the height of the uppermost fifth insulating layer 159 is lower than that of the second region 302.

  According to the present embodiment, the second region 302 adjacent to the first region 301 in which the multilayer wiring circuit is disposed is provided, the number of wirings is smaller than that of the first region 301, and the wiring layer extended from the first region 301 By combining (120, 140) and disposing a pseudo wiring layer 170 that is electrically independent of the multilayer wiring circuit disposed in the first region 301, the first region 301 and The gradient due to the height difference of the third region 303 can be relaxed.

  As a result, the stress accompanying the gradient of the insulating layer can be dispersed near the both ends of the second region 302 or within the second region 302 and relaxed. Therefore, it is possible to provide a multilayer wiring structure and a semiconductor device using the same, in which cracks are unlikely to occur and a high production yield can be obtained.

  Here, the second region 302 to be secured preferably includes a region of 5 μm from the boundary with the first region 301. By adopting such an arrangement, the stress in the insulating layer can be effectively relieved.

  In addition, although the multilayer wiring circuit arrange | positioned in the 1st area | region 102 in this embodiment has five wiring layers (110, 120, 130, 140, 150), as above-mentioned, it is not limited to this.

  In the present embodiment, the two wiring layers (120, 140) are extended from the first region 301 to the second region 302, and the pseudo wiring layer 170 is disposed on all the wiring layers in the second region 302. Although the embodiment to be described was shown, it is as above-mentioned that it is not limited to this. Further, the pseudo wiring layer 170 of each wiring layer does not have to have a plurality of intervals as shown in the present embodiment, and may have a single continuous shape.

<Sixth to eighth embodiments>
The arrangement of the first area 301, the second area 302, and the third area 303 is not limited to that shown in FIG. Below, some arrangement examples are shown.

  FIG. 8 is a plan view of the multilayer wiring structure according to the sixth embodiment, and shows the vicinity of the end portion of the substrate 100. The multilayer wiring structure according to the present embodiment is different from the first embodiment in that it does not include the third region 303 having no wiring layer. In order to suppress cracks, it is only necessary to relieve stress in the vicinity of the end portion of the first region 301. Therefore, the second region may be provided adjacent to the first region 301. Therefore, the third region 303 may not be provided.

  FIG. 9 is a plan view of the multilayer wiring structure according to the seventh embodiment, showing the entire surface of the substrate 100. In the multilayer wiring structure according to the present embodiment, the second region 302 is disposed so as to surround the first region 301, and further, the third region 303 is disposed so as to surround the second region 302. The second region 302 and the third region 303 are arranged around the substrate 100, and the third region 303 is adjacent to the end portion of the substrate 100.

  By having such a configuration, since the end portions of the first region 301 are all adjacent to the second region, the stress can be relieved in the entire first region 301 and the occurrence of cracks can be suppressed.

  In the present embodiment, the stress in the first region 301 can be relieved if the second region 302 has a spread of 5 μm or more from the boundary with the first region. It does not need to be arranged.

  FIG. 10 is a plan view of the multilayer wiring structure according to the eighth embodiment, showing a part of the surface of the substrate 100. The multilayer wiring structure according to this embodiment has a region in which the second region 302 and the third region 303 are arranged in a part of the plane of the substrate 100. The second region 302 is adjacent to and surrounded by the first region 301, and the third region 303 is adjacent to and surrounded by the second region 302. In other words, the second region 302 is disposed between the first region 301 and the third region 303, defines the first region 301 and the third region 303, and separates the first region 301 and the third region 303. Yes.

  By having such a configuration, even when there is a region where the wiring layer is not disposed in the plane of the substrate 100, occurrence of cracks due to the region can be suppressed.

  In this case as well, the third region 303 may not be provided, and only the second region 302 may be arranged inside the substrate 100. That is, when a region where the wiring layer is not originally disposed exists in a part of the surface of the substrate 100, a pseudo wiring layer is provided in the region to form the second region 302, thereby causing a crack in the vicinity of the region. Can be suppressed.

<Example of Arrangement of Pseudo Wiring in Second Area>
The purpose of the pseudo wiring arranged in the second region 302 is to reduce the stress by reducing the height of the wiring layer, and therefore does not depend on the shape or size of the pseudo wiring. This has been confirmed in experiments as will be shown later. However, considering the recent trend toward miniaturization of wiring dimensions, the size of the pseudo wiring is preferably 0.5 μm or more and 50 μm or less. As a result, the size of the entire circuit can be reduced by suppressing the second area 302, which is an area unrelated to operations such as signal transmission, and efficient wiring design becomes possible. FIG. 11 shows several layout examples in plan view of pseudo wirings arranged in the second region 302.

  FIG. 11A shows an example in which square pseudo wirings electrically independent from the wiring layer of the first region 301 are arranged in a matrix. FIG. 11B is an example of pseudo wiring that differs from the example of FIG. 11A only in the square size. FIG. 11C shows an example in which rectangular pseudo wirings are arranged. FIG. 11D shows an example in which circular pseudo wirings are arranged in a matrix.

  In addition to the pseudo wiring arrangement examples exemplified above, various arrangement examples are conceivable. The pseudo wiring is not limited to the square, rectangle, or circle shown above, but may be another polygon or a combination of a straight line and a curve.

  Here, the width of the second region 302, the pattern of the pseudo wiring arranged in the second region 302, and some experimental results examining the crack occurrence rate are shown.

  FIG. 16A is a simplified cross-sectional view for explaining a pseudo wiring pattern arranged in the second region 302 used in this experiment. The multilayer wiring structure used in this experiment consists of nine layers, and each layer of the second region 302 is electrically separated from the wiring of the first region 301, and discretely provided pseudo wires are arranged. Is done. FIGS. 16B, 16C, and 16D are top views for explaining pseudo wiring patterns used in this experiment. As pseudo wirings, FIG. 16B is a square, FIG. 16C is a circle, and FIG. 16D is a rectangle, and the sizes and intervals set in this experiment are shown in the figure. Fifty samples were prepared for each pattern, and the crack generation rate was examined.

  FIG. 17 is a graph showing the results of this experiment. In the graph of FIG. 17, the horizontal axis indicates the width of the second region 302, and the vertical axis indicates the crack occurrence rate. According to this result, when the width of the second region 302 is set to 5 μm or more, the crack occurrence rate becomes 0 regardless of the pseudo wiring pattern.

  Next, the relationship between the pseudo wire occupation area ratio and the crack generation ratio in the second region 302 was examined. Here, as in the experiment related to FIG. 16, a nine-layer multilayer wiring structure was produced, and the width of the second region 302 was fixed to 1000 μm.

  FIGS. 18A and 18B are diagrams for explaining a pseudo wiring pattern used in this experiment. Here, the definition of the occupation area ratio is shown. The occupied area ratio is defined as the ratio of the area of one pattern to the area of the unit unit indicated by a broken line in each of FIGS. 18 (a) to 18 (c).

  FIG. 19 is a graph showing experimental results using the square pattern shown in FIG. In the graph of FIG. 19, the horizontal axis is the occupied area ratio, and the vertical axis is the crack occurrence rate, and the two sizes of the square pattern are overlapped. Here, the size of the square pattern is 10 μm and 50 μm on one side. According to this result, when the occupation area ratio of the pseudo wiring in the second region 302 is 10% or more and 80% or less, the crack occurrence ratio becomes 0 in any size.

  FIG. 20 is a graph showing experimental results using the circular pattern shown in FIG. In the graph of FIG. 20, the horizontal axis represents the occupied area ratio, and the vertical axis represents the crack occurrence rate, and the two sizes of the circular pattern are overlapped. Here, as the size of the circular pattern, the diameters are 10 μm and 50 μm. According to this result, when the occupation area ratio of the pseudo wiring in the second region 302 is 10% or more and 80% or less, the crack occurrence ratio becomes 0 in any size.

  FIG. 21 is a graph showing experimental results using the rectangular pattern shown in FIG. In the graph of FIG. 21, the horizontal axis represents the occupied area ratio and the vertical axis represents the crack occurrence rate, and the two sizes of the rectangular pattern are overlapped. Here, the size of the rectangular pattern was 10 μm × 30 μm and 50 μm × 150 μm. According to this result, when the occupation area ratio of the pseudo wiring in the second region 302 is 10% or more and 80% or less, the crack occurrence ratio becomes 0 in any size.

  As described above, from the experimental results shown in FIGS. 19 to 21, if the occupation area ratio of the pseudo wiring in the second region 302 is 10% or more and 80% or less, it does not depend on the pseudo wiring pattern and its size. It was found that the crack generation rate was zero.

  Next, the relationship between the width of the second region 302, the mode of pseudo wiring, and the crack generation rate was examined. 22 and 23 are cross-sectional views illustrating the width of the second region 302 of the multilayer wiring structure used in this experiment and the mode of pseudo wiring. Each multilayer wiring structure is composed of five layers, and the wiring layer in the first region 301 is extended to the second region 302.

  In the multilayer wiring structure shown in FIG. 22, as in the multilayer wiring structure shown in FIG. 4, the pseudo wiring width difference X between the adjacent upper and lower layers is common to each layer. That is, the difference X between the pseudo wiring widths of the adjacent upper and lower layers is a value obtained by dividing the width of the second region 302 by four.

  In the multilayer wiring structure shown in FIG. 23, in the first, third and fifth layers from the lower layer, the wiring layer of the first region 301 is extended over the entire second region 302, and two layers are formed from the lower layer. No pseudo wiring layer is provided for the eyes and the fourth layer.

  24 and 25 are graphs showing the results of experiments using the multilayer wiring structure shown in FIGS. 22 and 23, respectively. Here, the numerical values in parentheses in the legend in FIG. 24 mean a pseudo wiring width difference X between adjacent upper and lower layers. 24 and 25, the horizontal axis represents the length of the second region 302, and the vertical axis represents the crack occurrence rate. According to this result, when the length of the second region 302 was 5 μm or more, the crack occurrence rate was 0 in any of the multilayer wiring structures.

100: substrate 101: base layer 110: first wiring layer 111: first conductive layer 112: second conductive layer 113: first inorganic insulating layer 114: second inorganic insulating layer 115: first organic insulating layer 119: first Insulating layer 120: second wiring layer 121: third conductive layer 122: fourth conductive layer 123: third inorganic insulating layer 124: fourth inorganic insulating layer 125: second organic insulating layer 129: second insulating layer 130: second 3 wiring layer 131: 5th conductive layer 132: 6th conductive layer 133: 5th inorganic insulating layer 134: 6th inorganic insulating layer 135: 3rd organic insulating layer 139: 3rd insulating layer 140: 4th wiring layer 141: Seventh conductive layer 142: eighth conductive layer 143: seventh inorganic insulating layer 144: eighth inorganic insulating layer 145: fourth organic insulating layer 149: fourth insulating layer 150: fifth wiring layer 151: ninth conductive layer 152 : 10th conductive layer 153: 9th inorganic insulating layer 154: 1st 0 inorganic insulating layer 155: fifth organic insulating layer 159: fifth insulating layer 160: sixth wiring layer 161: eleventh conductive layer 162: twelfth conductive layer 163: thirteenth conductive layer 170: pseudo wiring layer 181, 182, 185: opening 191: first via 192: second via 193: third via 194: fourth via 301: first region 302: second region 303: third region 304: fourth region 305: fifth Area 310: Shadow

Claims (9)

A plurality of wiring layers and a plurality of insulating layers that insulate each of the plurality of wiring layers; a first region; a second region adjacent to the first region; and a third region adjacent to the second region. A multilayer wiring structure having a multilayer wiring circuit provided in the first region,
The plurality of insulating layers extend from the first region to the second region,
Some of the plurality of wiring layers do not exist in the second region,
The plurality of insulating layers extend from the second region to the third region,
At least another part of the plurality of wiring layers extending from the first region to the second region does not exist in the third region,
In the third region, a multilayer wiring structure in which adjacent insulating layers out of the plurality of insulating layers are in contact with each other. A multilayer wiring circuit including a plurality of wiring layers and a plurality of insulating layers that insulate each of the plurality of wiring layers, including a first region and a second region adjacent to the first region, and provided in the first region A multilayer wiring structure comprising:
The plurality of insulating layers extend from the first region to the second region,
Some of the plurality of wiring layers do not exist in the second region,
In the second region, each of the plurality of insulating layers positioned above and below the part of the wiring layers is in contact with each other. A multilayer wiring including a plurality of wiring layers and a plurality of insulating layers for insulating each of the plurality of wiring layers, the first region and a second region surrounded by the first region, and the multilayer wiring provided in the first region A multilayer wiring structure having a circuit,
The plurality of insulating layers extend from the first region to the second region,
Some of the plurality of wiring layers do not exist in the second region,
In the second region, each of the plurality of insulating layers positioned above and below the part of the wiring layers is in contact with each other.   4. The multilayer wiring structure according to claim 1, wherein at least a part of the plurality of insulating layers includes an organic insulating layer. 5.   5. The multilayer wiring structure according to claim 1, wherein at least a part of the plurality of insulating layers includes an inorganic insulating layer. 6.   The multilayer wiring structure according to claim 1, wherein the number of layers of the wiring layer in the second region is smaller than the number of layers of the wiring layer in the first region.   The multilayer wiring structure according to claim 1, wherein the wiring layer does not exist in the third region.   The multilayer wiring structure according to claim 1 or 7, wherein the number of the plurality of insulating layers in each of the first region, the second region, and the third region is the same. A semiconductor device comprising the multilayer wiring structure according to claim 1.