JP6766923B2 - Multi-layer wiring structure - Google Patents

Description

The present invention relates to a multilayer wiring structure, and one disclosed embodiment relates to a laminated structure of a substrate and a multilayer wiring structure.

In recent years, as the performance of integrated circuits has improved, the integrated circuits have become more complicated, and the number of elements such as transistors constituting the integrated circuits has increased. As the number of elements increases, the arrangement of wirings connecting the elements becomes complicated, and the area occupied by the wirings in the integrated circuit board increases. Therefore, in order to make the area occupied by the wiring in the plane direction as small as possible in the integrated circuit board, the development of a multi-layer wiring technology in which a plurality of wirings are laminated and the wirings are laid out three-dimensionally is being developed. In particular, a multi-layer wiring technique having a so-called stack via structure in which vias are laminated to improve the wiring density has been developed (for example, Patent Document 1).

In a multi-layer wiring structure such as a stack via structure, the expansion and contraction of each layer in the thermal cycle (heat treatment process) may cause cracks in the vias that connect the laminated wiring and the interlayer film that separates the laminated wiring. The multi-layer wiring structure and the substrate may peel off. When cracks occur in the interlayer film in this way, metal atoms of the wiring material may thermally diffuse through the cracks and reach the substrate, resulting in a short circuit between the wiring and the substrate. Therefore, there arises a problem that the wiring layer arranged closest to the substrate of the multilayer wiring structure cannot be used as a signal line.

Further, since the wiring layer is laminated on one surface of the substrate, the substrate may be distorted due to the stress of the laminated wiring layer and the interlayer film. In order to relieve this stress, it is necessary to adjust the material of the film to be laminated and the film forming conditions, which causes a problem that the degree of freedom in design is limited.

Japanese Unexamined Patent Publication No. 2006-173333

In view of the above circumstances, an object of the present invention is to provide a multi-layer wiring structure in which the degree of freedom in design is improved in the multi-layer wiring structure.

The multi-layer wiring structure according to one embodiment of the present invention includes a conductive substrate and a multi-layer wiring structure in which a plurality of wiring layers are laminated on one surface of the substrate, and the multi-layer wiring structures are adjacent to each other. Wiring layers are connected and include a plurality of vias that overlap each other in a plan view, and at least one of the plurality of wiring layers includes a signal line and a ground line, and is used between the multilayer wiring structure and the substrate. An insulating intermediate layer having a first opening is provided, and a conductive portion for connecting a substrate and a ground wire is provided in the first opening.

According to this multi-layer wiring structure, in the multi-layer wiring structure, the wiring layer closest to the substrate can be used as a signal line.

Further, in another preferred embodiment, at least one wiring layer may have a conductive layer containing Cu, and the diffusion rate of Cu may be slower in the intermediate layer than in the substrate.

According to this multilayer wiring structure, it is possible to suppress the diffusion of Cu on the substrate.

Further, in another preferred embodiment, the intermediate layer may be a resin material.

According to this multi-layer wiring structure, local stress due to expansion and contraction of each layer caused by the heat treatment step can be relieved.

Further, in another preferred embodiment, a patterned insulating layer may be provided on the other surface of the substrate.

Further, in another preferred embodiment, the insulating layer may be a resin material.

In another preferred embodiment, the insulating layer may have a second opening.

Further, in another preferred embodiment, the conductive portion and the second opening portion may overlap each other in a plan view.

Further, in another preferred embodiment, the plurality of vias and the second opening may overlap each other in a plan view.

According to this multi-layer wiring structure, the stress generated by the intermediate layer or the multi-layer wiring structure laminated on one surface of the substrate can be relaxed.

Further, in another preferred embodiment, a metal layer may be provided between the substrate and the intermediate layer.

According to this multilayer wiring structure, the contact resistance between the ground wire and the substrate can be reduced, and more stable ground characteristics can be ensured.

The multi-layer wiring structure according to an embodiment of the present invention is a multi-layer wiring structure in which a conductive substrate and a first wiring layer, a second wiring layer, and a third wiring layer are laminated in order from the substrate side on one surface of the substrate. It has a wiring structure, and the multi-layer wiring structure connects the first via connecting the first wiring layer and the second wiring layer, and the second wiring layer and the third wiring layer, and the first via in a plan view. The first wiring layer includes a signal line and a ground line, has a first opening between the multilayer wiring structure and the substrate, and has a lower Young rate than the substrate. An insulating intermediate layer is provided, and a conductive portion for connecting the substrate and the ground wire is provided in the first opening.

The multi-layer wiring structure according to an embodiment of the present invention is a multi-layer wiring structure in which a conductive substrate and a first wiring layer, a second wiring layer, and a third wiring layer are laminated in order from the substrate side on one surface of the substrate. It has a wiring structure, and the multi-layer wiring structure connects the first via connecting the first wiring layer and the second wiring layer, and the second wiring layer and the third wiring layer, and the first via in a plan view. The first wiring layer includes a signal line and a ground line, has a first opening between the multilayer wiring structure and the substrate, and has a higher thermal expansion rate than the substrate. An insulating intermediate layer which is high and has a lower thermal expansion rate than the first wiring layer is provided, and a conductive portion for connecting the substrate and the ground wire is provided in the first opening.

According to this multi-layer wiring structure, in the multi-layer wiring structure, the wiring layer closest to the substrate can be used as a signal line. In addition, local stress due to expansion and contraction of each layer caused by the heat treatment step can be relaxed.

Further, in another preferred embodiment, the first via and the conductive portion may be arranged at different positions in a plan view.

Further, in another preferred embodiment, the first wiring layer has a conductive layer containing Cu, and the diffusion rate of Cu may be slower in the intermediate layer than in the substrate.

According to this multilayer wiring structure, it is possible to suppress the diffusion of Cu on the substrate.

Further, in another preferred embodiment, the intermediate layer may be a resin material.

According to this multi-layer wiring structure, local stress due to expansion and contraction of each layer caused by the heat treatment step can be relieved.

Further, in another preferred embodiment, a patterned insulating layer may be provided on the other surface of the substrate.

Further, in another preferred embodiment, the insulating layer may be a resin material.

In another preferred embodiment, the insulating layer may have a second opening.

Further, in another preferred embodiment, the conductive portion and the second opening portion may overlap each other in a plan view.

Further, in another preferred embodiment, the first via and the second via and the second opening may overlap each other in a plan view.

According to this multi-layer wiring structure, the stress generated by the intermediate layer or the multi-layer wiring structure laminated on one surface of the substrate can be relaxed.

Further, in another preferred embodiment, a metal layer may be provided between the substrate and the intermediate layer.

According to this multilayer wiring structure, the contact resistance between the ground wire and the substrate can be reduced, and more stable ground characteristics can be ensured.

According to the present invention, it is possible to provide a multi-layer wiring structure in which the degree of freedom in design is improved in the multi-layer wiring structure.

It is sectional drawing of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate which formed the intermediate layer which has an opening in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the 1st conductive material and the lower 2nd conductive material were formed in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 5 is a cross-sectional view of a substrate in which a photoresist is formed on a lower second conductive material in the method for manufacturing a multilayer wiring structure according to a first embodiment of the present invention. It is sectional drawing of the substrate in which the upper 2nd conductive material was formed on the lower 2nd conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate from which the photoresist on the lower second conductive material was removed in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the pattern of the 1st wiring layer was formed by etching in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate which formed the 1st inorganic insulating layer and the 2nd inorganic insulating layer on the 1st wiring layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate which formed the 1st organic insulating layer on the 2nd inorganic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 5 is a cross-sectional view of a substrate in which openings are formed in the first inorganic insulating layer and the second inorganic insulating layer in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the substrate in which the 3rd conductive material was formed on the 1st organic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the lower 4th conductive material was formed on the 3rd conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 5 is a cross-sectional view of a substrate in which a photoresist is formed on a lower fourth conductive material in the method for manufacturing a multilayer wiring structure according to a first embodiment of the present invention. It is sectional drawing of the substrate in which the upper 4th conductive material was formed on the lower 4th conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate from which the photoresist on the lower fourth conductive material was removed in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the pattern of the 2nd wiring layer was formed by etching in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate which formed the 3rd inorganic insulating layer and the 4th inorganic insulating layer on the 2nd wiring layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the 2nd organic insulating layer was formed on the 4th inorganic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate in which the opening was formed in the 3rd inorganic insulating layer and the 4th inorganic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate explaining the detail of the method of etching the pattern of a wiring layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the substrate explaining the detail of the method of forming an organic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 2nd Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 3rd Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 4th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on the modification of 4th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 5th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on Example 1 of this invention.

<First Embodiment>
Hereinafter, the multilayer wiring structure according to the first embodiment of the present invention will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present invention, and the present invention is not construed as being limited to these embodiments. In the drawings referred to in the present embodiment, the same parts or parts having similar functions are designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. In addition, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

[Structure of multi-layer wiring structure]
FIG. 1 is a cross-sectional view of a multilayer wiring structure according to a first embodiment of the present invention. In FIG. 1, as an example of the multi-layer wiring structure, a cross-sectional view of the 6-layer wiring structure will be described.

In FIG. 1, the first to sixth wiring layers (110, 120, 130, 140, 150, 160) and the first to sixth wiring layers are separated from each other on one surface of the conductive substrate 100. The first to connect the first to fifth interlayer films (119, 129, 139, 149, 159) and the adjacent wiring layers of the first to fifth wiring layers (110, 120, 130, 140, 150). A multi-layer wiring structure having a fourth via (191, 192, 193, 194) is formed. Here, the first to fourth vias (191, 192, 193, 194) are superimposed on each other in a plan view.

In FIG. 1, the first to sixth wiring layers have a signal line 800 and a ground line 900, respectively. Further, an insulating intermediate layer 101 having an opening 180 is provided between the substrate 100 and the first wiring layer 110 which is the lowest wiring layer of the multi-layer wiring structure, and the substrate 100 and the ground are provided in the opening 180. A conductive portion 190 is formed to connect the first wiring layer 110 of the wire 900. In FIG. 1, a structure in which a conductive portion 190 is formed by filling a part of the first wiring layer 110 in the opening 180 is illustrated, but the structure is not limited to this structure, and for example, the conductive portion 190 is the first. 1 A conductive layer different from the wiring layer 110 may be used.

In FIG. 1, the first wiring layer 110 has a first conductive layer 111 and a second conductive layer 112. As the second conductive layer 112, a metal material having a low electrical resistance is preferable. For example, copper (Cu), silver (Ag), gold (Au), aluminum (Al) and the like can be used. Further, an aluminum alloy such as an aluminum-neodium alloy (Al-Nd) or an aluminum-copper alloy (Al-Cu) can be used. As the first conductive layer 111, it is preferable to use a material having adhesiveness and a barrier property with respect to the second conductive layer 112. For example, when Cu is used as the second conductive layer 112, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), etc. are used as the first conductive layer 111. Can be used. In FIG. 1, a laminated structure of two conductive layers is illustrated as the wiring layer, but the structure is not limited to this, and a single-layer structure of one conductive layer may be used, and three or more conductive layers may be used. It may be a laminated structure by.

In FIG. 1, the first interlayer film 119 has a first inorganic insulating layer 113, a second inorganic insulating layer 114, and a first organic insulating layer 115. The first inorganic insulating layer 113 is formed so as to cover the first conductive layer 111, the second conductive layer 112, and the exposed intermediate layer 101. Further, the second inorganic insulating layer 114 is formed so as to cover the first inorganic insulating layer 113, and the first organic insulating layer 115 is further formed on the second inorganic insulating layer 114. Here, it is desirable that the dielectric constant of the first organic insulating layer 115 is lower than the dielectric constant of each of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. The first interlayer film 119 is not limited to the above three-layer structure, and may be configured to include at least one organic insulating layer or an inorganic insulating layer.

For the first inorganic insulating layer 113, it is preferable to use a material having a barrier property with respect to the second conductive layer 112. In other words, the first inorganic insulating layer 113 is preferably a material having a slower diffusion rate of the second conductive layer 112 than the second inorganic insulating layer 114 and the first organic insulating layer 115. For example, when Cu is used as the second conductive layer 112, the first inorganic insulating layer 113 includes silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and silicon carbide (SiC). , Silicon nitride carbide (SiCN), carbon-added silicon oxide (SiOC) and the like can be used. Further, it is preferable that the first inorganic insulating layer 113 is formed under good film forming conditions. When Cu is used as the second conductive layer 112 and SiN is used as the first inorganic insulating layer 113, the film thickness is preferably a certain value or more in order to obtain the diffusion prevention function of Cu, and SiN is a relative permittivity. Since the rate is as high as 7.5, it is preferable to make the film thickness below a certain level in order to suppress the parasitic capacitance between the wiring layers. Specifically, the film thickness of the SiN film is preferably 10 nm or more and 200 nm or less. Further, it is more preferably 50 nm or more and 100 nm or less.

The first inorganic insulating layer 113 preferably prevents cracks in the first inorganic insulating layer 113 and regions with a rough film from occurring in the stepped portion formed by the first wiring layer 110. For example, it is desirable that the first inorganic insulating layer 113 is formed under conditions where the film forming temperature is high, and preferably 200 ° C. or higher. More preferably, it is 300 ° C. or higher. Further, in order to improve the covering property of the first inorganic insulating layer 113, the end surface of the first wiring layer 110 may have a forward taper shape inclined with respect to the surface of the intermediate layer 101. The taper angle of the first wiring layer 110 is preferably 30 degrees or more and 90 degrees or less. More preferably, it is 30 degrees or more and 60 degrees or less. Here, both the first conductive layer 111 and the second conductive layer 112 included in the first wiring layer 110 do not have to have a forward taper shape, and only one of them may have a forward taper shape.

For the second inorganic insulating layer 114, it is preferable to use a material having good adhesion to the first inorganic insulating layer 113 and the first organic insulating layer 115 formed on the first inorganic insulating layer 113. For example, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like can be used as the second inorganic insulating layer 114. Further, it is preferable that the second inorganic insulating layer 114 is formed under good film forming conditions. Further, the SiO ₂ film is preferably a film thickness of a certain level or more in order to adjust the warp of the substrate and improve reliability, and if the film thickness is too thick, it cannot be balanced with the stress of PI, so that the film thickness is below a certain level. It is preferably thick. Specifically, the film thickness of the SiO ₂ film is preferably 1 μm or more and 8 μm or less. Further, it is more preferably 2 μm or more and 5 μm or less.

The first organic insulating layer 115 may be a material that relaxes or flattens the step formed by the first wiring layer 110 and has a dielectric constant lower than that of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Preferably, it is formed of a resin material such as photosensitive polyimide. The film thickness of the first organic insulating layer 115 is preferably at least a film thickness equal to or greater than the step formed by the first wiring layer 110, and the coating step is possible in order to reduce the parasitic capacitance between the wiring layers. It is preferable to form it as thick as possible. Specifically, the film thickness of the first organic insulating layer is preferably 4 μm or more and 24 μm or less. Further, it is more preferably 8 μm or more and 20 μm or less. Further, instead of the photosensitive polyimide, photosensitive acrylic, photosensitive siloxane, or the like can be used. In addition, benzocyclobutene having a low dielectric constant and a barrier property against Cu may be used. Further, the present invention is not limited to the photosensitive resin, and a non-photosensitive resin may be used.

Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, and BT resin. , FR-4, FR-5, Polyacetal, Polybutylene terephthalate, Syndiotactic polystyrene, Polyphenylene sulfide, Polyether ether ketone, Polyethernitrile, Polycarbonate, Polyphenylene ether Polysulfone, Polyethersulfone, Polyarylate, Polyetherimide, etc. Can be used. The above resin may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, or alumina may be used in combination with the above resin.

The first interlayer film 119 is provided with an opening 181, and the inside of the opening 181 is filled with the first via 191. In FIG. 1, a structure for forming the first via 191 by filling the opening 181 with a part of the second wiring layer 120 is illustrated, but the structure is not limited to this structure, and for example, as the first via 191. , A conductive layer different from the second wiring layer 120 may be used. Further, in FIG. 1, the structure in which the opening 181 and the first via 191 have a shape perpendicular to the substrate is illustrated, but the structure is not limited to this, and the opening 181 and the first via 191 refer to the substrate. It may have a forward taper shape, and the opening 181 and the first via 191 may have a reverse taper shape with respect to the substrate. Further, in FIG. 1, a structure in which the opening 181 is filled with a conductive layer is illustrated, but the via may be connected between adjacent wiring layers, and a part of the opening 181 may be hollow.

As shown in FIG. 1, when the second wiring layer 120 is used as the first via 191, as the fourth conductive layer 122, copper (Cu), silver (Ag), which have low electrical resistance like the second conductive layer 112, Gold (Au), aluminum (Al) and the like can be used. Further, an aluminum alloy such as an aluminum-neodium alloy (Al-Nd) or an aluminum-copper alloy (Al-Cu) can be used. Further, as the third conductive layer 121, it is preferable to use a material having a barrier property with respect to the fourth conductive layer 122 as in the case of the first conductive layer 111. For example, when the fourth conductive layer 122 contains Cu, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), or the like is used as the third conductive layer 121. can do.

The first via 191 is in contact with the second conductive layer 112 of the first wiring layer 110 at the bottom thereof, and the first wiring layer 110 and the second wiring layer 120 are electrically connected to each other. Although the second wiring layers 126 and 127 are not connected to the upper and lower wiring layers in FIG. 1, they may be connected to the upper and lower wiring layers at a location different from the cross section shown in FIG.

A second interlayer film 129 is formed on the second wiring layer 120. The second interlayer film 129 has the same structure as the first interlayer film 119, and has a third inorganic insulating layer 123, a fourth inorganic insulating layer 124, and a second organic insulating layer 125. In FIG. 1, since the material used for each layer of the second interlayer film 129 is the same material as that of each layer of the first interlayer film 119, detailed description thereof will be omitted here. However, the material used for each layer of the second interlayer film 129 is not limited to the same material as each layer of the first interlayer film 119, and can be appropriately selected depending on the purpose of the interlayer film.

After that, the third to fifth wiring layers (130, 140, 150) can be formed in the same manner as the second wiring layer 120. The fifth conductive layer 131 of the third wiring layer 130, the seventh conductive layer 141 of the fourth wiring layer 140, and the ninth conductive layer 151 of the fifth wiring layer 150 may each be formed of the same material as the first conductive layer 111. it can. Further, the sixth conductive layer 132 of the third wiring layer 130, the eighth conductive layer 142 of the fourth wiring layer 140, and the tenth conductive layer 152 of the fifth wiring layer 150 are each formed of the same material as the second conductive layer 112. be able to. However, these conductive layers do not necessarily have to be the same as the first conductive layer 111 or the second conductive layer 112, and can be appropriately selected depending on the purpose of the wiring layer.

Further, the third to fifth interlayer films (139, 149, 159) can be formed in the same manner as the second interlayer film 129. The fifth inorganic insulating layer 133 of the third interlayer film 139, the seventh inorganic insulating layer 143 of the fourth interlayer film 149, and the ninth inorganic insulating layer 153 of the fifth interlayer film 159 are made of the same material as the first inorganic insulating layer 113, respectively. Can be formed. Further, the sixth inorganic insulating layer 134 of the third interlayer film 139, the eighth inorganic insulating layer 144 of the fourth interlayer film 149, and the tenth inorganic insulating layer 154 of the fifth interlayer film 159 are the same as the second inorganic insulating layer 114, respectively. It can be made of material. Further, the third organic insulating layer 135 of the third interlayer film 139, the fourth organic insulating layer 145 of the fourth interlayer film 149, and the fifth organic insulating layer 155 of the fifth interlayer film 159 are the same as the first organic insulating layer 115, respectively. It can be made of material. However, these insulating layers do not necessarily have to be the same as the first inorganic insulating layer 113, the second inorganic insulating layer 114, or the first organic insulating layer 115, and may be appropriately selected depending on the purpose of the insulating layer. it can.

The first to fourth vias (191, 192, 193, 194) each have a so-called stack via structure in which they are laminated with the same plane coordinates. In other words, the first to fourth vias (191, 192, 193, 194) overlap each other in a plan view. Here, the overlapping vias are not limited to a structure in which the vias are completely superimposed in a plan view, and include, for example, a structure in which a part of the vias is superimposed. In the stack via structure shown in FIG. 1, a structure in which all the stacked vias are superimposed on each other in a plan view is illustrated, but the structure is not limited to this structure, and at least the vias formed above and below a certain wiring layer are in the plan view. It suffices if they overlap each other. For example, the first via 191 below the second wiring layer 120 and the second via 192 above may overlap at least partly in a plan view.

Further, in FIG. 1, a structure in which the first to fourth vias (191, 192, 193, 194) all have the same diameter is illustrated, but the structure is not limited to this, and the diameter of the via may differ depending on the layer. Good. For example, the vias in the upper layer (for example, the fourth via 194) may have a larger diameter than the vias in the lower layer (for example, the first via 191). Further, the diameter of the vias of the specific layer may be different from the diameter of the vias of the other layers.

In FIG. 1, the fifth wiring layer 150 is connected to the uppermost sixth wiring layer 160 via an opening 185 provided in the fifth interlayer film 159. The sixth wiring layer 160 has an eleventh conductive layer 161 and a twelfth conductive layer 162 and a thirteenth conductive layer 163. As the eleventh conductive layer 161, it is preferable to use a material having low electrical resistance and good adhesion to the tenth conductive layer 152. For example, the same material as the tenth conductive layer 152 may be used, and Cu, Ag, Au, Al, Al-Nd, Al-Cu, and the like can be used.

Further, as the thirteenth conductive layer 163, it is preferable to use a material having high corrosion resistance, resistance to oxidation, and low contact resistance with an external element. For example, Au, platinum (Pt) and the like can be used. Further, as the 12th conductive layer 162, a material having good adhesion to the 11th conductive layer 161 and the 13th conductive layer 163 is preferable. Further, for example, when the 13th conductive layer 163 is formed by plating, it is preferable to use a material suitable as the seed layer of the 13th conductive layer 163. For example, Ti, nickel (Ni), TiN, Cr and the like can be used.

An insulating intermediate layer 101 is formed between the multilayer wiring structure and the substrate. It is desirable that the intermediate layer 101 is softer than the substrate 100, that is, has a smaller Young's modulus, in order to alleviate the stress transmitted to the substrate due to the multilayer wiring structure. Further, the intermediate layer 101 is more easily expanded and contracted than the substrate 100 in order to alleviate the thermal expansion of the substrate from being transmitted to the multilayer wiring structure, and is more than the first conductive layer 111 and the second conductive layer 112 of the first wiring layer 110. It is desirable that it does not expand or contract easily. That is, it is desirable that the coefficient of thermal expansion is higher than that of the substrate 100 and the coefficient of thermal expansion is lower than that of the first wiring layer. Here, when the thickness of the second conductive layer 112 is, for example, five times or more thicker than the thickness of the first conductive layer 111, the stress caused by the coefficient of thermal expansion is dominated by the stress caused by the second conductive layer 112. Therefore, the coefficient of thermal expansion of the intermediate layer 101 may be lower than the coefficient of thermal expansion of the second conductive layer 112. Further, it is desirable that the intermediate layer 101 contains a resin material. Further, it is preferable to use a material having a barrier property with respect to the second conductive layer 112 for the intermediate layer 101. In other words, the intermediate layer 101 is preferably a material in which the diffusion rate of the second conductive layer 112 is slower than that of the substrate 100. For example, when the second conductive layer 112 contains Cu, a resin material such as polyimide can be used as the intermediate layer 101. In FIG. 1, a structure in which one intermediate layer is sandwiched between a multilayer wiring structure and a substrate is illustrated, but the structure is not limited to this structure, and the intermediate layer and the multilayer wiring structure or the intermediate layer and the substrate are used. Another layer may be sandwiched between them.

Here, in FIG. 1, a plurality of vias are superimposed on each other in a plan view in order to provide a multilayer wiring structure having a high degree of freedom in design and to provide a multilayer wiring structure having a small occupied area in the plane direction. The stack via structure is disclosed. The degree of expansion and contraction due to the heat treatment step during the process differs between the organic insulating layer and the wiring layer, or between the organic insulating layer and the substrate. Therefore, in the stack via structure, the region AB line on which the wiring layer and vias are superimposed and the region CD line in which the organic insulating layer is formed between the wiring layers are generated in the degree of expansion and contraction due to the heat treatment step and inside. The stress applied is very different.

In particular, in the region AB line where the wiring layers harder than the organic insulating layer, that is, having a large Young's modulus are laminated, D2 (three-dimensional) as compared with the region CD line in which the organic insulating layer is arranged between the wiring layers. A large stress is generated in the direction. Further, stress in the D1 (planar) direction due to the degree of expansion and contraction due to the heat treatment step is also generated on the entire surface of the substrate between the organic insulating layer and the substrate.

When a stack via structure is formed without providing an intermediate layer on the substrate as in the conventional case, cracks occur in the vias and the inorganic insulating layer due to the above stress in the D1 direction or the D2 direction, and the vias and the wiring are connected. Problems such as peeling occur. However, according to the structure shown in FIG. 1, the stress in the D1 direction or the D2 direction can be relaxed at least in the region where the intermediate layer 101 is provided between the first wiring layer 110 and the substrate 100. It is possible to suppress problems such as cracks in vias and inorganic insulating layers and peeling of vias and wiring.

Further, in a structure in which a multilayer wiring structure is formed without providing an intermediate layer on a substrate as in the conventional case, particularly when the second conductive layer 112 of the first wiring layer 110 contains Cu, the first conductive layer 111 and the first 1 Even when a material having a barrier property against Cu is used as the inorganic insulating layer 113, Cu may diffuse to the substrate through cracks generated in the first inorganic insulating layer 113 by the heat treatment step. For example, when a conductive or semiconductor material is used for the substrate 100, there arises a problem that the first wiring layer 110 and the substrate 100 are short-circuited. When such a problem occurs, at least the first wiring layer 110 cannot be used for the signal line, and the degree of freedom in design is limited.

As described above, by providing an insulating intermediate layer having the above characteristics between the substrate and the multilayer wiring structure, the stress in the three-dimensional direction generated in the region where the wiring layer and vias are superimposed by the heat treatment step is relaxed. be able to. Further, by providing the intermediate layer, the stress in the plane direction generated on the entire surface of the substrate by the heat treatment step can be relaxed. As a result, problems such as cracks in the vias and the inorganic insulating layer and peeling of the vias and the wiring can be suppressed.

Further, by providing an insulating intermediate layer having the above characteristics between the substrate and the multilayer wiring structure, it is possible to suppress the diffusion of Cu to the substrate by the heat treatment step. As a result, since the problem that the first wiring layer and the substrate are short-circuited can be suppressed, the first wiring layer 110 can be used for the signal line 800, and the wiring whose characteristic impedance is matched can be arranged. .. Further, by connecting the ground wire 900 to the conductive substrate 100, more stable ground characteristics can be obtained.

Therefore, according to the first embodiment shown in FIG. 1 as an example, it is possible to provide a multi-layer wiring structure in which the degree of freedom in design is improved in the multi-layer wiring structure. Further, it is possible to provide a multilayer wiring structure having high resistance to a heat treatment step. Further, since a multi-layer wiring structure having a stack via structure can be obtained, it is possible to provide a multi-layer wiring structure having a small occupied area in the plane direction. Further, by using a material having a dielectric constant lower than that of the inorganic insulating layer as the organic insulating layer, the parasitic capacitance between the laminated wirings can be reduced, so that the delay of the signal transmitted through the wirings is suppressed. It is possible to provide a multilayer wiring structure capable of providing a multilayer wiring structure. Further, wiring having a matching characteristic impedance can be arranged in all the wiring layers, and a multi-layer wiring structure capable of high-speed transmission can be provided.

[Manufacturing method of multilayer wiring structure]
Next, a method of manufacturing the multilayer wiring structure according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 19. In FIGS. 2 to 19, the same elements as those shown in FIG. 1 are designated by the same reference numerals.

FIG. 2 is a cross-sectional view of a substrate on which a first conductive material and a lower second conductive material are formed in the method for manufacturing a multilayer wiring structure according to a first embodiment of the present invention. As shown in FIG. 2, an insulating intermediate layer 101 using a resin material such as polyimide is formed on a substrate 100 such as a silicon substrate by a coating method. Next, after exposure using a photomask, development is performed to form an opening 180 as shown in FIG.

Next, as shown in FIG. 3, a first conductive material 211 is formed on the intermediate layer 101 and inside the opening 180 by a sputtering method, and a lower second conductive material 212 is formed on the first conductive material 211. A part of the conductive portion 190 is formed. As the lower second conductive material 212, it is preferable to use Cu having low resistance, and in that case, it is preferable to use Ti having a barrier property with respect to Cu as the first conductive material 211. The intermediate layer 101 and the first conductive material 211 serve as a barrier layer for suppressing Cu from diffusing into the substrate 100 and causing a short circuit between the first conductive material 211 and the substrate 100. Further, the lower second conductive material 212 serves as a seed layer for growing Cu by the electrolytic plating method. Here, as the material of the barrier layer other than Ti, TiN, refractory metal Ta, TaN, Cr, or the like can also be used.

Next, as shown in FIG. 4, the photoresist pattern 310 for wiring formation is formed by applying a photoresist on the lower second conductive material 212 and then exposing and developing the resist. Then, by using an electrolytic plating method to grow the same material as the lower second conductive material 212 on the lower second conductive material 212 exposed from the wiring forming resist pattern 310, the upper second conductive material 212 is grown as shown in FIG. 2 Form the conductive material 213. By these steps, the conduction portion 190 is filled in the opening 180. In FIG. 5, a manufacturing method for growing the same material as the lower second conductive material 212 as the upper second conductive material 213 is illustrated, but the method is not limited to this method, and the upper second conductive material 213 is used as the lower second conductive material. Materials different from 212 may be grown.

Next, after forming the upper second conductive material 213, the photoresist forming the wiring forming resist pattern 310 is removed with an organic solvent to obtain the structure of FIG. In addition, for removing the photoresist, ashing with oxygen plasma can be used instead of using an organic solvent.

Next, as shown in FIG. 7, a part of the lower second conductive material 212 and a part of the first conductive material 211 covered with the wiring forming resist pattern 310 are etched with an acidic chemical solution, and the first The conductive layer 111 and the second conductive layer 112 are formed. Since the film thickness of the upper second conductive material 213 is reduced by this etching, it is preferable to set the film thickness of the upper second conductive material 213 in consideration of the influence of this thinning. Further, instead of the above-mentioned etching with a chemical solution, ion milling, dry etching or the like can be used.

When an acidic aqueous solution is used, if the etching rate of the first conductive layer 111 is faster than that of the second conductive layer 112, the undercut 301 is formed as shown in FIG. In particular, when the width of the wiring is 5 μm or less, sufficient adhesion cannot be obtained between the first conductive layer 111 and the underlying intermediate layer 101, and the first conductive layer 111 is peeled off due to its own stress or the like. Sometimes. On the other hand, when ion milling or dry etching is used, such undercuts are unlikely to occur, so that fine wiring can be formed.

Next, as shown in FIG. 8, a first inorganic insulating layer 113 such as a SiN film and a second inorganic insulating layer 114 such as a SiO ₂ film are formed on the second conductive layer 112 by a plasma CVD method. To do. SiH ₄ can be used as a Si source and NH ₃ can be used as a nitrogen source for forming a SiN film. Further, the deposition of the SiO ₂ film, may be a SiH ₄ Si MinamotoToshi, the N ₂ O with an oxygen source. Further, tetraethoxysilane (TEOS) can be used as the Si source. Moreover, O ₂ can also be used as an oxygen source.

The SiO ₂ film preferably adjusts the film stress to a compressive stress of −300 MPa or more and −100 MPa or less in terms of suppressing warpage of the substrate 100. In particular, the film stress is preferably adjusted to −200 MPa or more and −150 MPa or less.

When the second conductive layer 112 contains Cu, if copper oxide is present on the surface of Cu, the adhesion between the first inorganic insulating layer 113 and Cu decreases, so that before the first inorganic insulating layer 113 is formed. It is preferable to clean the Cu surface with dilute sulfuric acid or the like. Further, copper oxide can be removed by exposing the Cu surface to NH ₃ plasma in the same chamber before forming the first inorganic insulating layer 113.

When the second conductive layer 112 contains Cu, it is preferable to use a SiN film having a barrier property against Cu as the first inorganic insulating layer 113, and Cu atoms, Cu molecules, and Cu ions of the second conductive layer 112 are used. Serves as a barrier insulating layer that prevents thermal diffusion from the side surfaces and upper surfaces of the second conductive layer 112 to the second inorganic insulating layer 114, and further prevents diffusion due to an electric field between adjacent wiring layers. Here, instead of using the SiC film as the barrier insulating layer, a SiC film (which may contain several% to 10% of oxygen) can be used. The SiC film can also be formed by plasma CVD, and has the effect of preventing the diffusion of Cu atoms, Cu molecules, and Cu ions in the second conductive layer 112.

Further, as the second inorganic insulating layer 114, a SiOC film, a SiOF film, or the like may be used instead of the SiO ₂ film. A SiOC film and a SiOF film can also be formed by plasma CVD. The SiOC film and the SiOF film have a lower dielectric constant than the SiO ₂ film, and the parasitic capacitance between the laminated wirings can be reduced.

Next, the first organic insulating layer 115 such as polyimide is applied onto the second inorganic insulating layer 114 by a spin coating method. Benzocyclobutene or the like may be used instead of polyimide. Further, the present invention is not limited to the photosensitive resin, and a non-photosensitive resin may be used.

Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, and BT resin. , FR-4, FR-5, Polyacetal, Polybutylene terephthalate, Syndiotactic polystyrene, Polyphenylene sulfide, Polyether ether ketone, Polyethernitrile, Polycarbonate, Polyphenylene ether Polysulfone, Polyethersulfone, Polyarylate, Polyetherimide, etc. Can be used. The above resin may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, or alumina may be used in combination with the above resin.

However, when a non-photosensitive resin is used, it is necessary to further apply a photosensitive resin and perform patterning by lithography. Therefore, the number of steps may be increased if a non-photosensitive resin is used. In the first embodiment, a manufacturing method using photosensitive polyimide as the first organic insulating layer 115 will be described.

When the first organic insulating layer 115 is applied, it is exposed with a photomask and then developed, and as shown in FIG. 9, a recess 281 is formed at a required position above the second conductive layer 112. .. Here, the "necessary position" refers to a position where a via for connecting the second conductive layer 112 to the wiring formed in the upper layer thereof needs to be arranged.

A thermosetting treatment is performed to cure the first organic insulating layer 115 applied after the formation of the recess 281. The thermosetting treatment is preferably set to a temperature equal to or lower than the glass transition temperature of the organic insulating layer to be used. This is because if the glass is cured at a temperature exceeding the glass transition temperature, the shape of the recess 281 is deformed, causing problems such as an opening diameter larger than the design size. For example, when polyimide is used as the first organic insulating layer 115, if the glass transition temperature of the polyimide is 280 ° C., the heat treatment is preferably performed at 250 ° C., for example, heat treatment at 250 ° C. for 1 hour in a nitrogen atmosphere. It is good to do. Not limited to the thermosetting treatment, the heat treatment after this step is preferably performed so as not to exceed the glass transition temperature of the polyimide.

When the first organic insulating layer 115 is thermoset, a step 302 as shown in FIG. 21 may occur in a region other than the recess 281 due to the influence of the step caused by the first wiring layer 110. Such a step becomes larger as the wiring layers are laminated, and causes a focus shift during pattern exposure. For this reason, it becomes difficult to form a wiring pattern based on the design dimensions, which causes a problem that adjacent wirings are short-circuited and a problem that wirings are broken. In order to reduce the step 302 of the first organic insulating layer 115, it is preferable to use an organic material having a small heat shrinkage rate (preferably, the heat shrinkage rate is 15% or less) such as polyimide. A fly cutter can also be used to remove irregularities on the surface of the polyimide with high accuracy.

Next, the first inorganic insulating layer 113 and the second inorganic insulating layer 114 at the bottom of the recess 281 are etched by plasma etching using the first organic insulating layer 115 as a mask. Here, an etching method when a SiN film is used as the first inorganic insulating layer 113, a SiO ₂ film is used as the second inorganic insulating layer 114, and polyimide is used as the first organic insulating layer 115 will be described in detail.

As the etching gas for the SiO ₂ film, a mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) can be used. By changing the flow rate ratio of the mixed gas, it is possible to adjust the ratio of the etching rate of the cured polyimide and the SiO ₂ film. Here, it is preferable to adjust so that the ratio of the etching rate of polyimide to the SiO ₂ film is small. The etching gas is not limited to the one described above, and CHF 3 or CH ₂ F ₂ can be used instead of CF ₄ .

As the etching gas for the SiN film, a mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) can be used. Also in the etching of the SiN film, it is possible to adjust the ratio of the etching rate of the cured polyimide and the SiN film by changing the flow rate ratio of the mixed gas. Similar to SiO ₂ , it is preferable to adjust so that the ratio of the etching rate of polyimide to the SiN film is small.

As described above, the opening for filling the first via 191 that electrically connects the first wiring layer 110 and the second wiring layer 120 by etching the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Part 181 is formed. Immediately after the opening 181 is formed, a carbon compound containing Si or F may be attached to the side wall or the bottom of the opening 181. In order to remove this carbon compound, cleaning may be carried out with an organic solvent. Further, the surface of the second conductive layer 112 exposed at the bottom of the opening 181 may be oxidized by plasma etching. Cleaning with dilute sulfuric acid may be performed to remove oxides on the surface.

Due to plasma etching on the first inorganic insulating layer 113 and the second inorganic insulating layer 114, the surface of the first organic insulating layer 115 may be damaged by plasma, and the heat resistance inherent in the first organic insulating layer 115 may be impaired. .. In this case, for example, the damaged layer on the surface can be removed by performing the heat treatment at the glass transition temperature or lower of the first organic insulating layer 115. In this way, the structure shown in FIG. 10 can be obtained.

Next, as shown in FIG. 11, the third conductive material 221 is formed into a film by a sputtering method. When the second conductive layer 112 contains Cu, the third conductive material 221 uses Ti, TiN, Ta, TaN, Cr, or the like as in the case of the first conductive layer 111, so that Cu atoms, Cu molecules, and Cu can be used. It can function as a barrier metal that prevents ions from diffusing.

Next, as shown in FIG. 12, the lower fourth conductive material 222 is formed into a film by a sputtering method. As the lower fourth conductive material 222, it is preferable to use Cu having low resistance. Further, the lower fourth conductive material 222 serves as a seed layer for growing Cu by the electrolytic plating method.

Next, as shown in FIG. 13, a photoresist is applied on the lower fourth conductive material 222, and then exposure and development are performed to form a wiring forming resist pattern 320. Then, by using an electrolytic plating method to grow the same material as the lower fourth conductive material 222 on the lower fourth conductive material 222 exposed from the wiring forming resist pattern 320, the upper fourth conductive material 222 is grown as shown in FIG. 4 Form the conductive material 223. In FIG. 14, a manufacturing method for growing the same material as the lower fourth conductive material 222 as the upper fourth conductive material 223 is illustrated, but the method is not limited to this method, and the upper fourth conductive material 223 is used as the lower fourth conductive material. Materials different from 222 may be grown.

Next, after forming the upper fourth conductive material 223, the photoresist forming the wiring forming resist pattern 320 is removed with an organic solvent to obtain the structure of FIG. 15. In addition, for removing the photoresist, ashing with oxygen plasma can be used instead of using an organic solvent.

Next, as shown in FIG. 16, a part of the lower fourth conductive material 222 and a part of the third conductive material 221 covered by the wiring forming resist pattern 320 are etched with an acidic chemical solution to form a third. The conductive layer 121 and the fourth conductive layer 122 are formed. Since the film thickness of the upper fourth conductive material 223 is reduced by this etching, it is preferable to set the film thickness of the upper fourth conductive material 223 in consideration of the influence of this thinning. Further, instead of the above-mentioned etching with a chemical solution, ion milling, dry etching or the like can be used.

Next, as shown in FIG. 17, a third inorganic insulating layer 123 and a fourth inorganic insulating layer 124 are formed on the fourth conductive layer 122. For example, when the fourth conductive layer 122 contains Cu, it is preferable to use a SiN film having a barrier property against Cu as the third inorganic insulating layer 123, like the first inorganic insulating layer 113, and the fourth inorganic insulating layer. As the layer 124, it is preferable to use a SiO ₂ film as in the case of the second inorganic insulating layer 114. Instead of using the SiN film as the barrier insulating layer as the third inorganic insulating layer 123, a SiC film (which may contain several% to 10% of oxygen) can be used. Further, as the fourth inorganic insulating layer 124, a SiOC film, a SiOF film, or the like may be used instead of the SiO ₂ film.

Next, a second organic insulating layer 125 such as polyimide is applied onto the fourth inorganic insulating layer 124 by a spin coating method. Benzocyclobutene or the like may be used instead of polyimide. Further, the present invention is not limited to the photosensitive resin, and a non-photosensitive resin may be used.

Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, and BT resin. , FR-4, FR-5, Polyacetal, Polybutylene terephthalate, Syndiotactic polystyrene, Polyphenylene sulfide, Polyether ether ketone, Polyethernitrile, Polycarbonate, Polyphenylene ether Polysulfone, Polyethersulfone, Polyarylate, Polyetherimide, etc. Can be used. The above resin may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, or alumina may be used in combination with the above resin.

In the first embodiment, a manufacturing method using photosensitive polyimide as the second organic insulating layer 125 will be described.

When the second organic insulating layer 125 is applied, it is exposed with a photomask and then developed to form a recess 282 at a required position above the fourth conductive layer 122, as shown in FIG. .. Here, the “necessary position” refers to a position where a via for connecting the fourth conductive layer 122 to the wiring formed in the upper layer thereof needs to be arranged.

After forming the recess 281, in order to cure the second organic insulating layer 125, a thermosetting treatment is performed at a temperature equal to or lower than the glass transition temperature of the second organic insulating layer 125. For example, when polyimide is used as the second organic insulating layer 125, if the glass transition temperature of the polyimide is 280 ° C, it is set to 250 ° C as described above. Not limited to the thermosetting treatment, the heat treatment after this step is preferably performed so as not to exceed the glass transition temperature of the polyimide.

Next, the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124 at the bottom of the recess 282 are etched by plasma etching using the second organic insulating layer 125 as a mask. As the plasma etching method, the same method as the etching method of the first inorganic insulating layer 113 and the second inorganic insulating layer 114 can be used. By etching the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124, an opening 182 for filling the second via 192 that electrically connects the second wiring layer 120 and the third wiring layer 130 is formed. Ru. In this way, the structure shown in FIG. 19 can be obtained.

Hereinafter, by repeating the methods described with reference to FIGS. 11 to 19, the multilayer wiring structure shown in FIG. 1 can be obtained.

<Second Embodiment>
Hereinafter, the multilayer wiring structure according to the second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 22 is a cross-sectional view of the multilayer wiring structure according to the second embodiment of the present invention. FIG. 22 is similar to FIG. 1 in that a multilayer wiring structure is formed on one surface of the substrate 100, but has a back surface insulating layer 102 patterned on the other surface of the substrate 100. Different from 1.

The back surface insulating layer 102 has an opening 103 at the same plane coordinates as the opening 180 formed in the intermediate layer 101 in a plan view. In other words, the opening 180 or the conductive portion 190 formed in the intermediate layer 101 and the opening 103 formed in the back surface insulating layer 102 overlap each other in a plan view. The back surface insulating layer 102 may be made of the same material as the intermediate layer 101, and a resin material such as polyimide can be used. Further, the planar shape of the back surface insulating layer 102 may be the same shape as the opening 180 (for example, dot shape).

According to the above structure, it is possible to alleviate the distortion of the substrate due to the stress generated in the multilayer wiring structure and the intermediate layer 101 by the heat treatment step. Further, by arranging the opening 103 so that the back surface insulating layer 102 overlaps with the opening 180 in a plan view, the stress generated by the intermediate layer 101 can be more effectively relaxed. As a result, it is possible to provide a multilayer wiring structure in which distortion of the substrate is suppressed. Further, the substrate 100 can be connected to an external grounding member via the opening 103 formed in the back surface insulating layer 102, and more stable ground characteristics can be obtained.

<Third Embodiment>
Hereinafter, the multilayer wiring structure according to the third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 23 is a cross-sectional view of the multilayer wiring structure according to the third embodiment of the present invention. FIG. 23 is similar to FIG. 1 in that the opening 180 and the conductive portion 190 formed in the intermediate layer 101 are arranged at different plane coordinates from the plurality of vias formed in the upper layer thereof. Different from 1. In other words, the conductive portion 190 and the first to fourth vias (191, 192, 193, 194) are arranged at different positions in a plan view. In other words, at least the conductive portion 190 and the first via 191 are arranged at different positions in a plan view. In other words, the conductive portion 190 and the first via 191 have a crank structure.

According to the above structure, even in the stack via structure of the ground wire 900, the stress in the three-dimensional direction generated by the heat treatment step can be relaxed by the intermediate layer 101. As a result, problems such as cracks in the vias and the inorganic insulating layer and peeling of the vias and the wiring can be suppressed even in the vicinity of the ground wire 900.

<Fourth Embodiment>
Hereinafter, the multilayer wiring structure according to the fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 24 is a cross-sectional view of the multilayer wiring structure according to the fourth embodiment of the present invention. FIG. 24 is similar to FIG. 23 in that a multilayer wiring structure is formed on one surface of the substrate 100, but has a back surface insulating layer 102 patterned on the other surface of the substrate 100. Different from 23.

The back surface insulating layer 102 has an opening 103 at the same plane coordinates as the opening 180 formed in the plurality of laminated vias and the intermediate layer 101 in a plan view. In other words, the plurality of vias and openings 180 and the openings 103 formed in the back surface insulating layer 102 overlap each other in a plan view. The back surface insulating layer 102 may be made of the same material as the intermediate layer 101, and a resin material such as polyimide can be used. Further, the planar shape of the back surface insulating layer 102 may be the same shape (for example, dot shape) as the opening 180 of the intermediate layer 101 or the openings 181 to 184 of the multilayer wiring structure.

Further, FIG. 25 is a cross-sectional view of a multilayer wiring structure according to a modified example of the fourth embodiment of the present invention. FIG. 25 differs from FIG. 24 in that the plurality of stacked vias are arranged at different plane coordinates. In other words, in FIG. 25, a plurality of stacked vias are arranged at different positions in a plan view. In other words, the plurality of laminated vias have a crank structure. Further, FIG. 25 illustrates a structure in which the back surface insulating layer 102 is provided with a plurality of vias and an opening 103 so as to overlap with the opening 180 in a plan view, but the structure is not limited to this structure, and at least one location is provided. It suffices to have an opening capable of establishing continuity with the substrate 100.

According to the above structure, it is possible to alleviate the distortion of the substrate due to the stress generated in the multilayer wiring structure and the intermediate layer 101 by the heat treatment step. Further, by arranging the opening 103 in the back surface insulating layer 102 so as to overlap the opening 180 of the intermediate layer 101 and the openings 181 to 184 of the multilayer wiring structure in a plan view, the back surface insulating layer 102 becomes the intermediate layer 101. And the stress generated by the plurality of interlayer films (119, 129, 139, 149, 159) of the multilayer wiring structure can be more effectively relieved. As a result, it is possible to provide a multilayer wiring structure in which distortion of the substrate is suppressed. Further, the substrate 100 can be connected to an external grounding member via the opening 103 formed in the back surface insulating layer 102, and more stable ground characteristics can be obtained.

<Fifth Embodiment>
Hereinafter, the multilayer wiring structure according to the fifth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 26 is a cross-sectional view of the multilayer wiring structure according to the fifth embodiment of the present invention. FIG. 26 is similar to FIG. 1, but differs from FIG. 1 in that a ground auxiliary layer 104 is provided between the substrate 100 and the intermediate layer 101. The ground auxiliary layer 104 is preferably made of a material having at least a lower intrinsic resistance than the conductive substrate 100 and a lower contact resistance with the conductive portion 190. That is, the ground auxiliary layer 104 is preferably a metal layer.

According to the above structure, the contact resistance between the conductive portion 190 and the substrate 100 can be further reduced. Further, when a plurality of ground wires are connected to the substrate 100 via the plurality of conductive portions 190, the plurality of ground wires can be connected to each other with low resistance. Therefore, more stable ground characteristics can be obtained.

Hereinafter, the present invention will be specifically described with reference to Example 1 shown in FIG. 27, but the present invention is not limited to these Examples. FIG. 27 is a cross-sectional view of the multilayer wiring structure according to the first embodiment of the present invention. In the first embodiment, an example in which an eight-layer wiring structure is produced by adding two wiring layers to the multilayer wiring structure of the first embodiment will be described.

First, as the substrate 100, a silicon substrate having a thickness of 400 μm was prepared. Next, as an insulating intermediate layer 101, a photosensitive polyimide of 10 μm was applied onto the substrate 100 by a spin coating method, exposed using a photomask, and then developed, and an intermediate having an opening 180 having a diameter of 20 μm was formed. The layer 101 is formed. The Young's modulus of the polyimide is 3 to 3.5 GPa, and the Young's modulus of the silicon substrate is about 185 GPa. That is, the intermediate layer 101 has a Young's modulus lower than that of the substrate 100. In other words, the intermediate layer 101 is softer than the substrate 100. In addition, polyimide has a barrier property against Cu used for the wiring layer described later. That is, polyimide has a slower Cu diffusion rate than a silicon substrate.

The first wiring layer 110 and the conductive portion 190 are formed in the same process on the intermediate layer 101 and inside the opening 180. The first wiring layer 110 and the conductive portion 190 are formed by laminating Ti having a thickness of 50 nm as the first conductive layer 111 and Cu having a thickness of 4 μm as the second conductive layer 112. Here, Ti of the first conductive layer 111 has a barrier property against Cu of the second conductive layer 112. The inside of the opening 180 is covered with Ti of the first conductive layer, and is formed so as to separate the Cu of the second conductive layer from the inside of the opening 180 of the intermediate layer 101. Further, the wiring pattern of the first wiring layer 110 can be formed with a line width of 10 to 100 μm.

In Example 1 shown in FIG. 27, the second to seventh wiring layers (120, 130, 140, 150, 160, 170) are also formed with the same laminated structure and pattern line width as the first wiring layer 110. That is, the third, fifth, seventh, ninth, 11, and thirteen conductive layers (121, 131, 141, 151, 161 and 171) are formed of the same Ti as the first conductive layer 111, and the fourth, sixth, eighth, and tenth are formed. , 12, 14 conductive layers (122, 132, 142, 152, 162, 172) are formed of the same Cu as the second conductive layer 112.

When the first wiring layer 110 is formed on the intermediate layer 101, the first interlayer film 119 is formed so as to cover them. The first interlayer film 119 includes a SiN film having a thickness of 10 nm as the first inorganic insulating layer 113, a SiO ₂ film having a thickness of 2 μm as the second inorganic insulating layer 114, and a polyimide having a thickness of 12 μm as the first organic insulating layer 115. And are formed by stacking. Here, the SiN film of the first inorganic insulating layer 113 and the SiO ₂ film of the second inorganic insulating layer 114 are formed by using the plasma CVD method. Further, the polyimide of the first organic insulating layer 115 relaxes or flattens the step formed by the first wiring layer 110. That is, the polyimide film thickness 115b of the first organic insulating layer 115 on the first wiring layer 110 is compared with the polyimide film thickness 115a of the first organic insulating layer 115 on the intermediate layer 101 in which the first wiring layer 110 does not exist. It will be formed thin. In Example 1 shown in FIG. 27, the film thickness 115a was 12 μm, and the film thickness 115b was 8 μm, which was approximately as thin as the film thickness of the first wiring layer 110.

Subsequently, an opening 181 is formed in the first interlayer film 119. The opening 181 has a diameter of 15 μm. The opening 181 is first coated with photosensitive polyimide as the first organic insulating layer 115, exposed to light using a photomask, and then developed. At the position where the opening 181 is provided, the lower second inorganic insulating layer 114 Form a recess to expose. Using the photosensitive polyimide of the first organic insulating layer 115 as a mask, the second inorganic insulating layer 114 exposed in the recess and the first inorganic insulating layer 113 below the second inorganic insulating layer 113 were formed by plasma etching. A mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) was used for etching the SiO ₂ film of the second inorganic insulating layer 114. A mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) was used for etching the SiN film of the first inorganic insulating layer 113.

Subsequently, the second wiring layer 120 and the first via 191 are formed on the first interlayer film 119 and inside the opening 181 in the same process. Similar to the first wiring layer 110, the second wiring layer 120 and the first via 191 are formed by laminating Ti having a thickness of 50 nm as the third conductive layer 121 and Cu having a thickness of 4 μm as the fourth conductive layer 122. Form. Here, Ti of the third conductive layer 121 has a barrier property against Cu of the fourth conductive layer 122. The inside of the opening 181 is covered with Ti of the third conductive layer 121, and is formed so as to separate the Cu of the fourth conductive layer 122 from the inside of the opening 181 of the first interlayer film 119.

The diameter 191a of the first via 191 is 15 μm, which is the same as the diameter of the opening 181 and the diameter 191b of the land located above the first via 191 is 30 μm. The via pitch, which indicates the distance between the centers of adjacent vias, is 40 μm at the smallest pitch.

As described above, the first wiring layer, the first interlayer film, and the first via are formed. Similar to these, the second to seventh wiring layers, interlayer films, and second to sixth vias are formed. Then, the eighth wiring layer 380 and the seventh via 197 of the uppermost layer are formed in the same process on the seventh interlayer film 179 and inside the opening 187 provided in the seventh interlayer film 179. The eighth wiring layer 380 is formed by laminating Cu having a thickness of 3 μm as the 15th conductive layer 381, Ni having a thickness of 1 μm as the 16th conductive layer 382, and Au having a thickness of 1 μm as the 17th conductive layer 383. Will be done.

As described above, according to the first embodiment, by providing an insulating intermediate layer having the above-mentioned characteristics between the substrate and the multilayer wiring structure, it is possible to prevent Cu from diffusing to the substrate by the heat treatment step. be able to. As a result, since the problem that the first wiring layer and the substrate are short-circuited can be suppressed, the first wiring layer 110 can be used for the signal line 800, and the wiring whose characteristic impedance is matched can be arranged. .. Further, by connecting the ground wire 900 to the conductive substrate 100, more stable ground characteristics can be obtained.

The present invention is not limited to the above embodiment, and can be appropriately modified without departing from the spirit.

100: Substrate 101: Intermediate layer 102: Back surface insulating layer 103: Opening 104: Ground auxiliary layer 110: First wiring layer 111: First conductive layer 112: Second conductive layer 113: First inorganic insulating layer 114: Second Inorganic insulating layer 115: First organic insulating layer 119: First interlayer film 120, 126, 127: Second wiring layer 121: Third conductive layer 122: Fourth conductive layer 123: Third inorganic insulating layer 124: Fourth inorganic Insulating layer 125: Second organic insulating layer 129: Second interlayer film 130: Third wiring layer 131: Fifth conductive layer 132: Sixth conductive layer 133: Fifth inorganic insulating layer 134: Sixth inorganic insulating layer 135: Third 3 Organic insulating layer 139: 3rd interlayer film 140: 4th wiring layer 141: 7th conductive layer 142: 8th conductive layer 143: 7th inorganic insulating layer 144: 8th inorganic insulating layer 145: 4th organic insulating layer 149 : 4th interlayer film 150: 5th wiring layer 151: 9th conductive layer 152: 10th conductive layer 153: 9th inorganic insulating layer 154: 10th inorganic insulating layer 155: 5th organic insulating layer 159: 5th interlayer film 160: 6th wiring layer 161: 11th conductive layer 162: 12th conductive layer 163: 13th conductive layer 180, 181, 182, 185: opening 190: conductive portion 191: 1st via 192: 2nd via 193: 3rd via 194: 4th via 211: 1st conductive material 212: Lower 2nd conductive material 213: Upper 2nd conductive material 221: 3rd conductive material 222: Lower 4th conductive material 223: Upper 4th conductive material 281 282: Recessed 301: Undercut 302: Step 310, 320: Conducting pattern for wiring formation 800: Signal line 900: Ground line

Claims (8)

With a conductive layer
It has a multi-layer wiring structure in which a plurality of wiring layers are laminated on one surface of the conductive layer.
The multilayer wiring structure includes a plurality of first vias that connect adjacent wiring layers and overlap each other in a plan view and a plurality of second vias that overlap each other in a plan view .
One of the plurality of first vias and one of the plurality of second vias form a crank structure.
At least one wiring layer of the plurality of wiring layers includes a ground line,
Wherein between the layer having a multilayer wiring structure of the conductive, insulating intermediate layer having a first opening is provided directly on one surface of the layer having the conductivity,
Conducting portion is provided to connect the layers and the ground line with the conductive to the first opening,
An insulating layer is provided on the other surface of the conductive layer.
The insulating layer has a second opening and a second opening.
The second 1 opening overlaps with one of the plurality of first vias.
A multilayer wiring structure characterized in that the second second opening is superimposed on one of the plurality of second vias . The multilayer wiring structure according to claim 1, wherein the intermediate layer is a layer made of a resin material. The multilayer wiring structure according to claim 1 or 2, wherein the insulating layer is a layer made of a resin material. The multilayer wiring structure according to any one of claims 1 to 3, wherein the intermediate layer has a Young's modulus lower than that of the conductive layer. The multilayer wiring structure according to any one of claims 1 to 3, wherein the intermediate layer has a higher coefficient of thermal expansion than the conductive layer. The invention according to any one of claims 1 to 5, wherein the conductive portion, the second 1 opening, and any one of the second 2 openings are superimposed on each other in a plan view. Multi-layer wiring structure. The multilayer wiring structure according to any one of claims 1 to 6, wherein at least one of the plurality of wiring layers has a first inorganic insulating layer that covers at least a part of the one wiring layer. body. The multilayer wiring structure according to claim 7, further comprising a second inorganic insulating layer that covers at least a part of the first inorganic insulating layer.

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