JP6330374B2 - Multilayer wiring structure - Google Patents

Description

  The present invention relates to a multilayer wiring structure, and one disclosed embodiment relates to a laminated structure of a substrate and a multilayer wiring structure.

  In recent years, with the performance enhancement of integrated circuits, integrated circuits have become more complex, and the number of elements such as transistors constituting the integrated circuit has increased. As the number of elements increases, the arrangement of wirings that connect the elements also becomes complicated, and the area occupied by the wirings in the integrated circuit substrate increases. Therefore, in order to reduce the occupied area in the plane direction of the wiring as much as possible in the integrated circuit substrate, development of a multilayer wiring technique in which a plurality of wirings are stacked and the wirings are routed three-dimensionally is underway. In particular, a multilayer wiring technique having a so-called stacked via structure in which vias are stacked in order to improve wiring density has been developed (for example, Patent Document 1).

  In a multilayer wiring structure such as a stacked via structure, cracks occur in the interlayer film that separates the vias connecting the stacked wirings and the stacked wirings due to expansion and contraction of each layer in the thermal cycle (heat treatment step), The multilayer wiring structure and the substrate may peel off. As described above, when a crack occurs in the interlayer film, the metal atoms of the wiring material may thermally diffuse through the crack and reach the substrate, and the wiring and the substrate may be short-circuited. Therefore, there arises a problem that the wiring layer disposed closest to the substrate of the multilayer wiring structure cannot be used as a signal line.

  Furthermore, since the wiring layer is laminated on one surface of the substrate, the substrate may be distorted by the stress of the laminated wiring layer or interlayer film. In order to relieve this stress, it is necessary to adjust the material of the film to be laminated and the film formation conditions, which causes a problem that the degree of freedom in design is limited.

JP 2006-173333 A

  In view of the above circumstances, an object of the present invention is to provide a multilayer wiring structure in which the degree of freedom of design is improved in the multilayer wiring structure.

  A multilayer wiring structure according to an embodiment of the present invention includes a conductive substrate and a multilayer wiring structure in which a plurality of wiring layers are stacked on one surface of the substrate, and the multilayer wiring structure is adjacent to each other. A plurality of vias overlapping each other in plan view, at least one of the plurality of wiring layers includes a signal line and a ground line, and between the multilayer wiring structure and the substrate, An insulating intermediate layer having a first opening is provided, and a conduction portion for connecting the substrate and the ground line is provided in the first opening.

  According to this multilayer wiring structure, in the multilayer wiring structure, the wiring layer closest to the substrate can be used as the signal line.

  In another preferred embodiment, at least one wiring layer has a conductive layer containing Cu, and the diffusion rate of Cu may be slower in the intermediate layer than in the substrate.

  According to this multilayer wiring structure, Cu can be prevented from diffusing into the substrate.

  In another preferred embodiment, the intermediate layer may be a resin material.

  According to this multilayer wiring structure, local stress due to expansion and contraction of each layer caused by the heat treatment process can be relieved.

  Moreover, in another preferable aspect, you may have the insulating layer patterned on the other surface of the board | substrate.

  In another preferred embodiment, the insulating layer may be a resin material.

  In another preferred embodiment, the insulating layer may have a second opening.

  In another preferable aspect, the conducting portion and the second opening may overlap each other in plan view.

  In another preferable aspect, the plurality of vias and the second opening may overlap each other in plan view.

  According to this multilayer wiring structure, the stress generated by the intermediate layer or multilayer wiring structure laminated on one surface of the substrate can be relaxed.

  Moreover, in another preferable aspect, you may have a metal layer between a board | substrate and an intermediate | middle layer.

  According to this multilayer wiring structure, the contact resistance between the ground line and the substrate can be lowered, and more stable ground characteristics can be ensured.

  A multilayer wiring structure according to an embodiment of the present invention includes a conductive substrate and a multilayer in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially stacked on one surface of the substrate from the substrate side. The multilayer wiring structure includes a first via that connects the first wiring layer and the second wiring layer, and a second wiring layer that connects the third wiring layer, and the first via in a plan view. The first wiring layer includes a signal line and a ground line, has a first opening between the multilayer wiring structure and the substrate, and has a lower Young's modulus than the substrate. An insulating intermediate layer is provided, and a conductive portion that connects the substrate and the ground line is provided in the first opening.

  A multilayer wiring structure according to an embodiment of the present invention includes a conductive substrate and a multilayer in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially stacked on one surface of the substrate from the substrate side. The multilayer wiring structure includes a first via that connects the first wiring layer and the second wiring layer, and a second wiring layer that connects the third wiring layer, and the first via in a plan view. The first wiring layer includes a signal line and a ground line, has a first opening between the multilayer wiring structure and the substrate, and has a thermal expansion coefficient higher than that of the substrate. An insulating intermediate layer that is higher and has a lower thermal expansion coefficient than the first wiring layer is provided, and a conductive portion that connects the substrate and the ground line is provided in the first opening.

  According to this multilayer wiring structure, in the multilayer wiring structure, the wiring layer closest to the substrate can be used as the signal line. Further, local stress due to expansion and contraction of each layer that occurs in the heat treatment process can be reduced.

  In another preferable aspect, the first via and the conductive portion may be arranged at different positions in plan view.

  In another preferred embodiment, the first wiring layer may have a conductive layer containing Cu, and the intermediate layer may have a slower Cu diffusion rate than the substrate.

  According to this multilayer wiring structure, Cu can be prevented from diffusing into the substrate.

  In another preferred embodiment, the intermediate layer may be a resin material.

  According to this multilayer wiring structure, local stress due to expansion and contraction of each layer caused by the heat treatment process can be relieved.

  Moreover, in another preferable aspect, you may have the insulating layer patterned on the other surface of the board | substrate.

  In another preferred embodiment, the insulating layer may be a resin material.

  In another preferred embodiment, the insulating layer may have a second opening.

  In another preferable aspect, the conducting portion and the second opening may overlap each other in plan view.

  In another preferred embodiment, the first via, the second via, and the second opening may overlap each other in plan view.

  According to this multilayer wiring structure, the stress generated by the intermediate layer or multilayer wiring structure laminated on one surface of the substrate can be relaxed.

  Moreover, in another preferable aspect, you may have a metal layer between a board | substrate and an intermediate | middle layer.

  According to this multilayer wiring structure, the contact resistance between the ground line and the substrate can be lowered, and more stable ground characteristics can be ensured.

  According to the present invention, it is possible to provide a multilayer wiring structure having an improved design freedom in the multilayer wiring structure.

1 is a cross-sectional view of a multilayer wiring structure according to a first embodiment of the present invention. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which an intermediate layer which has an opening was formed. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which the 1st conductive material and the lower 2nd conductive material were formed. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of the substrate by which the photoresist was formed on the lower 2nd conductive material. In the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention, it is a cross-sectional view of a substrate in which an upper second conductive material is formed on a lower second conductive material. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate from which the photoresist on the lower 2nd electric conduction material was removed. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which the pattern of the 1st wiring layer was formed by etching. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate by which the 1st inorganic insulating layer and the 2nd inorganic insulating layer were formed on the 1st wiring layer. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate by which the 1st organic insulating layer was formed on the 2nd inorganic insulating layer. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which an opening was formed in the 1st inorganic insulating layer and the 2nd inorganic insulating layer. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of the substrate by which the 3rd conductive material was formed on the 1st organic insulating layer. In the manufacturing method of the multilayer wiring structure according to the first embodiment of the present invention, it is a cross-sectional view of a substrate in which a lower fourth conductive material is formed on a third conductive material. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of the substrate by which the photoresist was formed on the lower 4th electric conduction material. In the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention, it is a cross-sectional view of a substrate in which an upper fourth conductive material is formed on a lower fourth conductive material. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of the substrate from which the photoresist on the lower 4th electric conduction material was removed. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which the pattern of the 2nd wiring layer was formed by etching. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate by which the 3rd inorganic insulating layer and the 4th inorganic insulating layer were formed on the 2nd wiring layer. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate by which the 2nd organic insulating layer was formed on the 4th inorganic insulating layer. In the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention, it is a sectional view of a substrate in which an opening was formed in the 3rd inorganic insulating layer and the 4th inorganic insulating layer. It is sectional drawing of the board | substrate explaining the detail of the method of etching the pattern of a wiring layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the board | substrate explaining the detail of the method of forming an organic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 2nd Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 3rd Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 4th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on the modification of 4th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on 5th Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on Example 1 of this invention.

<First Embodiment>
Hereinafter, a multilayer wiring structure according to a first embodiment of the present invention will be described in detail with reference to the drawings. In addition, embodiment shown below is an example of embodiment of this invention, This invention is limited to these embodiment, and is not interpreted. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference symbols or similar symbols, and repeated description thereof may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

[Configuration of multilayer wiring structure]
FIG. 1 is a cross-sectional view of a multilayer wiring structure according to the first embodiment of the present invention. In FIG. 1, as an example of a multilayer wiring structure, a cross-sectional view of a six-layer wiring structure will be described.

  In FIG. 1, the first to sixth wiring layers (110, 120, 130, 140, 150, 160) and the first to sixth wiring layers are separated from each other on one surface of the conductive substrate 100. The first to fifth interlayer films (119, 129, 139, 149, 159) to be connected to the adjacent wiring layers among the first to fifth wiring layers (110, 120, 130, 140, 150) are connected. A multilayer wiring structure having through vias (191, 192, 193, 194) is formed. Here, the first to fourth vias (191, 192, 193, 194) overlap each other in plan view.

  In FIG. 1, each of the first to sixth wiring layers has a signal line 800 and a ground line 900. In addition, an insulating intermediate layer 101 having an opening 180 is provided between the substrate 100 and the first wiring layer 110 which is the lowermost wiring layer of the multilayer wiring structure. A conductive portion 190 that connects the first wiring layer 110 of the line 900 is formed. In FIG. 1, the structure in which the conductive portion 190 is formed by filling a part of the first wiring layer 110 in the opening 180 is illustrated. However, the structure is not limited to this structure. A conductive layer different from the one wiring layer 110 may be used.

  In FIG. 1, the first wiring layer 110 includes a first conductive layer 111 and a second conductive layer 112. The second conductive layer 112 is preferably a metal material with low electrical resistance. For example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), or the like can be used. Alternatively, an aluminum alloy such as an aluminum-neodymium alloy (Al—Nd) or an aluminum-copper alloy (Al—Cu) can be used. As the first conductive layer 111, it is preferable to use a material having adhesiveness and a barrier property to the second conductive layer 112. For example, when Cu is used as the second conductive layer 112, the first conductive layer 111 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), or the like. Can be used. In FIG. 1, a laminated structure of two conductive layers is illustrated as the wiring layer. However, the present invention is not limited to this structure, and may be a single-layer structure of one conductive layer, or three or more conductive layers. A laminated structure may be used.

  In FIG. 1, the first interlayer film 119 includes a first inorganic insulating layer 113, a second inorganic insulating layer 114, and a first organic insulating layer 115. The first inorganic insulating layer 113 is formed so as to cover the first conductive layer 111, the second conductive layer 112, and the exposed intermediate layer 101. The second inorganic insulating layer 114 is formed so as to cover the first inorganic insulating layer 113, and the first organic insulating layer 115 is further formed thereon. Here, the dielectric constant of the first organic insulating layer 115 is preferably lower than the dielectric constant of each of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. The first interlayer film 119 is not limited to the above three-layer structure, and may be configured to include at least one organic insulating layer or inorganic insulating layer.

The first inorganic insulating layer 113 is preferably made of a material having a barrier property with respect to the second conductive layer 112. In other words, the first inorganic insulating layer 113 is preferably made of a material having a slower diffusion rate of the second conductive layer 112 than the second inorganic insulating layer 114 and the first organic insulating layer 115. For example, when Cu is used as the second conductive layer 112, the first inorganic insulating layer 113 includes silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC). Silicon nitride carbide (SiCN), carbon-added silicon oxide (SiOC), or the like can be used. The first inorganic insulating layer 113 is preferably formed under film formation conditions with good coverage. Further, when Cu is used as the second conductive layer 112 and SiN is used as the first inorganic insulating layer 113, it is preferable that the film has a certain thickness or more in order to obtain a Cu diffusion preventing function. Since the ratio is as high as 7.5, it is preferable to set the film thickness to a certain value or less in order to suppress parasitic capacitance between wiring layers. Specifically, the thickness of the SiN film is preferably 10 nm or more and 200 nm or less. More preferably, it is 50 nm or more and 100 nm or less.

  The first inorganic insulating layer 113 preferably prevents the first inorganic insulating layer 113 from being cracked or a region having a rough film at the step formed by the first wiring layer 110. For example, the first inorganic insulating layer 113 is desirably formed under a condition where the deposition temperature is high, and is preferably 200 ° C. or higher. More preferably, it is good at 300 degreeC or more. Further, in order to improve the coverage of the first inorganic insulating layer 113, the end surface of the first wiring layer 110 may have a forward taper shape inclined with respect to the surface of the intermediate layer 101. The taper angle of the first wiring layer 110 is preferably 30 degrees or more and 90 degrees or less. More preferably, it is 30 degrees or more and 60 degrees or less. Here, both the first conductive layer 111 and the second conductive layer 112 included in the first wiring layer 110 do not have to have a forward taper shape, and any one of them may be a forward taper shape.

The second inorganic insulating layer 114 is preferably made of a material having good adhesion to the first inorganic insulating layer 113 and the first organic insulating layer 115 formed thereon. For example, as the second inorganic insulating layer 114, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like can be used. The second inorganic insulating layer 114 is preferably formed under film formation conditions with good coverage. In addition, the SiO ₂ film is preferably a film thickness of a certain level or more for adjusting the warpage of the substrate and improving the reliability. If the film thickness is too large, the film cannot be balanced with the stress of PI, and the film is less than a certain level. Thickness is preferred. Specifically, the thickness of the SiO ₂ film is preferably 1 μm or more and 8 μm or less. More preferably, it is 2 μm or more and 5 μm or less.

  The first organic insulating layer 115 is made of a material that relaxes or flattens the step formed by the first wiring layer 110 and has a dielectric constant lower than that of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Preferably, it is good to form with resin materials, such as photosensitive polyimide, for example. The film thickness of the first organic insulating layer 115 is preferably at least equal to or greater than the step formed by the first wiring layer 110, and a coating process is possible in order to reduce the parasitic capacitance between the wiring layers. It is preferable to form it as thick as possible. Specifically, the film thickness of the first organic insulating layer is preferably 4 μm or more and 24 μm or less. More preferably, it is 8 μm or more and 20 μm or less. Moreover, photosensitive acrylic, photosensitive siloxane, etc. can be used instead of photosensitive polyimide. In addition, benzocyclobutene having a low dielectric constant and a barrier property against Cu may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyether ether ketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyetherimide, etc. Can be used. The above resins may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  An opening 181 is provided in the first interlayer film 119, and the inside of the opening 181 is filled with a first via 191. In FIG. 1, the structure in which the first via 191 is formed by filling a part of the second wiring layer 120 into the opening 181 is illustrated, but the structure is not limited to this structure. For example, as the first via 191, A conductive layer different from the second wiring layer 120 may be used. 1 illustrates a structure in which the opening 181 and the first via 191 have a shape perpendicular to the substrate. However, the present invention is not limited to this structure, and the opening 181 and the first via 191 are formed with respect to the substrate. It may have a forward tapered shape, and the opening 181 and the first via 191 may have a reverse tapered shape with respect to the substrate. 1 illustrates a structure in which the opening 181 is filled with a conductive layer, the vias may connect adjacent wiring layers, and a part of the opening 181 may be a cavity.

  As shown in FIG. 1, when the second wiring layer 120 is used as the first via 191, as the fourth conductive layer 122, copper (Cu), silver (Ag), Gold (Au), aluminum (Al), or the like can be used. Alternatively, an aluminum alloy such as an aluminum-neodymium alloy (Al—Nd) or an aluminum-copper alloy (Al—Cu) can be used. Further, as the third conductive layer 121, it is preferable to use a material having a barrier property with respect to the fourth conductive layer 122 like the first conductive layer 111. For example, when the fourth conductive layer 122 contains Cu, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium), or the like is used as the third conductive layer 121. can do.

  The first via 191 is in contact with the second conductive layer 112 of the first wiring layer 110 at the bottom thereof, and the first wiring layer 110 and the second wiring layer 120 are electrically connected. In FIG. 1, the second wiring layers 126 and 127 are not connected to the upper and lower wiring layers, but may be connected to the upper and lower wiring layers at locations different from the cross section shown in FIG. 1.

  A second interlayer film 129 is formed on the second wiring layer 120. The second interlayer film 129 has the same structure as the first interlayer film 119 and includes a third inorganic insulating layer 123, a fourth inorganic insulating layer 124, and a second organic insulating layer 125. In FIG. 1, since the material used for each layer of the second interlayer film 129 is the same material as each layer of the first interlayer film 119, detailed description thereof is omitted here. However, the material used for each layer of the second interlayer film 129 is not limited to the same material as each layer of the first interlayer film 119, and can be appropriately selected according to the purpose of the interlayer film.

  Thereafter, the third to fifth wiring layers (130, 140, 150) can be formed in the same manner as the second wiring layer 120. The fifth conductive layer 131 of the third wiring layer 130, the seventh conductive layer 141 of the fourth wiring layer 140, and the ninth conductive layer 151 of the fifth wiring layer 150 may be formed of the same material as the first conductive layer 111, respectively. it can. Further, the sixth conductive layer 132 of the third wiring layer 130, the eighth conductive layer 142 of the fourth wiring layer 140, and the tenth conductive layer 152 of the fifth wiring layer 150 are each formed of the same material as the second conductive layer 112. be able to. However, these conductive layers are not necessarily the same as the first conductive layer 111 or the second conductive layer 112, and can be appropriately selected according to the purpose of the wiring layer.

  Similarly to the second interlayer film 129, third to fifth interlayer films (139, 149, 159) can be formed. The fifth inorganic insulating layer 133 of the third interlayer film 139, the seventh inorganic insulating layer 143 of the fourth interlayer film 149, and the ninth inorganic insulating layer 153 of the fifth interlayer film 159 are made of the same material as the first inorganic insulating layer 113, respectively. Can be formed. The sixth inorganic insulating layer 134 of the third interlayer film 139, the eighth inorganic insulating layer 144 of the fourth interlayer film 149, and the tenth inorganic insulating layer 154 of the fifth interlayer film 159 are the same as the second inorganic insulating layer 114, respectively. Can be made of material. In addition, the third organic insulating layer 135 of the third interlayer film 139, the fourth organic insulating layer 145 of the fourth interlayer film 149, and the fifth organic insulating layer 155 of the fifth interlayer film 159 are the same as the first organic insulating layer 115, respectively. Can be made of material. However, these insulating layers are not necessarily the same as the first inorganic insulating layer 113, the second inorganic insulating layer 114, or the first organic insulating layer 115, and may be appropriately selected depending on the purpose of the insulating layer. it can.

  The first to fourth vias (191, 192, 193, 194) have a so-called stacked via structure in which the first to fourth vias are stacked with the same plane coordinates. In other words, the first to fourth vias (191, 192, 193, 194) overlap each other in plan view. Here, the vias to be overlapped are not limited to a structure in which the vias are completely overlapped in a plan view, and include, for example, a structure in which a part of the vias overlap. In the stacked via structure shown in FIG. 1, a structure in which all stacked vias are overlapped with each other in a plan view is illustrated, but the present invention is not limited to this structure, and at least vias formed above and below a certain wiring layer are in a plan view. As long as they overlap each other. For example, the first via 191 below the second wiring layer 120 and the second via 192 above only have to overlap at least partially in plan view.

  In FIG. 1, the first to fourth vias (191, 192, 193, 194) are all illustrated with the same diameter. However, the present invention is not limited to this structure, and even if the via diameter varies depending on the layer. Good. For example, the upper layer via (for example, the fourth via 194) may have a larger diameter than the lower layer via (for example, the first via 191). Moreover, the diameter of the via of a specific layer may be different from the diameter of the via of another layer.

  In FIG. 1, the fifth wiring layer 150 is connected to the uppermost sixth wiring layer 160 through an opening 185 provided in the fifth interlayer film 159. The sixth wiring layer 160 includes an eleventh conductive layer 161, a twelfth conductive layer 162, and a thirteenth conductive layer 163. As the eleventh conductive layer 161, it is preferable to use a material having low electrical resistance and good adhesion to the tenth conductive layer 152. For example, the same material as the tenth conductive layer 152 may be used, and Cu, Ag, Au, Al, Al—Nd, Al—Cu, or the like can be used.

  The thirteenth conductive layer 163 is preferably made of a material that has high corrosion resistance, is not easily oxidized, and has low contact resistance with an external element. For example, Au, platinum (Pt), etc. can be used. The twelfth conductive layer 162 is preferably made of a material having good adhesion to the eleventh conductive layer 161 and the thirteenth conductive layer 163. For example, when the 13th conductive layer 163 is formed by plating, it is preferable to use a material suitable as a seed layer for the 13th conductive layer 163. For example, Ti, nickel (Ni), TiN, Cr, etc. can be used.

  An insulating intermediate layer 101 is formed between the multilayer wiring structure and the substrate. The intermediate layer 101 is preferably softer than the substrate 100, that is, has a smaller Young's modulus, in order to reduce the stress caused by the multilayer wiring structure from being transmitted to the substrate. In addition, the intermediate layer 101 is more easily expanded and contracted than the substrate 100 in order to mitigate the thermal expansion of the substrate being transmitted to the multilayer wiring structure, and from the first conductive layer 111 and the second conductive layer 112 of the first wiring layer 110. It is desirable that it is difficult to expand and contract. That is, it is desirable that the thermal expansion coefficient is higher than that of the substrate 100 and lower than that of the first wiring layer. Here, when the film thickness of the second conductive layer 112 is, for example, five times or more thicker than the film thickness of the first conductive layer 111, the stress caused by the thermal expansion coefficient is dominated by the stress caused by the second conductive layer 112. Therefore, the thermal expansion coefficient of the intermediate layer 101 only needs to be lower than the thermal expansion coefficient of the second conductive layer 112. The intermediate layer 101 preferably includes a resin material. The intermediate layer 101 is preferably made of a material having a barrier property with respect to the second conductive layer 112. In other words, the intermediate layer 101 is preferably a material whose diffusion rate of the second conductive layer 112 is slower than that of the substrate 100. For example, when the second conductive layer 112 includes Cu, a resin material such as polyimide can be used for the intermediate layer 101. FIG. 1 illustrates a structure in which one intermediate layer is sandwiched between the multilayer wiring structure and the substrate. However, the present invention is not limited to this structure, and the intermediate layer and the multilayer wiring structure or the intermediate layer and the substrate Another layer may be sandwiched between them.

  Here, in FIG. 1, a plurality of vias overlap each other in plan view in order to provide a multilayer wiring structure having a high degree of design freedom and to provide a multilayer wiring structure having a small occupied area in the planar direction. A stacked via structure is disclosed. The degree of expansion and contraction due to the heat treatment step in the process differs between the organic insulating layer and the wiring layer, or between the organic insulating layer and the substrate. Therefore, in the stacked via structure, the region AB line in which the wiring layer and the via are overlapped and the region CD line in which the organic insulating layer is formed between the wiring layers are generated in the degree of expansion and contraction due to the heat treatment process. The stress to be done varies greatly.

  In particular, in the region AB line in which the wiring layer that is harder than the organic insulating layer, that is, the Young's modulus is stacked, is D2 (three-dimensional) compared to the region CD line in which the organic insulating layer is disposed between the wiring layers. A large stress is generated in the direction. In addition, stress in the D1 (planar) direction due to the degree of expansion and contraction due to the heat treatment process is also generated between the organic insulating layer and the substrate over the entire surface of the substrate.

  When a stacked via structure is formed without providing an intermediate layer on the substrate as in the prior art, cracks in the via or inorganic insulating layer are generated due to the stress in the D1 direction or D2 direction, and the via and wiring are not connected. Problems such as peeling occur. However, according to the structure shown in FIG. 1, at least in the region where the intermediate layer 101 is provided between the first wiring layer 110 and the substrate 100, the stress in the direction D1 or D2 can be relieved. It is possible to suppress problems such as cracks in vias and inorganic insulating layers and peeling of vias and wiring.

  Further, in a structure in which a multilayer wiring structure is formed without providing an intermediate layer on the substrate as in the prior art, particularly when the second conductive layer 112 of the first wiring layer 110 contains Cu, the first conductive layer 111 and the first conductive layer Even when a material having a barrier property against Cu is used as the first inorganic insulating layer 113, Cu may diffuse to the substrate through cracks generated in the first inorganic insulating layer 113 by the heat treatment process. For example, when a conductive or semiconductor material is used for the substrate 100, there is a problem that the first wiring layer 110 and the substrate 100 are short-circuited. When such a problem occurs, at least the first wiring layer 110 cannot be used as a signal line, and the degree of freedom in design is limited.

  As described above, by providing the insulating intermediate layer having the above characteristics between the substrate and the multilayer wiring structure, the stress in the three-dimensional direction generated in the region where the wiring layer and the via are overlapped by the heat treatment process is relieved. be able to. Further, by providing the intermediate layer, it is possible to relieve the stress in the planar direction generated over the entire surface of the substrate by the heat treatment process. As a result, problems such as generation of cracks in vias and inorganic insulating layers and peeling of vias and wiring can be suppressed.

  Further, by providing an insulating intermediate layer having the above characteristics between the substrate and the multilayer wiring structure, it is possible to suppress the diffusion of Cu to the substrate by the heat treatment process. As a result, it is possible to suppress a problem that the first wiring layer and the substrate are short-circuited, so that the first wiring layer 110 can be used for the signal line 800, and wiring with matching characteristic impedance can be arranged. . Further, by connecting the ground line 900 to the conductive substrate 100, more stable ground characteristics can be obtained.

  Therefore, according to the first embodiment, an example of which is shown in FIG. 1, it is possible to provide a multilayer wiring structure having an improved design freedom in the multilayer wiring structure. In addition, it is possible to provide a multilayer wiring structure having high resistance to the heat treatment process. In addition, since a multilayer wiring structure having a stacked via structure can be obtained, a multilayer wiring structure having a small occupied area in the plane direction can be provided. In addition, by using a material having a dielectric constant lower than that of the inorganic insulating layer as the organic insulating layer, the parasitic capacitance between the stacked wirings can be reduced, so that delay of signals transmitted through the wirings is suppressed. A multilayer wiring structure that can be provided can be provided. Further, in all the wiring layers, wirings having matched characteristic impedance can be arranged, and a multilayer wiring structure capable of high-speed transmission can be provided.

[Manufacturing method of multilayer wiring structure]
Next, a method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 19, the same elements as those shown in FIG.

  FIG. 2 is a cross-sectional view of a substrate on which a first conductive material and a lower second conductive material are formed in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. As shown in FIG. 2, an insulating intermediate layer 101 using a resin material such as polyimide is formed on a substrate 100 such as a silicon substrate using a coating method. Next, after exposure using a photomask, development is performed to form an opening 180 as shown in FIG.

  Next, as shown in FIG. 3, a first conductive material 211 is formed on the intermediate layer 101 and inside the opening 180 by sputtering, and a lower second conductive material 212 is formed thereon, A part of the conduction part 190 is formed. As the lower second conductive material 212, it is preferable to use Cu having a low resistance. In this case, it is preferable to use Ti having a barrier property against Cu as the first conductive material 211. The intermediate layer 101 and the first conductive material 211 serve as a barrier layer for suppressing Cu from diffusing into the substrate 100 and short-circuiting between the first conductive material 211 and the substrate 100. The lower second conductive material 212 serves as a seed layer for growing Cu by an electrolytic plating method. Here, as the material of the barrier layer other than Ti, TiN or refractory metal Ta, TaN, Cr, or the like can be used.

  Next, as shown in FIG. 4, after applying a photoresist on the lower second conductive material 212, a resist pattern 310 for wiring formation is formed by performing exposure and development. Thereafter, the same material as the lower second conductive material 212 is grown on the lower second conductive material 212 exposed from the resist pattern 310 for wiring formation using an electrolytic plating method. Two conductive materials 213 are formed. Through these steps, the conductive portion 190 is filled in the opening 180. In FIG. 5, a manufacturing method in which the same material as the lower second conductive material 212 is grown as the upper second conductive material 213 is illustrated, but the upper second conductive material 213 is not limited to this method. A material different from 212 may be grown.

  Next, after the upper second conductive material 213 is formed, the photoresist for forming the wiring formation resist pattern 310 is removed with an organic solvent to obtain the structure of FIG. Note that ashing by oxygen plasma can be used for removing the photoresist instead of using an organic solvent.

  Next, as shown in FIG. 7, a part of the lower second conductive material 212 and a part of the first conductive material 211 covered with the wiring formation resist pattern 310 are etched with an acidic chemical solution, and the first A conductive layer 111 and a second conductive layer 112 are formed. Since the thickness of the upper second conductive material 213 is reduced by this etching, it is preferable to set the thickness of the upper second conductive material 213 in consideration of the influence of this thinning. Further, ion milling, dry etching, or the like can be used instead of the etching using the above chemical solution.

  When the acidic aqueous solution is used, if the etching rate of the first conductive layer 111 is higher than that of the second conductive layer 112, an undercut 301 is formed as shown in FIG. In particular, when the wiring width is 5 μm or less, sufficient adhesion between the first conductive layer 111 and the underlying intermediate layer 101 cannot be obtained, and the first conductive layer 111 is peeled off due to its own stress. Sometimes. On the other hand, when ion milling or dry etching is used, such an undercut is unlikely to occur, so that fine wiring can be formed.

Next, as shown in FIG. 8, a first inorganic insulating layer 113 such as a SiN film and a second inorganic insulating layer 114 such as a SiO ₂ film are formed on the second conductive layer 112 by plasma CVD. To do. In forming the SiN film, SiH ₄ can be used as a Si source, and NH ₃ can be used as a nitrogen source. In forming the SiO ₂ film, SiH ₄ can be used as a Si source and N ₂ O can be used as an oxygen source. Further, tetraethoxysilane (TEOS) can be used as the Si source. Further, as the oxygen source, it is also possible to use a O _2.

The SiO ₂ film is preferably adjusted to a compressive stress of −300 MPa or more and −100 MPa or less in terms of suppressing warpage of the substrate 100. In particular, the film stress is preferably adjusted to -200 MPa or more and -150 MPa or less.

When the second conductive layer 112 includes Cu, if copper oxide is present on the surface of Cu, the adhesion between the first inorganic insulating layer 113 and Cu is reduced. Therefore, before the first inorganic insulating layer 113 is formed, It is preferable to clean the Cu surface with dilute sulfuric acid or the like. In addition, before the first inorganic insulating layer 113 is formed, the Cu oxide can be removed by exposing the Cu surface to NH ₃ plasma in the same chamber.

  Further, when the second conductive layer 112 contains Cu, it is preferable to use a SiN film having a barrier property against Cu as the first inorganic insulating layer 113, and Cu atoms, Cu molecules, Cu ions of the second conductive layer 112 are used. Serves as a barrier insulating layer that prevents thermal diffusion from the side surface and upper surface of the second conductive layer 112 to the second inorganic insulating layer 114, and further prevents diffusion due to an electric field between adjacent wiring layers. Here, instead of using the SiN film as the barrier insulating layer, a SiC film (which may contain several to 10% oxygen) can be used. The SiC film can also be formed by plasma CVD, and has an effect of preventing diffusion of Cu atoms, Cu molecules, and Cu ions in the second conductive layer 112.

Further, as the second inorganic insulating layer 114, a SiOC film, a SiOF film, or the like may be used instead of the SiO ₂ film. The SiOC film and the SiOF film can also be formed by plasma CVD. The SiOC film and the SiOF film have a lower dielectric constant than the SiO ₂ film, and can reduce the parasitic capacitance between the stacked wirings.

  Next, a first organic insulating layer 115 such as polyimide is applied on the second inorganic insulating layer 114 by spin coating. Instead of polyimide, benzocyclobutene may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyether ether ketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyetherimide, etc. Can be used. The above resins may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  However, when a non-photosensitive resin is used, it is necessary to apply a photosensitive resin and perform patterning by lithography. For this reason, when non-photosensitive resin is used, a process may increase. In the first embodiment, a manufacturing method using photosensitive polyimide as the first organic insulating layer 115 will be described.

  When the first organic insulating layer 115 is applied, exposure is performed using a photomask and development is performed to form a recess 281 at a required position above the second conductive layer 112 as shown in FIG. . Here, the “necessary position” refers to a position where a via that connects the second conductive layer 112 to a wiring formed in an upper layer is necessary.

  In order to cure the first organic insulating layer 115 applied after the formation of the recess 281, a thermosetting process is performed. The thermosetting treatment is preferably set to be equal to or lower than the glass transition temperature of the organic insulating layer to be used. This is because if the curing is performed at a temperature exceeding the glass transition temperature, the shape of the concave portion 281 is deformed, and problems such as an opening diameter larger than the design size occur. For example, when polyimide is used as the first organic insulating layer 115, if the glass transition temperature of polyimide is 280 ° C., it is preferable to perform heat treatment at 250 ° C., for example, heat treatment at 250 ° C. for 1 hour in a nitrogen atmosphere. It is good to do. In addition, it is preferable to perform not only the thermosetting process but the heat processing after this process so that the glass transition temperature of a polyimide may not be exceeded.

  Note that when the first organic insulating layer 115 is thermally cured, a step 302 as shown in FIG. 21 may occur in a region other than the recess 281 due to the step caused by the first wiring layer 110. Such a step becomes larger as the wiring layers are stacked, and a focus shift occurs during pattern exposure. For this reason, it becomes difficult to form a wiring pattern based on the design dimensions, and there arises a problem that adjacent wirings are short-circuited, and conversely, a problem that the wiring is disconnected. In order to reduce the step 302 of the first organic insulating layer 115, it is preferable to use an organic material such as polyimide having a low thermal shrinkage rate (preferably, a thermal shrinkage rate of 15% or less). In addition, a fly cutter can be used to remove unevenness on the surface of polyimide with high accuracy.

Next, the first inorganic insulating layer 113 and the second inorganic insulating layer 114 at the bottom of the recess 281 are etched by plasma etching using the first organic insulating layer 115 as a mask. Here, an etching method in the case where a SiN film is used as the first inorganic insulating layer 113, a SiO ₂ film is used as the second inorganic insulating layer 114, and polyimide is used as the first organic insulating layer 115 will be described in detail.

As an etching gas for the SiO ₂ film, a mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) can be used. By changing the flow ratio of the mixed gas, it is possible to adjust the ratio of the etching rate of the cured polyimide and the SiO ₂ film. Here, it is preferable to adjust so that the ratio of the etching rate of polyimide with respect to the SiO ₂ film becomes small. Note that the etching gas is not limited to that described above, and CHF ₃ or CH ₂ F ₂ can be used instead of CF ₄ .

As an etching gas for the SiN film, a mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) can be used. Also in the etching of the SiN film, the ratio of the etching rate of the cured polyimide and the SiN film can be adjusted by changing the flow ratio of the mixed gas. Similar to SiO ₂ , it is preferable to adjust so that the ratio of the etching rate of polyimide to the SiN film becomes small.

  As described above, the opening for filling the first via 191 that electrically connects the first wiring layer 110 and the second wiring layer 120 by etching the first inorganic insulating layer 113 and the second inorganic insulating layer 114. A portion 181 is formed. Immediately after the opening 181 is formed, a carbon compound containing Si or F may adhere to the side wall or bottom of the opening 181. In order to remove this carbon compound, you may wash | clean with an organic solvent. Further, the surface of the second conductive layer 112 exposed at the bottom of the opening 181 may be oxidized by plasma etching. In order to remove the oxide on the surface, washing with dilute sulfuric acid may be performed.

  Due to plasma etching on the first inorganic insulating layer 113 and the second inorganic insulating layer 114, the surface of the first organic insulating layer 115 may be damaged by plasma, and the heat resistance inherent to the first organic insulating layer 115 may be impaired. . In this case, for example, the damaged layer on the surface can be removed by performing a heat treatment at a temperature equal to or lower than the glass transition temperature of the first organic insulating layer 115. In this way, the structure shown in FIG. 10 can be obtained.

  Next, as shown in FIG. 11, a third conductive material 221 is formed by sputtering. In the case where the second conductive layer 112 contains Cu, the third conductive material 221 uses Ti, TiN, Ta, TaN, Cr, etc. as in the first conductive layer 111, so that Cu atoms, Cu molecules, Cu It can function as a barrier metal that prevents ions from diffusing.

  Next, as shown in FIG. 12, a lower fourth conductive material 222 is formed by sputtering. As the lower fourth conductive material 222, it is preferable to use Cu having low resistance. The lower fourth conductive material 222 serves as a seed layer for growing Cu by an electrolytic plating method.

  Next, as shown in FIG. 13, after applying a photoresist on the lower fourth conductive material 222, a resist pattern 320 for wiring formation is formed by performing exposure and development. Thereafter, the same material as that of the lower fourth conductive material 222 is grown on the lower fourth conductive material 222 exposed from the wiring formation resist pattern 320 by using an electrolytic plating method. Four conductive material 223 is formed. In FIG. 14, a manufacturing method in which the same material as the lower fourth conductive material 222 is grown as the upper fourth conductive material 223 is illustrated, but the present invention is not limited to this method, and the upper fourth conductive material 223 is replaced with the lower fourth conductive material. A material different from 222 may be grown.

  Next, after the upper fourth conductive material 223 is formed, the photoresist for forming the wiring forming resist pattern 320 is removed with an organic solvent to obtain the structure of FIG. Note that ashing by oxygen plasma can be used for removing the photoresist instead of using an organic solvent.

  Next, as shown in FIG. 16, a part of the lower fourth conductive material 222 and a part of the third conductive material 221 covered with the wiring formation resist pattern 320 are etched with an acidic chemical solution. A conductive layer 121 and a fourth conductive layer 122 are formed. Since the thickness of the upper fourth conductive material 223 is reduced by this etching, it is preferable to set the thickness of the upper fourth conductive material 223 in consideration of the influence of this thinning. Further, ion milling, dry etching, or the like can be used instead of the etching using the above chemical solution.

Next, as shown in FIG. 17, a third inorganic insulating layer 123 and a fourth inorganic insulating layer 124 are formed on the fourth conductive layer 122. For example, when the fourth conductive layer 122 contains Cu, it is preferable to use a SiN film having a barrier property against Cu as the third inorganic insulating layer 123 as the third inorganic insulating layer 123. As the layer 124, it is preferable to use a SiO ₂ film similarly to the second inorganic insulating layer 114. Instead of using the SiN film as the barrier insulating layer as the third inorganic insulating layer 123, a SiC film (which may contain several to 10% oxygen) can be used. Further, as the fourth inorganic insulating layer 124, a SiOC film, a SiOF film, or the like may be used instead of the SiO ₂ film.

  Next, a second organic insulating layer 125 such as polyimide is applied on the fourth inorganic insulating layer 124 by spin coating. Instead of polyimide, benzocyclobutene may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  Non-photosensitive resins include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyether ether ketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyetherimide, etc. Can be used. The above resins may be used alone or in combination of two or more kinds of resins. Further, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  In the first embodiment, a manufacturing method using photosensitive polyimide as the second organic insulating layer 125 will be described.

  When the second organic insulating layer 125 is applied, development is performed after exposure using a photomask, and a recess 282 is formed at a necessary position above the fourth conductive layer 122 as shown in FIG. . Here, the “necessary position” refers to a position where a via that connects the fourth conductive layer 122 to a wiring formed in an upper layer is necessary.

  After the recess 281 is formed, a thermosetting process is performed at a temperature equal to or lower than the glass transition temperature of the second organic insulating layer 125 in order to cure the second organic insulating layer 125. For example, when polyimide is used as the second organic insulating layer 125, if the glass transition temperature of polyimide is 280 ° C., the temperature is set to 250 ° C. as described above. In addition, it is preferable to perform not only the thermosetting process but the heat processing after this process so that the glass transition temperature of a polyimide may not be exceeded.

  Next, the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124 at the bottom of the recess 282 are etched by plasma etching using the second organic insulating layer 125 as a mask. As the plasma etching method, a method similar to the etching method of the first inorganic insulating layer 113 and the second inorganic insulating layer 114 can be used. By etching the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124, an opening 182 for filling the second via 192 that electrically connects the second wiring layer 120 and the third wiring layer 130 is formed. The In this way, the structure shown in FIG. 19 can be obtained.

  Thereafter, the multilayer wiring structure shown in FIG. 1 can be obtained by repeating the method described with reference to FIGS.

Second Embodiment
Hereinafter, a multilayer wiring structure according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 22 is a cross-sectional view of the multilayer wiring structure according to the second embodiment of the present invention. FIG. 22 is similar to FIG. 1 in that a multilayer wiring structure is formed on one surface of the substrate 100, but is different in that it has a back surface insulating layer 102 patterned on the other surface of the substrate 100. Different from 1.

  The back insulating layer 102 has an opening 103 at the same plane coordinates as the opening 180 formed in the intermediate layer 101 in plan view. In other words, the opening 180 or the conduction portion 190 formed in the intermediate layer 101 and the opening 103 formed in the back surface insulating layer 102 overlap each other in plan view. The back insulating layer 102 may be made of the same material as that of the intermediate layer 101. For example, a resin material such as polyimide can be used. Further, the planar shape of the back surface insulating layer 102 may be the same shape as the opening 180 (for example, a dot shape).

  According to the above structure, the distortion of the substrate due to the stress generated in the multilayer wiring structure and the intermediate layer 101 by the heat treatment process can be reduced. Furthermore, the opening 103 is arranged so that the back insulating layer 102 overlaps the opening 180 in plan view, so that the stress generated by the intermediate layer 101 can be more effectively reduced. As a result, it is possible to provide a multilayer wiring structure in which substrate distortion is suppressed. Further, the substrate 100 can be connected to an external grounding member through the opening 103 formed in the back surface insulating layer 102, and more stable ground characteristics can be obtained.

<Third Embodiment>
Hereinafter, a multilayer wiring structure according to a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 23 is a cross-sectional view of the multilayer wiring structure according to the third embodiment of the present invention. FIG. 23 is similar to FIG. 1 except that the opening 180 and the conductive portion 190 formed in the intermediate layer 101 are arranged at different plane coordinates from the plurality of vias formed in the upper layer. Different from 1. In other words, the conduction part 190 and the first to fourth vias (191, 192, 193, 194) are arranged at different positions in plan view. In other words, at least the conductive portion 190 and the first via 191 are arranged at different positions in plan view. In other words, the conduction part 190 and the first via 191 have a crank structure.

  According to the above structure, even in the stacked via structure of the ground line 900, the stress in the three-dimensional direction generated by the heat treatment process can be relieved by the intermediate layer 101. As a result, even in the vicinity of the ground line 900, problems such as the occurrence of cracks in the via and the inorganic insulating layer and the separation of the via and the wiring can be suppressed.

<Fourth embodiment>
Hereinafter, a multilayer wiring structure according to a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 24 is a cross-sectional view of a multilayer wiring structure according to the fourth embodiment of the present invention. FIG. 24 is similar to FIG. 23 in that a multilayer wiring structure is formed on one surface of the substrate 100, but is different in that it has a back insulating layer 102 patterned on the other surface of the substrate 100. 23.

  The back insulating layer 102 has an opening 103 at the same plane coordinate as the opening 180 formed in the stacked vias and the intermediate layer 101 in plan view. In other words, the plurality of vias and openings 180 and the openings 103 formed in the back insulating layer 102 overlap each other in plan view. The back insulating layer 102 may be made of the same material as that of the intermediate layer 101. For example, a resin material such as polyimide can be used. Further, the planar shape of the back surface insulating layer 102 may be the same shape (for example, dot shape) as the opening 180 of the intermediate layer 101 and the openings 181 to 184 of the multilayer wiring structure.

  FIG. 25 is a cross-sectional view of a multilayer wiring structure according to a modification of the fourth embodiment of the present invention. FIG. 25 differs from FIG. 24 in that the stacked vias are arranged at different plane coordinates. In other words, in FIG. 25, a plurality of stacked vias are arranged at different positions in plan view. In other words, the plurality of stacked vias have a crank structure. 25 illustrates a structure in which the back surface insulating layer 102 is provided with the opening 103 so as to overlap with the plurality of vias and the opening 180 in a plan view. However, the structure is not limited to this structure. It is only necessary to have an opening that can be electrically connected to the substrate 100.

  According to the above structure, the distortion of the substrate due to the stress generated in the multilayer wiring structure and the intermediate layer 101 by the heat treatment process can be reduced. Further, the opening 103 is arranged in the back insulating layer 102 so as to overlap with the opening 180 of the intermediate layer 101 and the openings 181 to 184 of the multilayer wiring structure in a plan view, so that the back insulating layer 102 becomes the intermediate layer 101. In addition, the stress generated by the plurality of interlayer films (119, 129, 139, 149, 159) of the multilayer wiring structure can be more effectively reduced. As a result, it is possible to provide a multilayer wiring structure in which substrate distortion is suppressed. Further, the substrate 100 can be connected to an external grounding member through the opening 103 formed in the back surface insulating layer 102, and more stable ground characteristics can be obtained.

<Fifth Embodiment>
Hereinafter, a multilayer wiring structure according to a fifth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 26 is a cross-sectional view of the multilayer wiring structure according to the fifth embodiment of the present invention. FIG. 26 is similar to FIG. 1, but differs from FIG. 1 in that a ground auxiliary layer 104 is provided between the substrate 100 and the intermediate layer 101. The ground auxiliary layer 104 is preferably made of a material having a lower specific resistance than that of the conductive substrate 100 and a lower contact resistance with the conductive portion 190. That is, the ground auxiliary layer 104 is preferably a metal layer.

  According to the above structure, the contact resistance between the conductive portion 190 and the substrate 100 can be further reduced. Further, when a plurality of ground lines are connected to the substrate 100 via the plurality of conductive portions 190, the plurality of ground lines can be connected with low resistance. Therefore, more stable ground characteristics can be obtained.

  Hereinafter, the present invention will be specifically described based on Example 1 shown in FIG. 27, but the present invention is not limited to only these examples. FIG. 27 is a cross-sectional view of the multilayer wiring structure according to Embodiment 1 of the present invention. In Example 1, an example in which an eight-layer wiring structure is manufactured by adding two more wiring layers to the multilayer wiring structure of the first embodiment will be described.

  First, a 400 μm thick silicon substrate was prepared as the substrate 100. Next, a 10 μm photosensitive polyimide is applied as an insulating intermediate layer 101 on the substrate 100 by a spin coating method, exposed using a photomask, developed, and an intermediate having an opening 180 having a diameter of 20 μm. Layer 101 is formed. The Young's modulus of polyimide is 3 to 3.5 GPa, and the Young's modulus of the silicon substrate is about 185 GPa. That is, the intermediate layer 101 has a Young's modulus lower than that of the substrate 100. In other words, the intermediate layer 101 is softer than the substrate 100. In addition, polyimide has a barrier property against Cu used in a wiring layer described later. That is, polyimide has a slower Cu diffusion rate than a silicon substrate.

  On the intermediate layer 101 and inside the opening 180, the first wiring layer 110 and the conductive portion 190 are formed in the same process. The first wiring layer 110 and the conductive portion 190 are formed by stacking Ti having a thickness of 50 nm as the first conductive layer 111 and Cu having a thickness of 4 μm as the second conductive layer 112. Here, Ti of the first conductive layer 111 has a barrier property against Cu of the second conductive layer 112. The inside of the opening 180 is covered with Ti of the first conductive layer, and is formed so as to isolate Cu of the second conductive layer and the inside of the opening 180 of the intermediate layer 101. The wiring pattern of the first wiring layer 110 can be formed with a line width of 10 to 100 μm.

  In Example 1 shown in FIG. 27, the second to seventh wiring layers (120, 130, 140, 150, 160, 170) are also formed with the same laminated structure and pattern line width as the first wiring layer 110. That is, the third, fifth, seventh, ninth, eleventh, and thirteenth conductive layers (121, 131, 141, 151, 161, and 171) are formed of the same Ti as the first conductive layer 111, and the fourth, sixth, eighth, and tenth layers are formed. , 12, 14 conductive layers (122, 132, 142, 152, 162, 172) are formed of the same Cu as the second conductive layer 112.

When the first wiring layer 110 is formed on the intermediate layer 101, a first interlayer film 119 is formed so as to cover them. The first interlayer film 119 includes a 10 nm thick SiN film as the first inorganic insulating layer 113, a 2 μm thick SiO ₂ film as the second inorganic insulating layer 114, and a 12 μm thick polyimide as the first organic insulating layer 115. And is formed by lamination. Here, the SiN film of the first inorganic insulating layer 113 and the SiO ₂ film of the second inorganic insulating layer 114 are formed using a plasma CVD method. Further, the polyimide of the first organic insulating layer 115 relaxes or flattens the step formed by the first wiring layer 110. That is, the polyimide film thickness 115b of the first organic insulating layer 115 on the first wiring layer 110 is compared with the polyimide film thickness 115a of the first organic insulating layer 115 on the intermediate layer 101 where the first wiring layer 110 does not exist. It will be formed thin. In Example 1 shown in FIG. 27, the film thickness 115a was 12 μm, and the film thickness 115b was about 8 μm, which was approximately the thickness of the first wiring layer 110.

Subsequently, an opening 181 is formed in the first interlayer film 119. The opening 181 has a diameter of 15 μm. In the opening 181, first, photosensitive polyimide is applied as the first organic insulating layer 115, exposure is performed using a photomask, development is performed, and the lower second inorganic insulating layer 114 is provided at a position where the opening 181 is provided. Forming a recess that exposes. Using the photosensitive polyimide of the first organic insulating layer 115 as a mask, the second inorganic insulating layer 114 exposed in the recess and the first inorganic insulating layer 113 underneath were formed by plasma etching. For etching the SiO ₂ film of the second inorganic insulating layer 114, a mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) was used. Further, a mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) was used for etching the SiN film of the first inorganic insulating layer 113.

  Subsequently, the second wiring layer 120 and the first via 191 are formed in the same process on the first interlayer film 119 and inside the opening 181. Similar to the first wiring layer 110, the second wiring layer 120 and the first via 191 are formed by stacking Ti having a thickness of 50 nm as the third conductive layer 121 and Cu having a thickness of 4 μm as the fourth conductive layer 122. Form. Here, Ti of the third conductive layer 121 has a barrier property against Cu of the fourth conductive layer 122. The inside of the opening 181 is covered with Ti of the third conductive layer 121 and is formed so as to isolate Cu of the fourth conductive layer 122 and the inside of the opening 181 of the first interlayer film 119.

  The diameter 191 a of the first via 191 is 15 μm, which is the same as the diameter of the opening 181, and the diameter 191 b of the land located above the first via 191 is 30 μm. The via pitch indicating the distance between the centers of adjacent vias is 40 μm at the smallest pitch.

  As described above, the first wiring layer, the first interlayer film, and the first via are formed. Similarly to these, second to seventh wiring layers, interlayer films, and second to sixth vias are formed. Then, the uppermost eighth wiring layer 380 and the seventh via 197 are formed in the same process on the seventh interlayer film 179 and inside the opening 187 provided in the seventh interlayer film 179. The eighth wiring layer 380 is formed by stacking Cu having a thickness of 3 μm as the fifteenth conductive layer 381, Ni having a thickness of 1 μm as the sixteenth conductive layer 382, and Au having a thickness of 1 μm as the seventeenth conductive layer 383. Is done.

  As described above, according to the first embodiment, by providing the insulating intermediate layer having the above characteristics between the substrate and the multilayer wiring structure, Cu is prevented from diffusing to the substrate by the heat treatment process. be able to. As a result, it is possible to suppress a problem that the first wiring layer and the substrate are short-circuited, so that the first wiring layer 110 can be used for the signal line 800, and wiring with matching characteristic impedance can be arranged. . Further, by connecting the ground line 900 to the conductive substrate 100, more stable ground characteristics can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention.

100: substrate 101: intermediate layer 102: back surface insulating layer 103: opening 104: ground auxiliary layer 110: first wiring layer 111: first conductive layer 112: second conductive layer 113: first inorganic insulating layer 114: second Inorganic insulating layer 115: first organic insulating layer 119: first interlayer films 120, 126, 127: second wiring layer 121: third conductive layer 122: fourth conductive layer 123: third inorganic insulating layer 124: fourth inorganic Insulating layer 125: second organic insulating layer 129: second interlayer film 130: third wiring layer 131: fifth conductive layer 132: sixth conductive layer 133: fifth inorganic insulating layer 134: sixth inorganic insulating layer 135: first 3 organic insulating layer 139: third interlayer film 140: fourth wiring layer 141: seventh conductive layer 142: eighth conductive layer 143: seventh inorganic insulating layer 144: eighth inorganic insulating layer 145: fourth organic insulating layer 149 : Fourth interlayer film 150: Fifth wiring layer 51: ninth conductive layer 152: tenth conductive layer 153: ninth inorganic insulating layer 154: tenth inorganic insulating layer 155: fifth organic insulating layer 159: fifth interlayer film 160: sixth wiring layer 161: eleventh conductive Layer 162: Twelfth conductive layer 163: Thirteenth conductive layer 180, 181, 182, 185: Opening 190: Conducting portion 191: First via 192: Second via 193: Third via 194: Fourth via 211: First 1 conductive material 212: lower second conductive material 213: upper second conductive material 221: third conductive material 222: lower fourth conductive material 223: upper fourth conductive material 281 and 282: concave portion 301: undercut 302: step 310 320: wiring pattern resist pattern 800: signal line 900: ground line

Claims (12)

A conductive layer ;
A multilayer wiring structure in which a plurality of wiring layers are laminated on one surface of the conductive layer, and
The multilayer wiring structure includes a plurality of vias connecting adjacent wiring layers,
At least one wiring layer of the plurality of wiring layers includes a signal line and a ground line,
An insulating intermediate layer having a first opening is provided directly on one surface of the conductive layer between the multilayer wiring structure and the conductive layer, and the first opening has the A conductive layer connecting the conductive layer and the ground line is provided ;
An insulating layer is directly provided on the other surface of the conductive layer;
The insulating layer has a second opening provided so that the other surface of the conductive layer is exposed.
The multilayer wiring structure, wherein the second opening is provided so as to overlap with a position where the plurality of vias are provided .   The multilayer wiring structure according to claim 1, wherein the intermediate layer is a resin material. Multilayer wiring structure according to claim 1 or 2, wherein the insulating layer is a resin material. Wherein A conductive portion and the second opening, the multilayer wiring structure according to any one of claims 1 to 3, characterized in that superimposed with each other in plan view. The multilayer wiring structure according to claim 4 , wherein the plurality of vias and the second opening overlap each other in plan view. A conductive layer ;
A multilayer wiring structure in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially laminated from one side of the conductive layer on one surface of the conductive layer ;
The multilayer interconnection structure includes a first via that connects the second wiring layer and the first wiring layer, a second via that connects the third wiring layer and the second wiring layer, and
The first wiring layer includes a signal line and a ground line,
Between the layer having the conductivity and the multilayer interconnection structure has a first opening, one of the layers of the conductive Young's modulus than the layer having a low insulating property of the intermediate layer has the conductive Is provided directly on the surface, and the first opening is provided with a conductive portion for connecting the conductive layer and the ground line ,
An insulating layer is directly provided on the other surface of the conductive layer;
The insulating layer has a second opening provided so that the other surface of the conductive layer is exposed;
The multilayer wiring structure, wherein the second opening is provided so as to overlap with a position where the first via is provided . A conductive layer ;
A multilayer wiring structure in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially laminated from one side of the conductive layer on one surface of the conductive layer ;
The multilayer interconnection structure includes a first via that connects the second wiring layer and the first wiring layer, a second via that connects the third wiring layer and the second wiring layer, and
The first wiring layer includes a signal line and a ground line,
Wherein between the layer having a multilayer wiring structure of the conductive, has a first opening, the intermediate layer of the thermal expansion coefficient higher insulating properties than a layer having the conductive layer having the conductive Directly provided on one surface, the conductive portion connecting the conductive layer and the ground line is provided in the first opening ,
An insulating layer is directly provided on the other surface of the conductive layer;
The insulating layer has a second opening provided so that the other surface of the conductive layer is exposed;
The multilayer wiring structure, wherein the second opening is provided so as to overlap with a position where the first via is provided . The multilayer wiring structure according to claim 6, wherein the first via and the conductive portion are arranged at different positions in a plan view. The multilayer wiring structure according to claim 8 , wherein the intermediate layer is a resin material. The multilayer wiring structure according to claim 6, wherein the insulating layer is a resin material. The multilayer wiring structure according to claim 10 , wherein the conductive portion and the second opening overlap each other in plan view. The multilayer wiring structure according to claim 11 , wherein the first via, the second via, and the second opening overlap each other in a plan view.

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