JP2000311982A - Semiconductor device, semiconductor module and method of manufacturing them - Google Patents
Semiconductor device, semiconductor module and method of manufacturing themInfo
- Publication number
- JP2000311982A JP2000311982A JP11118294A JP11829499A JP2000311982A JP 2000311982 A JP2000311982 A JP 2000311982A JP 11118294 A JP11118294 A JP 11118294A JP 11829499 A JP11829499 A JP 11829499A JP 2000311982 A JP2000311982 A JP 2000311982A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- semiconductor
- semiconductor element
- layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置と半導
体モジュールおよびそれらの製造方法に係わり、特に、
小型化と低コスト化が要求されるメモリー装置およびメ
モリーモジュールに適用される半導体装置と半導体モジ
ュール、およびそれらの装置またはモジュールを製造す
る方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a semiconductor module, and a method of manufacturing the same,
The present invention relates to a semiconductor device and a semiconductor module which are applied to a memory device and a memory module which are required to be reduced in size and cost, and to a method of manufacturing the device or the module.
【0002】[0002]
【従来の技術】従来から、複数の半導体素子を集積した
半導体モジュールとしては、図8に示すように、SOP
(Small Outline Package)のような、2方向にリード
を有する半導体パッケージ21の複数個を、1枚の実装
基板(例えば、プリント配線板)22の上に並べて搭載
し、接続した構造のものが知られている。2. Description of the Related Art Conventionally, as a semiconductor module in which a plurality of semiconductor elements are integrated, as shown in FIG.
It is known that a plurality of semiconductor packages 21 having leads in two directions, such as a (Small Outline Package), are mounted side by side on a single mounting board (for example, a printed wiring board) 22 and connected. Have been.
【0003】また、半導体素子を縦方向に積層した積層
モジュールとしては、図9に示すように、複数のTCP
(Tape Carrier Package)23を垂直方向に重ねて配置
し、各TCP23のアウターリード24を、プリント配
線板のような実装基板22の接続パッド25に一括して
接続した構造、あるいは図10に示すように、複数のS
ON(Small Outline Non-leaded Package)またはQF
N(Quad Flat Non-leaded Package)26を、垂直方向
に積み重ねて実装基板22に搭載し、各パッケージのア
ウターリード24を順に接続するとともに、最下段のパ
ッケージのアウターリード24を、実装基板22の接続
パッド25に接続した構造のものが開発されている。As a stacked module in which semiconductor elements are stacked in a vertical direction, as shown in FIG.
(Tape Carrier Package) 23 is vertically stacked, and the outer leads 24 of each TCP 23 are collectively connected to connection pads 25 of a mounting board 22 such as a printed wiring board, or as shown in FIG. And several S
ON (Small Outline Non-leaded Package) or QF
N (Quad Flat Non-leaded Package) 26 is vertically stacked and mounted on the mounting substrate 22, and the outer leads 24 of each package are connected in order, and the outer leads 24 of the lowermost package are connected to the mounting substrate 22. A structure connected to the connection pad 25 has been developed.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、複数の
半導体パッケージ21を1枚の基板上に横並びに搭載・
実装した半導体モジュールでは、パッケージの個数が増
えるほど実装基板22上での実装面積が増大するため、
実装効率が著しく低下するという問題があった。However, a plurality of semiconductor packages 21 are mounted side by side on a single substrate.
In the mounted semiconductor module, the mounting area on the mounting board 22 increases as the number of packages increases.
There is a problem that the mounting efficiency is significantly reduced.
【0005】また、パッケージを垂直方向に積み重ねて
実装した積層モジュールにおいても、パッケージの個数
が増加するほど実装高さが増大するため、3次元的な実
装効率の低下が生じていた。In a stacked module in which packages are stacked in the vertical direction and mounted, the mounting height increases as the number of packages increases, and three-dimensional mounting efficiency is reduced.
【0006】さらに、従来の積層モジュールでは、半導
体素子をパッケージングした構造のものを積み重ねてお
り、半導体素子間の間隔を、パッケージの厚さ、外形、
リード(アウターリード)の形状、端子数等によって決
まる最小パッケージ間距離より小さくすることができな
いため、モジュール全体を小型化することが難しかっ
た。そして、パッケージ間を電気的に接続する配線の長
さが長くなるため、信号遅延やインダクタンスの増大等
の問題が生じ、システムの高速化の障害となっていた。Further, in a conventional laminated module, semiconductor devices having a packaged structure are stacked, and the distance between the semiconductor devices is determined by the thickness, outer shape,
Since the distance between the packages, which is determined by the shape of the lead (outer lead), the number of terminals, and the like, cannot be reduced, it has been difficult to reduce the size of the entire module. In addition, since the length of the wiring for electrically connecting the packages becomes longer, problems such as an increase in signal delay and an increase in inductance are caused, which is an obstacle to a high-speed system.
【0007】本発明は、これらの問題を解決するために
なされたもので、小型で半導体素子の実装効率が高く、
素子間の配線長をほとんどゼロにすることが可能な半導
体装置および半導体モジュールと、それらの製造方法を
提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and has a small size and a high mounting efficiency of a semiconductor element.
It is an object of the present invention to provide a semiconductor device and a semiconductor module capable of reducing the wiring length between elements to almost zero, and a method for manufacturing them.
【0008】[0008]
【課題を解決するための手段】本発明の第1の発明の半
導体装置は、電極端子の配設位置に表裏を貫通する貫通
孔を有する半導体素子基板と、この半導体素子基板の半
導体素子面である表面、および反対側の裏面にそれぞれ
形成された表面保護膜および絶縁樹脂膜と、前記半導体
素子基板の裏面の前記絶縁樹脂膜上で、前記貫通孔の開
口の周りに形成された導体パッドと、前記貫通孔の内周
面に周設された中間絶縁層と、前記貫通孔内で前記中間
絶縁層の内側に形成された導電層とを備え、この導電層
が、前記半導体素子基板の表面側の電極端子および裏面
側の導体パッドに、直接または他の導電層を介して電気
的に接続されていることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor element substrate having a through hole penetrating front and back at an electrode terminal arrangement position, and a semiconductor element surface of the semiconductor element substrate. A surface, a surface protective film and an insulating resin film respectively formed on the opposite back surface, and a conductive pad formed around the opening of the through hole on the insulating resin film on the back surface of the semiconductor element substrate. An intermediate insulating layer provided on an inner peripheral surface of the through hole, and a conductive layer formed inside the intermediate insulating layer in the through hole, the conductive layer being provided on a surface of the semiconductor element substrate. It is electrically connected to the electrode terminal on the side and the conductor pad on the back side directly or via another conductive layer.
【0009】第2の発明の半導体モジュールは、前記し
た第1の発明の半導体装置の複数個を、厚さ方向に重ね
て配置し、各半導体装置の当接する面を接着するととも
に、相互に電気的に接続したことを特徴とする。In a semiconductor module according to a second aspect of the present invention, a plurality of the semiconductor devices according to the first aspect of the present invention are arranged in an overlapping manner in the thickness direction, and the contact surfaces of the semiconductor devices are adhered to each other. It is characterized by the fact that the connection is made.
【0010】第3の発明の半導体装置の製造方法は、半
導体素子基板の半導体素子面である表面および裏面に、
表面保護膜および絶縁樹脂膜をそれぞれ形成する工程
と、前記半導体素子基板の表面に形成された電極端子に
対応して、裏面の前記絶縁樹脂膜上に導体パッドを形成
する工程と、前記電極端子および導体パッドの形成位置
に、前記半導体素子基板の表裏を貫通する第1の貫通孔
を形成する工程と、前記第1の貫通孔内に絶縁性樹脂を
充填する工程と、前記絶縁性樹脂の充填層を厚さ方向に
貫通して、第2の貫通孔を形成する工程と、前記第2の
貫通孔内に導電性材料を充填する工程と、前記導電性材
料の充填層と前記電極端子および導体パッドを、直接ま
たは他の導電層を介して接続する工程とを備えたことを
特徴とする。The method of manufacturing a semiconductor device according to a third aspect of the present invention is a method for manufacturing a semiconductor device, comprising:
Forming a surface protection film and an insulating resin film, respectively; forming a conductive pad on the insulating resin film on the back surface corresponding to the electrode terminal formed on the surface of the semiconductor element substrate; Forming a first through-hole penetrating the front and back of the semiconductor element substrate at a position where the conductive pad is formed; filling the first through-hole with an insulating resin; Forming a second through hole by penetrating the filling layer in the thickness direction, filling a conductive material in the second through hole, filling the conductive material with the filling layer and the electrode terminal And connecting the conductive pad directly or via another conductive layer.
【0011】第4の発明の半導体装置の製造方法は、半
導体素子基板の半導体素子面である表面および裏面に、
表面保護膜および絶縁樹脂膜をそれぞれ形成する工程
と、前記半導体素子基板の表面に形成された電極端子に
対応して、裏面の前記絶縁樹脂膜上に導体パッドを形成
する工程と、前記電極端子および導体パッドの形成位置
に、レーザー光の照射により、前記半導体素子基板の表
裏を貫通する第1の貫通孔を形成すると同時に、形成さ
れた貫通孔の内周面を熱酸化して絶縁性の酸化物層を形
成する工程と、内周面に前記酸化物層が形成された前記
第1の貫通孔内に、導電性材料を充填する工程と、前記
導電性材料の充填層と前記電極端子および導体パッド
を、直接または他の導電層を介して接続する工程とを備
えたことを特徴とする。In a fourth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of:
Forming a surface protection film and an insulating resin film, respectively; forming a conductive pad on the insulating resin film on the back surface corresponding to the electrode terminal formed on the surface of the semiconductor element substrate; And forming a first through-hole penetrating the front and back of the semiconductor element substrate by irradiating a laser beam at a position where the conductive pad is to be formed, and at the same time, thermally oxidizing an inner peripheral surface of the formed through-hole to obtain an insulating property. A step of forming an oxide layer, a step of filling a conductive material in the first through hole in which the oxide layer is formed on an inner peripheral surface, a step of filling the conductive material with the filled layer and the electrode terminal And connecting the conductive pad directly or via another conductive layer.
【0012】第5の発明の半導体モジュールの製造方法
は、半導体素子基板の半導体素子面である表面および裏
面に、表面保護膜および絶縁樹脂膜をそれぞれ形成する
工程と、前記半導体素子基板の表面に形成された電極端
子に対応して、裏面の前記絶縁樹脂膜上に導体パッドを
形成する工程と、前記電極端子および導体パッドの形成
位置に、前記半導体素子基板の表裏を貫通する第1の貫
通孔を形成する工程と、前記第1の貫通孔内に絶縁性樹
脂を充填する工程と、前記第1の貫通孔内に前記絶縁性
樹脂の充填層が形成された構造体の複数個を、前記第1
の貫通孔の位置が一致するように重ね、各構造体の当接
面を接着剤により接着する工程と、前記接着工程で得ら
れた積層構造体において、前記絶縁性樹脂の充填層を厚
さ方向全体に亘って貫通する第2の貫通孔を形成する工
程と、前記第2の貫通孔内に導電性材料を充填する工程
と、前記導電性材料の充填層と、前記積層構造体の最上
面および最下面にそれぞれ配置された前記電極端子また
は導体パッドを、直接または他の導電層を介して接続す
る工程とを備えたことを特徴とする。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor module, comprising: forming a surface protective film and an insulating resin film on a front surface and a back surface of a semiconductor element substrate, respectively; Forming a conductor pad on the back surface of the insulating resin film corresponding to the formed electrode terminal; and forming a first penetration penetrating the front and back of the semiconductor element substrate at a position where the electrode terminal and the conductor pad are formed. Forming a hole, filling the first through hole with an insulating resin, and forming a plurality of the structures having the insulating resin filling layer formed in the first through hole, The first
And a step of bonding the contact surfaces of the respective structures with an adhesive so that the positions of the through holes coincide with each other, and in the laminated structure obtained in the bonding step, the thickness of the filling layer of the insulating resin is reduced. Forming a second through-hole penetrating in the entire direction, filling the second through-hole with a conductive material, filling the conductive material with a layer, Connecting the electrode terminals or the conductive pads respectively disposed on the upper surface and the lowermost surface, directly or via another conductive layer.
【0013】なお、本発明では、半導体ウェハまたは半
導体ウェハをダイシングした半導体チップをまとめて、
半導体素子基板と示すものとする。In the present invention, a semiconductor wafer or a semiconductor chip obtained by dicing the semiconductor wafer is put together,
It is referred to as a semiconductor element substrate.
【0014】本発明の半導体装置および半導体モジュー
ルにおいては、半導体素子基板の貫通孔内に形成された
導電層により、半導体素子領域の形成された表面側から
裏面側へのスルーホール接続がなされているので、半導
体素子基板の表裏両面に電極端子を形成することがで
き、半導体素子基板相互の接続構造、および半導体素子
基板と実装基板との接続構造を、多肢に亘って選択する
ことができる。その結果、複数の半導体素子基板を3次
元的に積層し高密度に実装した超小型で低コストの半導
体装置およびモジュールを、容易に実現することができ
る。In the semiconductor device and the semiconductor module according to the present invention, the conductive layer formed in the through hole of the semiconductor element substrate makes a through-hole connection from the front side where the semiconductor element region is formed to the rear side. Therefore, the electrode terminals can be formed on both the front and back surfaces of the semiconductor element substrate, and the connection structure between the semiconductor element substrates and the connection structure between the semiconductor element substrate and the mounting substrate can be selected in many ways. As a result, an ultra-compact and low-cost semiconductor device and module in which a plurality of semiconductor element substrates are three-dimensionally stacked and densely mounted can be easily realized.
【0015】また、3次元的に積層された複数の半導体
素子基板間の接続が、前記したスルーホール接続を介し
て行なわれるので、半導体素子間の配線はほとんど不要
となる。このように、半導体素子間の電気配線長をほと
んどゼロにすることができるので、配線による信号遅延
およびインダクタンスの発生を著しく低減することがで
き、モジュールの高速化・小型化を達成することができ
る。Further, since connection between a plurality of three-dimensionally stacked semiconductor element substrates is performed through the above-described through-hole connection, wiring between the semiconductor elements is almost unnecessary. As described above, since the length of the electric wiring between the semiconductor elements can be made almost zero, the signal delay and the occurrence of inductance due to the wiring can be significantly reduced, and the high speed and miniaturization of the module can be achieved. .
【0016】さらに、本発明の半導体装置および半導体
モジュールでは、従来からの積層モジュールと異なり、
半導体素子を1個ずつパッケージングする必要がない。
そして、半導体素子基板の段階で一括して積層を行なこ
とができるため、モジュール化が容易であり、製造の工
程数および総工程時間を大幅に削減することができる。
したがって、モジュール当たりの製造コストを著しく低
減することができる。Further, in the semiconductor device and the semiconductor module of the present invention, unlike the conventional laminated module,
It is not necessary to package semiconductor elements one by one.
Then, since the layers can be collectively formed at the stage of the semiconductor element substrate, modularization is easy, and the number of manufacturing steps and the total processing time can be greatly reduced.
Therefore, the manufacturing cost per module can be significantly reduced.
【0017】[0017]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0018】図1は、本発明の半導体装置の第1の実施
例の要部を示す断面図である。FIG. 1 is a sectional view showing a main part of a first embodiment of a semiconductor device according to the present invention.
【0019】図において、符号1は、半導体ウェハまた
は半導体チップ(以下、半導体素子基板とする。)を示
し、その素子領域形成面(以下、表面と示す。)に、電
極パッド2aが形成されている。そして、この表面側の
電極パッド2aの中央に、半導体素子基板1の表裏を貫
通する貫通孔3が設けられている。また、半導体素子基
板1の表面には、酸化シリコン等の表面保護膜(パッシ
ベーション膜)4が形成され、裏面にはポリイミド等の
絶縁樹脂膜5が形成されている。さらに、裏面の絶縁樹
脂膜5上において、貫通孔3の開口の周りには、裏面側
の電極パッド2bが形成されている。In FIG. 1, reference numeral 1 denotes a semiconductor wafer or a semiconductor chip (hereinafter, referred to as a semiconductor element substrate), and an electrode pad 2a is formed on a surface on which an element region is formed (hereinafter, referred to as a surface). I have. In the center of the electrode pad 2a on the front side, a through hole 3 penetrating the front and back of the semiconductor element substrate 1 is provided. A surface protection film (passivation film) 4 such as silicon oxide is formed on the surface of the semiconductor element substrate 1, and an insulating resin film 5 such as polyimide is formed on the back surface. Further, on the insulating resin film 5 on the back surface, around the opening of the through hole 3, an electrode pad 2b on the back surface is formed.
【0020】また、貫通孔3内には、内周面に接して中
間絶縁層6が周設され、この中間絶縁層6の内側には、
導電層7が充填されている。さらに、このように貫通孔
3内に充填・形成された導電層7の両端部には、表面側
および裏面側の電極パッド2a、2bに跨がって、表面
側および裏面側の導電被覆層8a、8bがそれぞれ形成
されており、これらの導電被覆層8a、8bを介して、
両面側の電極パッド2a、2bと導電層7とがそれぞれ
電気的に接続されている。なお、少なくとも一方の面側
の導電被覆層8a、8bを、貫通孔3内に充填・形成さ
れた導電層7と同じ導電性材料で形成することができ
る。In the through hole 3, an intermediate insulating layer 6 is provided in contact with the inner peripheral surface, and inside the intermediate insulating layer 6,
The conductive layer 7 is filled. Further, at both ends of the conductive layer 7 filled and formed in the through hole 3 as described above, the conductive coating layers on the front side and the back side are laid over the electrode pads 2a and 2b on the front side and the back side. 8a and 8b are formed respectively, and via these conductive coating layers 8a and 8b,
The electrode pads 2a and 2b on both sides and the conductive layer 7 are electrically connected to each other. The conductive coating layers 8 a and 8 b on at least one surface side can be formed of the same conductive material as the conductive layer 7 filled and formed in the through-hole 3.
【0021】このような構造を有する半導体装置は、例
えば、以下に示す工程を経て製造される。A semiconductor device having such a structure is manufactured, for example, through the following steps.
【0022】まず、図2(a)に示すように、半導体素
子基板1の表面および裏面に、酸化シリコン等のパッシ
ベーション膜4とポリイミド等の絶縁樹脂膜5を、常法
によりそれぞれ形成し、裏面側の絶縁樹脂膜5上で、表
面側に形成された電極パッド2aに対応する位置に、裏
面側の電極パッド2bを形成する。First, as shown in FIG. 2A, a passivation film 4 made of silicon oxide or the like and an insulating resin film 5 made of polyimide or the like are formed on the front surface and the back surface of the semiconductor element substrate 1 by a conventional method. On the insulating resin film 5 on the side, electrode pads 2b on the back side are formed at positions corresponding to the electrode pads 2a formed on the front side.
【0023】次いで、プラズマエッチング、反応性イオ
ンエッチング(RIE)またはレーザー光照射等(白抜
き矢印で示す。)の方法により、図2(b)に示すよう
に、表面側の電極パッド2aの中央で半導体素子基板1
の表裏を貫通し、さらに裏面側の電極パッド2bを貫通
する第1の貫通孔3を形成した後、この第1の貫通孔3
内に、流動性(例えばペースト状)の絶縁性樹脂を充填
し、図2(c)に示すように、絶縁性樹脂の充填層9を
形成する。Next, as shown in FIG. 2B, the center of the electrode pad 2a on the front side is formed by a method such as plasma etching, reactive ion etching (RIE), or laser beam irradiation (indicated by a white arrow). Semiconductor element substrate 1
After forming a first through-hole 3 penetrating the front and back of the first through-hole and further penetrating the electrode pad 2b on the back side, the first through-hole 3 is formed.
The inside is filled with a fluid (for example, paste-like) insulating resin, and a filling layer 9 of the insulating resin is formed as shown in FIG.
【0024】次に、図2(d)に示すように、プラズマ
エッチング、反応性イオンエッチング(RIE)または
レーザー光照射等の方法により、絶縁性樹脂の充填層9
を厚さ方向に貫通する小径の第2の貫通孔10を同心的
に形成し、中間絶縁層6を形成した後、図2(e)に示
すように、この第2の貫通孔10内に流動性の導電性樹
脂等を充填し、導電層7を形成する。しかる後、図2
(f)に示すように、この導電層7の両端部に、表面側
および裏面側の電極パッド2a、2bに跨がって導電性
材料を塗布し、表面側および裏面側の導電被覆層8a、
8bを形成する。こうして、第1の実施例の半導体装置
が得られる。Next, as shown in FIG. 2D, the insulating resin filling layer 9 is formed by a method such as plasma etching, reactive ion etching (RIE), or laser beam irradiation.
Is formed concentrically in the thickness direction, and after forming the intermediate insulating layer 6, as shown in FIG. 2 (e), the second through hole 10 is formed in the second through hole 10. The conductive layer 7 is formed by filling a fluid conductive resin or the like. After a while, FIG.
As shown in (f), a conductive material is applied to both ends of the conductive layer 7 across the front and back electrode pads 2a and 2b, and the front and back conductive coating layers 8a are formed. ,
8b is formed. Thus, the semiconductor device of the first embodiment is obtained.
【0025】なお、このような半導体装置の製造方法
で、特にレーザー光の照射により第1の貫通孔3を形成
する場合には、レーザー光のエネルギー等の照射条件を
調整することにより、貫通孔3の形成と同時に、孔の内
周面の半導体を熱酸化し、絶縁性の酸化物(例えば、酸
化シリコン)層を形成することができる。そして、この
ようにして、貫通孔の形成と同時に絶縁性の酸化物層を
形成する方法では、前記した絶縁性樹脂を充填する工程
(図2(c))および絶縁性樹脂の充填層9に第2の貫
通孔10を形成する工程(図2(d))を経ることな
く、第1の貫通孔3内に導電性樹脂等を充填し、次いで
表面側および裏面側の導電性被覆層8a、8bを形成す
る工程を行なうことができる。In this method of manufacturing a semiconductor device, particularly, when the first through hole 3 is formed by irradiating a laser beam, by adjusting irradiation conditions such as energy of a laser beam, the through hole is formed. Simultaneously with the formation of 3, the semiconductor on the inner peripheral surface of the hole can be thermally oxidized to form an insulating oxide (for example, silicon oxide) layer. In the method of forming the insulating oxide layer simultaneously with the formation of the through hole, the step of filling the insulating resin (FIG. 2C) and the filling step 9 of the insulating resin are performed. The first through-hole 3 is filled with a conductive resin or the like without going through the step of forming the second through-hole 10 (FIG. 2D), and then the conductive coating layer 8a on the front side and the back side , 8b can be performed.
【0026】こうして製造される第1の実施例の半導体
装置においては、半導体素子基板1の表裏を貫通する貫
通孔3内に充填・形成された導電層7により、表面側か
ら裏面側へのスルーホール接続がなされているので、半
導体素子基板1の表裏両面に接続用の電極パッド2a、
2bを形成することができる。したがって、半導体装置
相互の接続構造、および実装基板への接続構造に対する
選択肢が大幅に増加する。その結果、複数の半導体装置
を3次元的に積層し、高密度に実装した超小型で低コス
トのモジュールを、容易に得ることができる。In the semiconductor device of the first embodiment manufactured as described above, the conductive layer 7 filled and formed in the through-hole 3 penetrating the front and back of the semiconductor element substrate 1 allows the through-hole from the front side to the back side. Since the hole connection is made, electrode pads 2a for connection are provided on both front and back surfaces of the semiconductor element substrate 1.
2b can be formed. Therefore, the number of options for the connection structure between the semiconductor devices and the connection structure to the mounting substrate is greatly increased. As a result, an ultra-small and low-cost module in which a plurality of semiconductor devices are three-dimensionally stacked and densely mounted can be easily obtained.
【0027】次に、本発明の第2の実施例について説明
する。Next, a second embodiment of the present invention will be described.
【0028】この実施例は、半導体装置の複数個を積層
し相互に接続した半導体モジュールであり、図3に示す
ように、前記した第1の実施例の半導体装置の複数個
(3個の場合を図に示す。)が、互いに裏面側と表面側
が対向し、かつ貫通孔3の位置が一致するように重ねて
配置され、対向する面の電極パッド2a、2b上を除く
全面に形成された接着剤層11を介して、接着一体化さ
れている。This embodiment is a semiconductor module in which a plurality of semiconductor devices are stacked and connected to each other. As shown in FIG. 3, as shown in FIG. Are shown in the drawing.), The back surface side and the front surface side are opposed to each other, and they are arranged so as to overlap with each other so that the positions of the through holes 3 coincide with each other. It is bonded and integrated through the adhesive layer 11.
【0029】そして、各層の半導体装置において、表面
側および裏面側にそれぞれ形成された導電被覆層8a、
8bが、上層および下層にそれぞれ配置された半導体装
置の導電被覆層と当接され、電気的に接続されている。
また、最上層に配置された半導体装置の表面側の導電被
覆層8a、あるいは最下層に配置された半導体装置の裏
面側の導電被覆層8bには、はんだボールのような実装
用の外部端子12が接合されている。Then, in the semiconductor device of each layer, the conductive coating layers 8a formed on the front side and the back side, respectively.
8b is in contact with and electrically connected to the conductive coating layers of the semiconductor device disposed in the upper layer and the lower layer, respectively.
The conductive coating layer 8a on the front surface of the semiconductor device disposed on the uppermost layer or the conductive coating layer 8b on the rear surface of the semiconductor device disposed on the lowermost layer is provided with external terminals 12 such as solder balls for mounting. Are joined.
【0030】なお、この実施例では、各半導体装置の裏
面側と表面側が対向するように、順に積層された構造の
モジュールについて説明したが、重ね合わせの向きにつ
いては特に限定されず、裏面側と裏面側、表面側と表面
側とがそれぞれ対向し当接されるように重ね合わせても
良い。In this embodiment, modules having a structure in which layers are sequentially stacked so that the back side and the front side of each semiconductor device are opposed to each other are described. The back side, the front side, and the front side may be overlapped so that they face each other and come into contact with each other.
【0031】このような構造を有する第2の実施例の半
導体モジュールにおいては、各半導体装置が、半導体素
子基板1の表面側から裏面側へのスルーホール接続によ
り互いに電気的に接続されており、半導体素子間の電気
配線長がほとんどゼロになっているので、配線による信
号遅延やインダクタンスの発生が著しく低減され、モジ
ュールの高速化および小型化が達成される。In the semiconductor module of the second embodiment having such a structure, the semiconductor devices are electrically connected to each other by through-hole connections from the front side to the back side of the semiconductor element substrate 1. Since the length of the electric wiring between the semiconductor elements is almost zero, the occurrence of signal delay and inductance due to the wiring is significantly reduced, and the module can be made faster and smaller.
【0032】第2の実施例の半導体モジュールは、以下
に示す方法により製造することができる。The semiconductor module of the second embodiment can be manufactured by the following method.
【0033】すなわち、第1の製造方法では、図2に示
す方法で得られた第1の実施例の半導体装置において、
図4(a)に示すように、一方の面(図では裏面)の電
極パッド2b上を除く全面に、接着剤を貼付または塗布
することにより、接着剤層11を形成した後、これらの
半導体装置の複数個を、裏面側と表面側が互いに対向
し、かつ貫通孔3の位置が一致するように重ねる。そし
て、熱を加えながら圧着することにより、図4(b)に
示すように、積層体を得る。次いで、図4(c)に示す
ように、このような積層体の最上層または最下層に配置
された導電被覆層8a、8bに、はんだボールのような
実装用の外部端子12を接合することにより、積層モジ
ュールが完成する。That is, in the first manufacturing method, in the semiconductor device of the first embodiment obtained by the method shown in FIG.
As shown in FIG. 4A, an adhesive layer 11 is formed by applying or applying an adhesive to the entire surface except for the electrode pad 2b on one surface (the back surface in the figure), and then, these semiconductors are formed. A plurality of devices are stacked so that the back side and the front side face each other, and the positions of the through holes 3 coincide. Then, by applying pressure while applying heat, a laminate is obtained as shown in FIG. Next, as shown in FIG. 4C, the mounting external terminals 12 such as solder balls are joined to the conductive coating layers 8a and 8b disposed on the uppermost layer or the lowermost layer of such a laminate. Thereby, the laminated module is completed.
【0034】第2の実施例の半導体モジュールは、以下
に示す方法によっても製造することができる。なお、以
下の工程図(e)〜(j)では、繁雑化を避けるため
に、半導体素子基板の裏面に形成される絶縁樹脂膜は、
図示を省略する。The semiconductor module of the second embodiment can be manufactured by the following method. In the following process diagrams (e) to (j), in order to avoid complication, the insulating resin film formed on the back surface of the semiconductor element substrate is
Illustration is omitted.
【0035】第2の製造方法では、図5(a)に示すよ
うに、半導体素子基板1の表裏両面に、酸化シリコン等
のパッシベーション膜4とポリイミド等の絶縁樹脂膜5
とをそれぞれ形成した後、プラズマエッチング、反応性
イオンエッチング(RIE)またはレーザー光照射等の
方法により、表面側の電極パッド2aの中央部で半導体
素子基板1を貫通する第1の貫通孔3を形成する。な
お、裏面側の絶縁樹脂膜5上で、表面側の電極パッド2
aに対応する位置に、裏面側の電極パッド2bを形成し
た後、第1の貫通孔3として、表面側の電極パッド2a
から裏面側の電極パッド2bへと、半導体素子基板1の
表裏を貫通する孔を形成しても良い。In the second manufacturing method, as shown in FIG. 5A, a passivation film 4 of silicon oxide or the like and an insulating resin film 5 of polyimide or the like
Are formed, a first through hole 3 penetrating the semiconductor element substrate 1 at the center of the electrode pad 2a on the front side is formed by a method such as plasma etching, reactive ion etching (RIE), or laser beam irradiation. Form. The electrode pads 2 on the front side are formed on the insulating resin film 5 on the rear side.
After the electrode pad 2b on the back side is formed at a position corresponding to a, a first through hole 3 is formed as the electrode pad 2a on the front side.
A hole penetrating the front and back of the semiconductor element substrate 1 may be formed from the substrate to the electrode pad 2b on the back side.
【0036】次いで、図5(b)に示すように、この第
1の貫通孔3内に流動性の絶縁性樹脂を充填し、絶縁性
樹脂の充填層9を形成した後、図5(c)に示すよう
に、この絶縁性樹脂の充填層9の少なくとも一方の端部
(例えば、裏面側の端部)に、導電性材料を塗布し、導
電被覆層8bを形成する。Next, as shown in FIG. 5B, the first through hole 3 is filled with a fluid insulating resin to form a filling layer 9 of the insulating resin. As shown in (1), a conductive material is applied to at least one end (for example, the end on the back surface side) of the insulating resin filling layer 9 to form a conductive coating layer 8b.
【0037】次に、このような半導体構造体の複数個を
重ねて積層一体化するにあたり、図5(d)に示すよう
に、各構造体の対向する面(例えば裏面)の導電被覆層
8b上を除く全面に、接着剤の貼付または塗布により接
着剤層11を形成した後、図5(e)に示すように、貫
通孔3の位置が一致するように重ね、熱圧着する。こう
して、図5(f)に示すように、半導体構造体の積層体
を得る。Next, in stacking and laminating a plurality of such semiconductor structures, as shown in FIG. 5D, the conductive coating layer 8b on the opposing surface (for example, the back surface) of each structure is used. After an adhesive layer 11 is formed on the entire surface except for the upper portion by applying or applying an adhesive, as shown in FIG. 5E, the adhesive layers 11 are overlaid so that the positions of the through holes 3 coincide with each other, and thermocompression-bonded. Thus, as shown in FIG. 5F, a stacked body of the semiconductor structure is obtained.
【0038】しかる後、図5(g)および図5(h)に
示すように、プラズマエッチング、反応性イオンエッチ
ング(RIE)、レーザー光照射等の方法により、各半
導体構造体の第1の貫通孔3内に形成された絶縁性樹脂
の充填層9と、その端部に形成された導電被覆層8bと
を順に貫通する第2の貫通孔10を、積層体の厚さ方向
全体に亘って連続して形成した後、図5(i)に示すよ
うに、この第2の貫通孔10内に導電性樹脂を充填し、
導電層7を形成する。Thereafter, as shown in FIGS. 5G and 5H, the first penetration of each semiconductor structure is performed by a method such as plasma etching, reactive ion etching (RIE), or laser beam irradiation. A second through-hole 10 penetrating through the insulating resin filling layer 9 formed in the hole 3 and the conductive coating layer 8b formed at the end thereof is formed in the entire thickness direction of the laminate. After the continuous formation, as shown in FIG. 5 (i), a conductive resin is filled in the second through-hole 10,
The conductive layer 7 is formed.
【0039】こうして、各半導体構造体の裏面に形成さ
れた導電被覆層8bは、いずれも、第2の貫通孔10内
に形成された導電層7に導通されるので、この導電層7
を介して、各半導体構造体は相互に電気的に接続され
る。なお、この段階では、積層体の最上面に配置・形成
された電極パッド2aのみが、導電層7に接続されてい
ないことになる。In this manner, the conductive coating layer 8b formed on the back surface of each semiconductor structure is conducted to the conductive layer 7 formed in the second through hole 10, so that the conductive layer 7b
, The respective semiconductor structures are electrically connected to each other. At this stage, only the electrode pads 2a arranged and formed on the uppermost surface of the stacked body are not connected to the conductive layer 7.
【0040】しかる後、図5(j)に示すように、この
最上層の電極パッド2a上に、導電性材料を塗布するな
どの方法で導電被覆層8aを形成し、この層を介して、
最上層の電極パッド2aと導電層7とを電気的に接続し
た後、最上層の導電被覆層8aに、ボール状のはんだバ
ンプ等の実装用外部端子12を接合することにより、積
層モジュールが完成する。Thereafter, as shown in FIG. 5 (j), a conductive coating layer 8a is formed on the uppermost electrode pad 2a by applying a conductive material or the like.
After the uppermost electrode pad 2a and the conductive layer 7 are electrically connected to each other, the mounting external terminals 12 such as ball-shaped solder bumps are joined to the uppermost conductive coating layer 8a to complete the laminated module. I do.
【0041】このような第2の製造方法によれば、第1
の製造方法で、半導体装置のそれぞれにおいて行なって
いた第2の貫通孔10の形成およびこの貫通孔内への導
電性樹脂の注入・充填を、複数の半導体構造体を積層し
た積層体全体に対して、一度に行なうことができるの
で、工程数および総プロセス時間を著しく削減すること
ができる。そして、モジュール化工程が容易になるだけ
でなく、モジュール当たりの製造コストを低減すること
ができる。According to the second manufacturing method, the first
In the manufacturing method described above, the formation of the second through hole 10 and the injection and filling of the conductive resin into the through hole, which were performed in each of the semiconductor devices, are performed on the entire stacked body in which the plurality of semiconductor structures are stacked. Therefore, since the processes can be performed at once, the number of steps and the total process time can be significantly reduced. And not only the modularization process becomes easy, but also the manufacturing cost per module can be reduced.
【0042】なお、第1の実施例の半導体装置におい
て、半導体素子基板1の裏面側に設けられる絶縁樹脂膜
を、接着性のある絶縁材料により構成する場合には、前
記した第1および第2の製造方法の熱圧着工程で、半導
体装置の対向面への接着剤の貼付または塗布を行なう必
要がなく、工程数の削減が可能となる。In the semiconductor device of the first embodiment, when the insulating resin film provided on the back surface side of the semiconductor element substrate 1 is made of an adhesive insulating material, the first and second insulating films are used. In the thermocompression bonding step of the manufacturing method described above, there is no need to apply or apply an adhesive to the opposing surface of the semiconductor device, and the number of steps can be reduced.
【0043】次に、複数の半導体装置を積層し電気的に
接続した半導体モジュールの別の実施例について説明す
る。Next, another embodiment of a semiconductor module in which a plurality of semiconductor devices are stacked and electrically connected will be described.
【0044】第3の実施例の半導体モジュールにおいて
は、図6に示すように、第1の実施例の半導体装置の複
数個(3個の場合を図に示す。)が、互いに裏面側と表
面側が対向するように積層・配置されている。そして、
各半導体装置では、半導体素子基板1の表面に、貫通孔
を有しない電極パッド2cが形成されており、この電極
パッド2cと、貫通孔3を有する表面側の電極パッド2
aとは、同じ素子領域形成面に形成された内部配線(図
示を省略。)などにより導通されている。In the semiconductor module of the third embodiment, as shown in FIG. 6, a plurality of semiconductor devices of the first embodiment (three are shown in the figure) are formed on the back side and the front side. They are stacked and arranged so that the sides face each other. And
In each semiconductor device, an electrode pad 2c having no through hole is formed on the surface of the semiconductor element substrate 1, and the electrode pad 2c and the electrode pad 2 on the front side having the through hole 3 are formed.
a is conducted by an internal wiring (not shown) formed on the same element region forming surface.
【0045】また、上下に対向した半導体装置の間で、
貫通孔3の位置が一致しない構造となっており、一方の
半導体装置(例えば、最上層の半導体装置)の貫通孔3
内に形成された導電層7と、他方の半導体装置(例え
ば、中間層の半導体装置)の貫通孔を有しない電極パッ
ド2cとが当接され、電気的に接続されている。また、
最上層に配置された半導体装置の表面側の導電被覆層8
a、あるいは最下層に配置された半導体装置の裏面側の
導電被覆層8bに、はんだボールのような実装用外部端
子12が接合されている。In addition, between the vertically opposed semiconductor devices,
The position of the through hole 3 does not match, and the through hole 3 of one semiconductor device (for example, the uppermost semiconductor device) is formed.
The conductive layer 7 formed therein and the electrode pad 2c having no through hole of the other semiconductor device (for example, a semiconductor device of an intermediate layer) are in contact with each other and are electrically connected. Also,
The conductive coating layer 8 on the front surface side of the semiconductor device disposed on the uppermost layer
The mounting external terminal 12 such as a solder ball is joined to the conductive coating layer 8b on the back surface side of the semiconductor device disposed at the bottom of the semiconductor device.
【0046】第3の実施例の半導体モジュールは、以下
に示す方法により製造される。The semiconductor module of the third embodiment is manufactured by the following method.
【0047】まず、図7(a)に示すように、前記した
図2に示す方法で得られた半導体装置において、一方の
面(図では裏面)の電極パッド2b上を除く全面に、接
着剤を貼付または塗布することにより、接着剤層11を
形成した後、これらの半導体装置の複数個を、裏面側と
表面側が互いに対向し、かつ一方の半導体装置の貫通孔
3内に形成された導電層7(および電極パッド2a、2
c)と他方の半導体装置の貫通孔を有しない電極パッド
2cとが当接するように、位置合わせして重ね、熱等を
加えながら圧着する。こうして得られた積層体を図7
(b)に示す。しかる後、このような積層体の最上層ま
たは最下層に配置された導電被覆層8a、8bに、はん
だボールのような実装用外部端子12を接合することに
より、積層モジュールが完成する。First, as shown in FIG. 7A, in the semiconductor device obtained by the method shown in FIG. 2 described above, the adhesive is applied to the entire surface except on the electrode pad 2b on one surface (the back surface in the figure). After the adhesive layer 11 is formed by sticking or applying, a plurality of these semiconductor devices are electrically connected to each other on the back surface side and the front surface side, and formed in the through hole 3 of one of the semiconductor devices. Layer 7 (and electrode pads 2a, 2a,
c) and the electrode pad 2c having no through-hole of the other semiconductor device are aligned and overlapped so that the electrode pad 2c does not have a through-hole, and pressure-bonded while applying heat or the like. FIG. 7 shows the laminate thus obtained.
(B). Thereafter, the mounting external terminals 12 such as solder balls are joined to the conductive coating layers 8a and 8b disposed on the uppermost layer or the lowermost layer of the stacked body, thereby completing the stacked module.
【0048】このように構成される第3の実施例の半導
体モジュールにおいては、各半導体装置が、半導体素子
基板1の表面側から裏面側へのスルーホール接続と、半
導体素子領域形成面に形成された内部配線などにより、
相互に電気的に接続されている。したがって、各半導体
装置において、半導体素子基板1上に形成される電極パ
ッドおよび配線の設計の自由度が増大し、様々なパター
ンの電極パッドおよび配線パターンを有する半導体素子
基板1を用いて、良好な電気的特性を有する半導体モジ
ュールを構成することが可能となる。In the semiconductor module of the third embodiment configured as described above, each semiconductor device is formed in a through hole connection from the front side to the back side of the semiconductor element substrate 1 and on the semiconductor element region forming surface. Due to internal wiring
They are electrically connected to each other. Therefore, in each semiconductor device, the degree of freedom in designing electrode pads and wirings formed on the semiconductor element substrate 1 is increased, and the semiconductor element substrate 1 having various patterns of electrode pads and wiring patterns is used. A semiconductor module having electrical characteristics can be configured.
【0049】[0049]
【発明の効果】以上の記載から明らかなように、本発明
においては、半導体素子基板の貫通孔内に形成された導
電層により、素子領域の形成された表面側から裏面側へ
のスルーホール接続がなされているので、半導体素子基
板の表裏両面に電極を形成することができ、半導体素子
基板相互の接続構造、および半導体素子基板と実装基板
との接続構造を、多肢に亘って選択することができる。
その結果、複数の半導体素子基板を3次元的に積層し、
高密度に実装した超小型で低コストの半導体装置および
モジュールを、容易に実現することができる。As is apparent from the above description, in the present invention, a through-hole connection from the front surface side in which the element region is formed to the rear surface side is provided by the conductive layer formed in the through hole of the semiconductor element substrate. Therefore, electrodes can be formed on both the front and back surfaces of the semiconductor element substrate, and the connection structure between the semiconductor element substrates and the connection structure between the semiconductor element substrate and the mounting substrate can be selected over many options. Can be.
As a result, a plurality of semiconductor element substrates are three-dimensionally stacked,
An ultra-compact and low-cost semiconductor device and module mounted at high density can be easily realized.
【0050】また、半導体素子間の接続が、スルーホー
ル接続を介して行なわれるので、素子間の電気配線長を
ほとんどゼロにすることができ、配線による信号遅延お
よびインダクタンスの発生を著しく低減し、モジュール
の高速化・小型化を達成することができる。Further, since the connection between the semiconductor elements is made through the through-hole connection, the length of the electric wiring between the elements can be reduced to almost zero, and the signal delay and the occurrence of inductance due to the wiring are significantly reduced. Higher speed and smaller size of the module can be achieved.
【図1】本発明の第1の実施例である半導体装置の要部
を示す断面図。FIG. 1 is a sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention.
【図2】第1の実施例の半導体装置を製造する方法の各
工程を示す断面図。FIG. 2 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device of the first embodiment.
【図3】本発明の第2の実施例である半導体モジュール
の要部を示す断面図。FIG. 3 is a sectional view showing a main part of a semiconductor module according to a second embodiment of the present invention.
【図4】第2の実施例を製造する第1の方法の各工程を
示す断面図。FIG. 4 is a sectional view showing each step of a first method of manufacturing the second embodiment.
【図5】第2の実施例を製造する第2の方法の各工程を
示す断面図。FIG. 5 is a sectional view showing each step of a second method of manufacturing the second embodiment.
【図6】本発明の第3の実施例である半導体モジュール
の要部を示す断面図。FIG. 6 is a sectional view showing a main part of a semiconductor module according to a third embodiment of the present invention.
【図7】第3の実施例を製造する方法の各工程を示す断
面図。FIG. 7 is a sectional view showing each step of a method for manufacturing the third embodiment.
【図8】従来からの半導体モジュールの1例を示す斜視
図。FIG. 8 is a perspective view showing an example of a conventional semiconductor module.
【図9】従来からの半導体積層モジュールの1例を示す
断面図。FIG. 9 is a sectional view showing an example of a conventional semiconductor laminated module.
【図10】従来からの半導体積層モジュールの別の例を
示す断面図。FIG. 10 is a sectional view showing another example of a conventional semiconductor laminated module.
1………半導体素子基板 2a………表面側の電極パッド 2b………裏面側の電極パッド 3………貫通孔(第1の貫通孔) 4………表面保護膜(パッシベーション膜) 5………絶縁樹脂膜 6………中間絶縁層 7………導電層 8a………表面側の導電被覆層 8b………裏面側の導電被覆層 9………絶縁性樹脂の充填層 10………第2の貫通孔 11………接着剤層 12………実装用外部端子 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element substrate 2a ... Front side electrode pad 2b ... Back side electrode pad 3 ... Through hole (first through hole) 4 ... Surface protective film (passivation film) 5 ... Insulating resin film 6... Intermediate insulating layer 7... Conductive layer 8a... Front surface conductive coating layer 8b... Back side conductive coating layer 9... Insulating resin filling layer 10 ... Second through-hole 11 Adhesive layer 12 External terminals for mounting
Claims (7)
通孔を有する半導体素子基板と、この半導体素子基板の
半導体素子面である表面、および反対側の裏面にそれぞ
れ形成された表面保護膜および絶縁樹脂膜と、前記半導
体素子基板の裏面の前記絶縁樹脂膜上で、前記貫通孔の
開口の周りに形成された導体パッドと、前記貫通孔の内
周面に周設された中間絶縁層と、前記貫通孔内で前記中
間絶縁層の内側に形成された導電層とを備え、この導電
層が、前記半導体素子基板の表面側の電極端子および裏
面側の導体パッドに、直接または他の導電層を介して電
気的に接続されていることを特徴とする半導体装置。1. A semiconductor element substrate having a through-hole penetrating the front and back at a position where an electrode terminal is provided, and a front surface protection film formed on a front surface, which is a semiconductor element surface of the semiconductor element substrate, and a back surface on an opposite side. A conductive pad formed around the opening of the through hole on the insulating resin film on the back surface of the semiconductor element substrate; and an intermediate insulating layer provided on the inner peripheral surface of the through hole. And a conductive layer formed inside the intermediate insulating layer in the through-hole, and the conductive layer is directly or otherly connected to the electrode terminals on the front side and the conductive pads on the back side of the semiconductor element substrate. A semiconductor device which is electrically connected through a conductive layer.
厚さ方向に重ねて配置し、各半導体装置の当接する面を
接着するとともに、相互に電気的に接続したことを特徴
とする半導体モジュール。2. The method according to claim 1, further comprising:
A semiconductor module, wherein the semiconductor modules are arranged so as to be overlapped in a thickness direction, and a contact surface of each semiconductor device is bonded and electrically connected to each other.
孔の位置が一致するように重ねて配置され、半導体装置
間の電気的接続が、前記貫通孔内に形成された導電層を
介してなされていることを特徴とする請求項2記載の半
導体モジュール。3. The semiconductor device according to claim 1, wherein a plurality of the semiconductor devices are disposed so as to overlap with each other so that the positions of the respective through-holes coincide with each other, and electrical connection between the semiconductor devices is performed via a conductive layer formed in the through-hole. 3. The semiconductor module according to claim 2, wherein said semiconductor module is provided.
ない不一致部を有し、この不一致部においては、前記半
導体素子面に形成された電極端子間を接続する内部配線
を介して、電気的に接続されていることを特徴とする請
求項2記載の半導体モジュール。4. A semiconductor device according to claim 1, further comprising: a mismatching portion in which positions of the through holes of the semiconductor device do not match. In the mismatching portion, an electrical connection is established via an internal wiring connecting electrode terminals formed on the semiconductor element surface. The semiconductor module according to claim 2, wherein the semiconductor module is connected to the semiconductor module.
面および裏面に、表面保護膜および絶縁樹脂膜をそれぞ
れ形成する工程と、 前記半導体素子基板の表面に形成された電極端子に対応
して、裏面の前記絶縁樹脂膜上に導体パッドを形成する
工程と、 前記電極端子および導体パッドの形成位置に、前記半導
体素子基板の表裏を貫通する第1の貫通孔を形成する工
程と、 前記第1の貫通孔内に絶縁性樹脂を充填する工程と、 前記絶縁性樹脂の充填層を厚さ方向に貫通して、第2の
貫通孔を形成する工程と、 前記第2の貫通孔内に導電性材料を充填する工程と、 前記導電性材料の充填層と前記電極端子および導体パッ
ドを、直接または他の導電層を介して接続する工程とを
備えたことを特徴とする半導体装置の製造方法。5. A step of forming a surface protection film and an insulating resin film on a front surface and a back surface, which are semiconductor element surfaces of a semiconductor element substrate, respectively, and corresponding to electrode terminals formed on the surface of the semiconductor element substrate. Forming a conductor pad on the insulating resin film on the back surface; forming a first through hole penetrating the front and back of the semiconductor element substrate at a position where the electrode terminal and the conductor pad are formed; Filling an insulating resin into the through-hole, forming a second through-hole by penetrating the filling layer of the insulating resin in a thickness direction, and forming a conductive film in the second through-hole. A method of filling a conductive material, and a step of connecting the filled layer of the conductive material with the electrode terminals and the conductive pads directly or through another conductive layer. .
面および裏面に、表面保護膜および絶縁樹脂膜をそれぞ
れ形成する工程と、 前記半導体素子基板の表面に形成された電極端子に対応
して、裏面の前記絶縁樹脂膜上に導体パッドを形成する
工程と、 前記電極端子および導体パッドの形成位置に、レーザー
光の照射により、前記半導体素子基板の表裏を貫通する
第1の貫通孔を形成すると同時に、形成された貫通孔の
内周面を熱酸化して絶縁性の酸化物層を形成する工程
と、 内周面に前記酸化物層が形成された前記第1の貫通孔内
に、導電性材料を充填する工程と、 前記導電性材料の充填層と前記電極端子および導体パッ
ドを、直接または他の導電層を介して接続する工程とを
備えたことを特徴とする半導体装置の製造方法。6. A step of forming a surface protection film and an insulating resin film on a front surface and a back surface, respectively, which are semiconductor element surfaces of the semiconductor element substrate, and corresponding to electrode terminals formed on the surface of the semiconductor element substrate. Forming a conductive pad on the insulating resin film on the back surface, and forming a first through hole penetrating the front and back of the semiconductor element substrate by irradiating a laser beam at a position where the electrode terminal and the conductive pad are formed. At the same time, a step of thermally oxidizing an inner peripheral surface of the formed through hole to form an insulating oxide layer; and forming a conductive layer in the first through hole having the oxide layer formed on the inner peripheral surface. A method of filling a conductive material, and a step of connecting the filled layer of the conductive material with the electrode terminals and the conductive pads directly or through another conductive layer. .
面および裏面に、表面保護膜および絶縁樹脂膜をそれぞ
れ形成する工程と、 前記半導体素子基板の表面に形成された電極端子に対応
して、裏面の前記絶縁樹脂膜上に導体パッドを形成する
工程と、 前記電極端子および導体パッドの形成位置に、前記半導
体素子基板の表裏を貫通する第1の貫通孔を形成する工
程と、 前記第1の貫通孔内に絶縁性樹脂を充填する工程と、 前記第1の貫通孔内に前記絶縁性樹脂の充填層が形成さ
れた構造体の複数個を、前記第1の貫通孔の位置が一致
するように重ね、各構造体の当接面を接着剤により接着
する工程と、 前記接着工程で得られた積層構造体において、前記絶縁
性樹脂の充填層を厚さ方向全体に亘って貫通する第2の
貫通孔を形成する工程と、 前記第2の貫通孔内に導電性材料を充填する工程と、 前記導電性材料の充填層と、前記積層構造体の最上面お
よび最下面にそれぞれ配置された前記電極端子または導
体パッドを、直接または他の導電層を介して接続する工
程とを備えたことを特徴とする半導体モジュールの製造
方法。7. A step of forming a surface protection film and an insulating resin film on a front surface and a back surface, respectively, which are semiconductor element surfaces of a semiconductor element substrate, and corresponding to electrode terminals formed on the surface of the semiconductor element substrate, Forming a conductor pad on the insulating resin film on the back surface; forming a first through hole penetrating the front and back of the semiconductor element substrate at a position where the electrode terminal and the conductor pad are formed; Filling the insulating resin into the through-hole, and aligning the plurality of structures having the insulating resin-filled layer formed in the first through-hole with the position of the first through-hole. And bonding the contact surfaces of the respective structures with an adhesive, and penetrating the filled layer of the insulating resin over the entire thickness direction in the laminated structure obtained in the bonding process. Forming a second through hole; A step of filling the second through-hole with a conductive material, a filling layer of the conductive material, and the electrode terminals or the conductive pads respectively arranged on the uppermost surface and the lowermost surface of the laminated structure, Or a step of connecting via another conductive layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11118294A JP2000311982A (en) | 1999-04-26 | 1999-04-26 | Semiconductor device, semiconductor module and method of manufacturing them |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11118294A JP2000311982A (en) | 1999-04-26 | 1999-04-26 | Semiconductor device, semiconductor module and method of manufacturing them |
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Publication Number | Publication Date |
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JP2000311982A true JP2000311982A (en) | 2000-11-07 |
Family
ID=14733126
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JP11118294A Abandoned JP2000311982A (en) | 1999-04-26 | 1999-04-26 | Semiconductor device, semiconductor module and method of manufacturing them |
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