JP2016062951A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which achieves low cost by improving efficiency of a process of forming a through electrode.SOLUTION: A semiconductor device manufacturing method comprises: a process of preparing a base substrate to be a base which is a semiconductor substrate having a plurality of semiconductor chips, and preparing a plurality of lamination substrates which are semiconductor substrates having a plurality of semiconductor chips and laminated on the base substrate, and selectively forming electrode pads on each lamination substrate; a process of making a substrate laminate in which the plurality of lamination substrates each of which is thinned on a back face side are laminated so as to face principal surfaces in the same direction; a process of laminating the substrate laminate on a principal surface of the base substrate in a manner such that principal surfaces of the lamination substrates face the same direction with the principal surface of the base substrate; a process of forming via holes which pierce the substrate laminate; and a process of forming a through electrode in each via hole and electrically connecting the selectively formed electrode pads and the through electrodes.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, semiconductor application products have been rapidly reduced in size, thickness and weight for various mobile devices such as smartphones. Along with this, semiconductor devices mounted on semiconductor application products are also required to be downsized and densified. Therefore, in order to meet the demand, for example, a wafer-on-wafer (hereinafter referred to as WOW) in which a plurality of semiconductor substrates (wafers) on which a plurality of semiconductor chips are formed are stacked in a semiconductor substrate (wafer) state via an adhesive layer. A method of manufacturing a semiconductor device having a structure has been proposed.

  In WOW, for example, a through-hole is formed each time a semiconductor substrate is stacked, a through-electrode is formed by filling the through-hole with a metal, and is electrically connected to a lower semiconductor substrate. Thereafter, a semiconductor substrate is further laminated, and is electrically connected to the lower semiconductor substrate by the same method. By repeating this, a plurality of semiconductor substrates are stacked.

JP 2008-153499 A

  However, the process of forming a through-hole each time a semiconductor substrate is stacked and filling the through-hole with a metal to form a through-electrode has many man-hours, which increases the manufacturing cost of the semiconductor device.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the cost by improving the efficiency of the process of forming the through electrode.

  In this method of manufacturing a semiconductor device, a plurality of semiconductor substrates on which a plurality of semiconductor chips are formed are stacked, semiconductor chips of different layers are connected so as to be able to transmit signals, and a portion where the semiconductor chips are stacked is separated into pieces. A method for manufacturing a semiconductor device, which is a semiconductor substrate having a plurality of semiconductor chips and serving as a base, and a plurality of stacked substrates that are semiconductor substrates having a plurality of semiconductor chips and are stacked on the base substrate. And a step of selectively forming electrode pads on each of the laminated substrates, and a substrate laminate in which a plurality of laminated substrates whose back sides are thinned are laminated with their main surfaces facing each other in the same direction Stacking the substrate laminate on the main surface of the base substrate with the main surface of each of the multilayer substrates facing the same direction as the main surface of the base substrate; and Penetrating through Forming a hole, the forming the through electrode in the via holes may be a requirement that has a step of conducting a selectively formed the electrode pads and the through-electrode.

  According to the disclosed technology, it is possible to provide a method of manufacturing a semiconductor device that can reduce the cost by increasing the efficiency of the process of forming the through electrode.

1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. FIG. 2 is a partial enlarged cross-sectional view illustrating only the periphery of a through electrode in FIG. 1. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a second diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 7 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 8) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 9 is a diagram (No. 9) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 10) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 11 is a diagram (No. 11) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 14 is a view (No. 12) illustrating the manufacturing process of the semiconductor device according to the first embodiment; It is a figure explaining the method of electrically isolate | separating arbitrary electrode pads and penetration electrodes. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment; FIG. FIG. 17 is a partial enlarged cross-sectional view illustrating only the periphery of the through electrode in FIG. 16. FIG. 10 is a diagram (part 1) illustrating a manufacturing process of a semiconductor device according to the second embodiment; FIG. 10 is a second diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 11 is a first diagram illustrating a manufacturing process of a semiconductor device according to a third embodiment; FIG. 10 is a second diagram illustrating a manufacturing process of the semiconductor device according to the third embodiment;

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

<First Embodiment>
[Structure of Semiconductor Device According to First Embodiment]
First, the structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 2 is a partially enlarged cross-sectional view illustrating only the periphery of the through electrode in FIG. In FIG. 1 and FIG. 2, the dimensional ratio of each part is appropriately changed for convenience. In FIG. 1, for convenience, a part of the portion shown in FIG. 2 is omitted.

  Referring to FIGS. 1 and 2, in the semiconductor device 10 according to the first embodiment, a plurality of semiconductor chips 110 are stacked with their main surfaces facing in the same direction, and semiconductor chips 110 of different layers are formed as through electrodes. 20 is connected to be able to transmit a signal. Each semiconductor chip 110 includes a substrate body 12, a semiconductor integrated circuit 13, an insulating layer 14, and an electrode pad 15.

  In the semiconductor chip 110, the surface on which the semiconductor integrated circuit 13 is provided may be referred to as a main surface. Further, the surface opposite to the main surface may be referred to as the back surface. Further, the planar view indicates that the object is viewed from the normal direction of the main surface of the semiconductor chip 110, and the planar shape indicates the shape of the object viewed from the normal direction of the main surface of the semiconductor chip 110. And

In each semiconductor chip 110, the substrate body 12 is made of, for example, silicon, gallium nitride, silicon carbide, or the like. In the semiconductor integrated circuit 13, for example, a diffusion layer (not shown), an insulating layer (not shown), a via hole (not shown), a wiring layer (not shown), etc. are formed in silicon, gallium nitride, silicon carbide or the like. Provided on one surface side of the substrate body 12. The insulating layer 14 is a layer that insulates the semiconductor integrated circuit 13 and the electrode pad 15 and is made of, for example, Si ₃ N ₄ , SiO ₂ , SiON, or the like.

  The electrode pad 15 is provided on the semiconductor integrated circuit 13 via the insulating layer 14. The electrode pad 15 is electrically connected to a wiring layer (not shown) provided in the semiconductor integrated circuit 13. The electrode pad 15 has a rectangular planar shape, for example, and an opening having a circular planar shape is provided near the center. The opening provided in the electrode pad 15 is a portion through which the through electrode 20 passes.

  As the electrode pad 15, for example, a laminated body in which an Au layer, an Al layer, a Cu layer, or the like is laminated on a Ti layer or a TiN layer can be used. As the electrode pad 15, a laminate in which an Au layer is laminated on a Ni layer, a laminate in which a Pd layer and an Au layer are sequentially laminated on a Ni layer, and a high melting point metal such as Co, Ta, Ti, TiN instead of Ni A layered body in which a Cu layer or an Al layer is stacked on the same layer, a damascene structure wiring, or the like may be used. The pitch of the electrode pads 15 can be about 5 to 20 μm, for example.

  Whether or not the electrode pad 15 is formed in each semiconductor chip 110 can be arbitrarily determined according to the specification. Thereby, each penetration electrode 20 can be connected only to the desired semiconductor chip 110 in the laminated semiconductor chips 110. For example, the same signal can be passed through the third-layer semiconductor chip 110 and supplied to the fourth-layer semiconductor chip 110 and the second-layer semiconductor chip 110, or different signals can be supplied to the semiconductor chip 110 of each layer.

In addition, an insulating layer (barrier layer) made of, for example, Si ₃ N ₄ , SiO ₂ , SiON or the like and having a thickness of about 0.1 μm to 2.0 μm is formed on the back surface of the substrate body 12 of each semiconductor chip 110. be able to. By forming an insulating layer (barrier layer) on the back side of the substrate body 12, it is possible to reduce the possibility that the semiconductor chip 110 is contaminated with metal impurities from the back side, and to insulate the semiconductor chip 110 from the lower layer.

The semiconductor chips 110 that are vertically adjacent to each other are directly bonded without using an adhesive layer or the like. Each semiconductor chip 110 excluding the lowermost layer is formed with a via hole 21 (through hole) that penetrates each semiconductor chip 110 excluding the lowermost layer and exposes the upper surface of the electrode pad 15 of the semiconductor chip 110 serving as a base. An insulating layer 22 made of, for example, Si ₃ N ₄ , SiO ₂ , SiON or the like is formed on the inner wall (side wall) of the via hole 21.

The electrode pads 15 of each semiconductor chip 110 are electrically connected via a through electrode 20 made of Cu or the like formed in the via hole 21. The through electrode 20 is integrally formed in the via hole 21. The upper end portion of the through electrode 20 protrudes from the upper surface of the electrode pad 15 of the uppermost semiconductor chip 110 (this portion is referred to as a protruding portion of the through electrode 20). An insulating layer 23 is formed around the protruding portion of the through electrode 20. For example, the upper surface of the protruding portion of the through electrode 20 and the upper surface of the insulating layer 23 can be flush with each other. As the material of the insulating layer 23, for example, Si ₃ N ₄ , SiO ₂ , SiON, or the like can be used.

  The through electrode 20 includes, for example, a metal layer 24 that continuously covers the inner wall of the via hole 21 and the inner wall of the insulating layer 23, and a metal layer 25 filled inside the metal layer 24 in the via hole 21 and the insulating layer 23. Can be configured. For example, the upper surface of the through electrode 20 (the upper end surface of the metal layer 24 and the upper surface of the metal layer 25) and the upper surface of the insulating layer 23 can be flush with each other.

  The planar shape of the portion of the through electrode 20 exposed from the insulating layer 23 can be a circular shape having a diameter of about 1 μm to 30 μm, for example. The portion of the through electrode 20 exposed from the insulating layer 23 serves as an external connection pad used for connecting the semiconductor device 10 to another semiconductor device, a wiring board, or the like. A solder bump or the like may be formed on the portion of the through electrode 20 exposed from the insulating layer 23.

[Manufacturing Process of Semiconductor Device According to First Embodiment]
Next, a manufacturing process of the semiconductor device according to the first embodiment will be described. 3 to 14 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. In addition, in order to distinguish the semiconductor substrate 11 of each layer, the semiconductor substrate 11 of each layer is displayed as the semiconductor substrate 11n (n is a natural number which shows what layer is laminated | stacked) for convenience. For example, the semiconductor substrate 11 ₁ denotes a semiconductor substrate 11 of the first layer functioning as a base, the semiconductor substrate _{11. 2} shows a semiconductor substrate 11 of the second layer laminated on the semiconductor substrate 11 _1. The same applies to the substrate body 12, the semiconductor integrated circuit 13, the insulating layer 14, and the electrode pad 15.

First, in the step shown in FIG. 3A, an unthinned semiconductor substrate 11 ₄ (wafer) on which a plurality of semiconductor chips 110 are formed is prepared. Semiconductor substrate 11 ₄ is, for example, a circular shape, a diameter of, for example 6 inches (about 150 mm), 8 inches (about 200 mm), is 12 inches (about 300 mm) or the like. The thickness of the semiconductor substrate _{11. 4,} for example (if a 6-inch) 0.625 mm, (if 8-inch) 0.725 mm, (if 12-inch) 0.775 mm, and the like. Semiconductor substrate 11 ₄ includes a substrate main body 12 _4, the semiconductor integrated circuit 13 _4, and the insulating layer 14 _4, the electrode pads 15 _4. The planar shape of the electrode pad 15 ₄ are for example rectangular, for example a planar shape in the vicinity of the central portion is provided with a circular opening 15x _4. The opening 15x _4, for example, the insulating layer 14 ₄ is formed.

  C indicates a position (hereinafter referred to as “cutting position C”) where a semiconductor substrate on which a plurality of dicing blades or the like are stacked is cut into pieces (refer to a process shown in FIG. 14B described later). . That is, each region separated by the cutting position C is a chip region that is finally separated into one semiconductor chip 110 (see FIG. 1). The vicinity of the cutting position C is a scribe area.

Next, in the step shown in FIG. 3B, a support 510 is prepared. As the support 510, a silicon or quartz glass substrate that can be easily removed by grinding can be used. Then, it turned upside down and removed using grinder unnecessary portions of the outer edge portion of the semiconductor substrate 11 ₄ shown in FIG. 3 (a), joined in a face-down state on one surface of the support 510.

The bonding between the support 510 and the semiconductor substrate _{11. 4,} for example, surface activated bonding: can be used (SAB Surface Activated Bonding). Specifically, for example, it is smoothed by polishing each bonding surface of the support 510 and the semiconductor substrate 11 _4. Then, for example, with an inert gas such as argon gas in a vacuum atmosphere, each bonding surface of the support 510 and the semiconductor substrate 11 ₄ to sputter etching by ion beam or plasma or the like. Thus, in each bonding surface to be bonded of the substrate 510 and the semiconductor substrate 11 ₄ is removed surface layer hinders bonding, bonding strength between state atoms having a bond is exposed (the other atoms are Large active state). Then, by applying arranged to pressure as the bonding surface of the surface layer is removed the support 510 and the semiconductor substrate 11 ₄ are in contact, it is possible to obtain a strong bond at room temperature.

However, the bonding between the support 510 and the semiconductor substrate 11 ₄ is not limited to the surface activated bonding, for example, a support 510 and the semiconductor substrate 11 ₄ may be bonded via an adhesive layer. The same applies to bonding between semiconductor substrates described later. In addition, it is preferable to use a surface activated bonding if the flatness (unevenness) in the entire region of the semiconductor substrate is 1 nm or more and less than 10 nm, and an adhesive layer if it is 10 nm or more and less than 1000 nm.

  When the adhesive layer is used, as a material for the adhesive layer, for example, a thermosetting insulating resin whose main composition is benzocyclobutene (for example, divinylsiloxane benzocyclobutene: DVS-BCB) can be used. In addition, as a material for the adhesive layer, a thermosetting insulating resin whose main composition is an epoxy resin, an acrylic resin, a polyimide resin, and an insulating composite material added with solid fine powder such as silica are used. It doesn't matter. Further, a material containing silicon such as siloxane may be used as the material of the adhesive layer.

In the case of using an adhesive layer, before the adhesive layer is formed or applied, the surface to be bonded is cleaned as necessary, and the surface modification is performed so that the chemical affinity of the surface to be bonded is high and uniform. preferable. Here, high and uniform chemical affinity means that a material having an electron donating property such as a hydroxyl group is produced at a density of 1e12 to 1e13 / cm ² .

  When an adhesive layer is used, a photosensitive adhesive (for example, divinylsiloxane benzocyclobutene: DVS-BCB) is used as the adhesive layer, and an opening is previously formed at a position corresponding to the through electrode 20 of the adhesive layer. It is preferable to join the semiconductor substrates together. If a non-photosensitive adhesive is used as the adhesive layer, etching using an oxygen-based gas is required to remove it, but in etching using an oxygen-based gas, an electrode pad connected to the through electrode The surface of the electrode may be oxidized, and the through electrode and the electrode pad may cause poor conduction. By using a photosensitive adhesive as the adhesive layer, and forming the opening portion at a position corresponding to the through electrode 20 of the adhesive layer in advance and bonding the semiconductor substrates to each other, etching using an oxygen-based gas becomes unnecessary, Such a problem can be avoided.

Next, in a step shown in FIG. 4 (a), a part of the semiconductor substrate 11 ₄ of the rear side of the substrate main body 12 ₄ ground by a grinder or the like to thin the semiconductor substrate 11 _4. Incidentally, the back surface of the substrate main body 12 ₄ after grinding, for example, _Si 3 _{N 4,} made of SiO 2, SiON or the like, a thickness of about 0.1μm~2.0μm insulating layer (barrier layer), for example, a plasma CVD It can be formed by a method or the like.

The semiconductor substrate 11 thickness of ₄ after thinning, for example, may be about 2Myuemu～100myuemu, preferably at 50μm or less, more preferably about 3Myuemu～10myuemu. This is because when the substrate volume is reduced, the processing time of the through electrode (TSV) is significantly shortened, and the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved. If the semiconductor integrated circuit 13 remains, the entire substrate body 12 may be removed by grinding.

Next, in a step shown in FIG. 4 (b), a semiconductor substrate 11 ₃ which is not the same thinning and FIG 3 (a). The semiconductor substrate 11 ₃ includes a substrate body 12 ₃ , a semiconductor integrated circuit 13 ₃ , an insulating layer 14 _3, and an electrode pad 15 ₃ . The electrode pad 15 _3, in a plan view, a position that overlaps with the electrode pads 15 ₄ are selectively formed (through electrode 20 is a region that penetrates). Whether forming the electrode pads 15 ₃ to a predetermined position can be determined arbitrarily according to the specifications. The planar shape of the electrode pads 15 ₃ is, for example, a rectangular shape, for example planar shape in the vicinity of the central portion is provided with a circular opening 15x _3. The opening 15x _3, for example, the insulating layer 14 ₃ is formed. The opening area of the opening 15x ₃ is smaller than the opening area of the opening 15x _4.

Then, joining main surface side of the semiconductor substrate 11 ₃ was prepared by surface activated bonding or the like on the back side of the semiconductor substrate 11 _4. The positioning of the semiconductor substrate 11 ₃ and the semiconductor substrate 11 ₄ may be carried out in a known manner with respect to the alignment marks formed in advance. The alignment accuracy can be set to 2 μm or less, for example.

Next, in a step shown in FIG. 5 (a), in the same manner as in the step of FIG. 4 (a), the semiconductor substrate 11 by a portion of the semiconductor substrate 11 ₃ of the rear side of the substrate main body 12 ₃ is ground by a grinder or the like ₃ is thinned. An insulating layer (barrier layer) made of, for example, Si ₃ N ₄ , SiO ₂ , SiON or the like and having a thickness of about 0.1 μm to 2.0 μm is formed on the back surface of the ground substrate body 12 ₃ by, for example, plasma CVD. It can be formed by a method or the like. The semiconductor substrate 11 thickness of ₃ after thinning may be the thickness of the same order of the semiconductor substrate 11 ₄ after thinning.

Next, in a step shown in FIG. 5 (b), a semiconductor substrate 11 ₂ which is not the same thinning and FIG 3 (a). The semiconductor substrate 11 ₂ includes a substrate main body 12 _2, the semiconductor integrated circuit 13 _2, and the insulating layer 14 _2, the electrode pads 15 _2. The electrode pads 15 _2, in a plan view, a position that overlaps with the electrode pads 15 ₄ and 15 ₃ is selectively formed (through electrode 20 is a region that penetrates). Whether to form the electrode pads 15 ₂ at a predetermined position can be determined arbitrarily according to the specifications. The planar shape of the electrode pads 15 ₂ is, for example, a rectangular shape, is for example a planar shape in the vicinity of the central portion is provided with a circular opening 15x _2. The opening 15x _2, for example, the insulating layer 14 ₂ is formed. The opening area of the opening portion 15x ₂ is smaller than the opening area of the opening 15x _3.

Then, joining main surface side of the semiconductor substrate 11 ₂ was prepared by surface activated bonding or the like on the back side of the semiconductor substrate 11 _3. The positioning of the semiconductor substrate 11 ₂ and the semiconductor substrate 11 ₃ can be carried out in a known manner with respect to the alignment marks formed in advance. The alignment accuracy can be set to 2 μm or less, for example.

Then, in the same manner as in the step of FIG. 4 (a), a portion of the semiconductor substrate 11 ₂ of the rear side of the substrate main body 12 ₂ by grinding with a grinder or the like to thin the semiconductor substrate 11 _2. Note that an insulating layer (barrier layer) made of, for example, Si ₃ N ₄ , SiO ₂ , SiON or the like and having a thickness of about 0.1 μm to 2.0 μm is formed on the back surface of the ground substrate body 12 ₂ by, for example, plasma CVD. It can be formed by a method or the like. The semiconductor thickness of the substrate 11 ₂ after thinning may be the thickness of the same order of the semiconductor substrate 11 ₄ after thinning. Thereby, a substrate laminate in which a plurality of semiconductor substrates 11 whose back sides are thinned is laminated with their main surfaces facing each other in the same direction is manufactured.

Next, in a step shown in FIG. 6 (a), in the same manner as in the step of FIG. 4 (b), to prepare the semiconductor substrate 11 ₁ serving as a base substrate, the surface activating main surface side of the semiconductor substrate 11 ₁ bonded to the back side of the semiconductor substrate 11 ₂ by such bonding. Next, in the step shown in FIG. 6B, the support 510 shown in FIG. 6A is removed by grinding with a grinder or the like. Accordingly, on the semiconductor substrate 11 ₁ serving as a base substrate, the substrate laminate (semiconductor substrate 11 _2, the semiconductor substrate 11 ₃ and laminate semiconductor substrate 11 ₄ are sequentially stacked) is formed. In other words, toward the main surface of the semiconductor substrate respectively on the main surface in the same direction of the semiconductor substrate 11 ₁ serving as a base substrate, the substrate laminate is laminated on the main surface of the semiconductor substrate 11 ₁ serving as a base substrate. The semiconductor substrate 11 ₁ and the substrate laminate shown in FIG. 6 (b) is shown in a state of being turned upside down from that of FIG. 6 (a).

Next, in a step shown in FIG. 7 (a), the semiconductor substrate 11 _2, then through the semiconductor substrate 11 ₃ and the semiconductor substrate 11 _4, a via hole 21 exposing the electrode pads 15 ₁ of the upper surface of the semiconductor substrate 11 ₁ (through hole ). Then, in the step shown in FIG. 7 (b), an insulating layer 23 to expose the holes 21 in the main surface of the semiconductor substrate 11 _4, further penetrating electrodes 20 to fill the openings and the via holes 21 of the insulating layer 23 Form. The electrode pads that are in contact with the through electrode 20 are electrically connected to each other.

  Here, the detail of the process shown to Fig.7 (a) and FIG.7 (b) is demonstrated using FIGS. 8-13. For convenience of explanation, in FIGS. 8 to 13, only a part of the structure (near the electrode pad 15) shown in FIGS. 7A and 7B is enlarged and shown.

In the step shown in FIG. 8, the semiconductor substrate 11 _2, then through the semiconductor substrate 11 ₃ and the semiconductor substrate 11 _4, to form a via hole 21 (through holes) exposing the electrode pads 15 ₁ of the upper surface of the semiconductor substrate 11 ₁ . More specifically, in order to form a via hole 21 to a desired position to form a resist film 520 is patterned on the insulating layer 14 _4. Resist film 520 is exposed inside the insulating layer 14 _fourth opening portion 15x _4, patterned so as to cover the outer insulating layer 14 _fourth electrode pads 15 _4. That is, the sidewall of the opening of the resist film 520 is positioned on the electrode pads 15 _4.

Then, the resist film 520 as a mask, etching each of the semiconductor substrate or the like to the electrode pads 15 ₁ of the upper surface of the semiconductor substrate 11 ₁ is exposed (e.g., plasma etching using a fluorine-based gas) to. Thereafter, the resist film 520 is removed and further washed.

  The opening area of the electrode pad opening of the semiconductor substrate stacked on the side close to the base substrate is smaller than the opening area of the electrode pad opening of the semiconductor substrate stacked on the side far from the base substrate. Yes. Therefore, in the step of forming the via hole 21, the semiconductor substrate exposed in the opening of the electrode pad is removed by etching using the respective electrode pads as a mask, and the via holes 21 are formed in a lump.

  For example, a via hole 21 having a stepped cross section is formed as shown in FIG. However, FIG. 8 shows the vicinity of the rightmost via hole in the region sandwiched by the broken line C in FIG. 7A, but other via holes in the region sandwiched by the broken line C in FIG. As described above, a step-like via hole is not formed in a portion where the electrode pad is not formed.

Then, in the process shown in FIG. 9, inside the via hole 21, forming an insulating layer 22 on the electrode pads 15 ₄ and the insulating layer 14 _4. The thickness of the insulating layer 22 on the side wall of the via hole 21 can be about 50 to 100 nm, for example. Next, in the step shown in FIG. 10, the insulating layer 22 formed other than the sidewall of the via hole 21 is removed by, for example, RIE (Reactive Ion Etching). Accordingly, in the via hole 21, the semiconductor substrate 11 _2, the side walls of the semiconductor substrate 11 ₃ and the semiconductor substrate 11 ₄ is covered with an insulating layer 22, the electrode pads 15 _1, the upper surface of the electrode pads 15 ₂ and the electrode pads 15 ₃ parts Exposed. Moreover, the entire upper surface of the electrode pad 15 ₄ is exposed.

For example, if the planar shape of the openings 15x ₄ , 15x ₃ and 15x _{2 is} a circular shape whose diameter decreases stepwise, the upper end of the insulating layer 22 of each semiconductor substrate is a substantially concentric circle from the inside in plan view. It is arranged in a ring. Also, in a plan view, a circular electrode pad 15 ₁ , an annular electrode pad 15 ₂ , an annular electrode pad 15 _3, and an annular electrode pad 15 _{4 that} are separated from each other by the insulating layers 22 from the inside are disposed. .

The circular electrode pad 15 ₁ , the annular electrode pad 15 ₂ , the annular electrode pad 15 _3, and the annular electrode pad 15 ₄ that are not covered with the insulating layer 22 finally come into contact with the metal layers 24 and 25. It becomes a part to conduct. Therefore, in order to make the resistance value of the conducting portion uniform, the circular electrode pad 15 ₁ , the annular electrode pad 15 _2, and the annular electrode pad 15 ₃ that are not covered with the insulating layer 22 have substantially the same area. It is preferable that The same applies to the area of the electrode pads 15 ₄ of the portion exposed to the annular insulating layer 23 in FIG. 11 to be described later.

Next, in a step shown in FIG. 11, on the electrode pads 15 ₄ and the insulating layer 14 _4, the inner edge of the upper surface of the electrode pad 15 ₄ cyclic (e.g., annular) to form the insulating layer 23 exposed to. Then, inside the via hole 21, the electrode pads 15 ₄ on, and on the insulating layer 23, a metal such as Cu is deposited by 200nm~500nm about sputtering or the like to form a metal layer 24 serving as a power feeding layer. Note that a barrier layer may be formed by forming a metal such as Ti / TiN, Ta or the like under the metal layer 24 by a sputtering method or the like with a thickness of about 50 to 100 nm.

  Next, in the process shown in FIG. 12, a metal such as Cu is filled in the via hole 21 by an electrolytic plating method using the metal layer 24 as a power feeding layer, and the metal layer 25 protruding from the upper surface of the insulating layer 23 is formed. Next, in the step shown in FIG. 13, portions of the metal layers 24 and 25 protruding from the upper surface of the insulating layer 23 are removed by CMP or the like, and the metal layer is formed inside the metal layer 24 in the via hole 21 and the insulating layer 23. A through electrode 20 filled with 25 is prepared. For example, the upper surface of the through electrode 20 (the upper end surface of the metal layer 24 and the upper surface of the metal layer 25) and the upper surface of the insulating layer 23 can be flush with each other.

Next, in a step shown in FIG. 14 (a), optionally, a portion of the back side of the substrate main body 12 ₁ of the semiconductor substrate 11 ₁ is ground by a grinder or the like to thin the semiconductor substrate 11 _1. The semiconductor thickness of the substrate 11 ₁ after thinning is a semiconductor substrate 11 2 _to the semiconductor substrate 11 ₄ after thinning may be comparable, because the semiconductor substrate 11 ₁ is foundation substrate, the semiconductor substrate 11 is a multilayer substrate it may be thicker than ₂ to the semiconductor substrate 11 _4. In addition, the semiconductor substrate 11 ₁ may be not thinned.

  Next, in the step shown in FIG. 14B, the structure shown in FIG. 14A is cut into pieces by cutting at a cutting position C with a dicing blade or the like, so that a plurality of semiconductor devices 10 shown in FIG. Individually produced.

  In this way, after laminating a plurality of semiconductor substrates on a semiconductor substrate that serves as a base, via holes are formed so as to penetrate the laminated semiconductor substrates all at once, a through electrode is formed in the via hole, and an electrode pad of each semiconductor substrate is formed. Can be connected. The number of semiconductor substrates to be stacked may be further increased. Thereby, the manufacturing process can be simplified, and the cost of the manufactured semiconductor device can be reduced.

  In addition, since whether or not to form an electrode pad in each semiconductor substrate is arbitrarily determined according to specifications, each through electrode can be connected only to a desired semiconductor substrate in the stacked semiconductor substrates. For example, the same signal can be passed through the third-layer semiconductor substrate and supplied to the fourth-layer semiconductor substrate or the second-layer semiconductor substrate, or different signals can be supplied to the semiconductor substrates of the respective layers.

  In addition, by making the opening diameter of the upper electrode pad larger than the opening diameter of the lower electrode pad, the area of the contact area between the electrode pad and the metal layer of the through electrode can be increased, thereby enabling reliable contact. In addition, the resistance value of the contact portion can be reduced.

  In the present embodiment, an example in which the electrode pad is not provided in a portion that does not need to be connected when the electrode pads of the semiconductor substrate of each layer are arbitrarily connected is shown (see FIG. 1 and the like). However, the present invention is not limited to this, and the electrode pad may be provided with a separation groove (electrical separation) for insulating from the through electrode.

For example, the electrode pad 15 ₃ shown in FIGS. 15A and 15B is provided with a separation groove 41 penetrating the electrode pad 15 ₃ so as to surround the through electrode 20 in plan view. The separation groove 41 may be filled with an insulating resin. 42 shows a wiring connected to the electrode pads 15 _3. Incidentally, FIG. 15 (a) cross-sectional view, FIG. 15 (b) is a plan view showing only the electrode pads 15 near ₃ in FIG. 15 (a).

By providing the isolation groove 41, the through electrode 20 and the electrode pads 15 ₃ and the wiring 42 are electrically separated. As described above, according to the method of providing the electrode pad also in the portion that does not need to be connected and further providing the separation groove for separating the electrode pad and the through electrode, the electrode pad is provided in the portion that does not need to be connected as shown in FIG. Since the area occupied by the electrode pad is larger than the method in which the electrode pad is not provided, when the insulating layer on the electrode pad is flattened, there is an advantage that the flattening becomes easy.

<Second Embodiment>
In the second embodiment, an example in which the insulating layer 22 is not formed on the inner wall (side wall) of the via hole 21 is shown. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

  FIG. 16 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. 17 is a partially enlarged cross-sectional view illustrating only the periphery of the through electrode of FIG. In FIG. 16 and FIG. 17, for convenience, the dimensional ratio of each part is appropriately changed. In FIG. 16, for convenience, a part of the portion shown in FIG. 17 is omitted.

  16 and 17, the semiconductor device 10A according to the second embodiment is different from the first embodiment in that the insulating layer 14 is replaced with the insulating layer 14A in the semiconductor chip 110 excluding the base. This is different from the semiconductor device 10 (see FIGS. 1 and 2).

Unlike the insulating layer 14 (see FIGS. 1 and 2), the insulating layer 14 </ b> A is also formed around the through-electrode 20 in the substrate body 12 and the semiconductor integrated circuit 13. That is, the insulating layer 14 </ b> A is a layer that insulates the semiconductor integrated circuit 13 and the electrode pad 15, and insulates the substrate body 12 and the semiconductor integrated circuit 13 from the through electrode 20. The insulating layer 14A is made of, for example, Si ₃ N ₄ , SiO ₂ , SiON, or the like, as with the insulating layer 14.

  Note that the portion of the insulating layer 14 </ b> A penetrating below the electrode pad 15 of each semiconductor chip 110 is made larger than the diameter of the largest opening among the openings formed in the electrode pad 15 of each semiconductor chip 110. . In plan view, a portion of the insulating layer 14 </ b> A penetrating below the electrode pad 15 of each semiconductor chip 110 may be made larger than the electrode pad 15.

18 and 19 are diagrams illustrating the manufacturing process of the semiconductor device according to the second embodiment. First, in the process shown in FIG. 18A, as in the process of FIG. 3A, a non-thinned semiconductor substrate 11 ₄ (wafer) on which a plurality of semiconductor chips 110 are formed is prepared. Insulating layer 14A _4, not only the upper surface of the semiconductor integrated circuit 13 _4, a via hole 21 should also be formed in a region to be formed (the insulating layer 14A ₄ of the substrate main body 12 _4, the formation of the semiconductor integrated circuit 13 ₄ Formed before).

Incidentally, the insulating layer 14A _4, an insulating layer formed on the upper surface of the semiconductor integrated circuit 13 _4, with even better (another step not one formed integrally with the insulating layer formed on the substrate main body 12 ₄ formed May be). The insulating layer 14A ₄ is by forming until the remaining portion when it is thinned by a substrate main body 12 ₄ later step may not be formed to the back surface side of the substrate main body 12 _4.

Next, in a step shown in FIG. 18 (b), in the same manner as in the step shown in FIG. 3 (b) and 4 (a), to prepare a support 510, the semiconductor substrate 11 ₄ shown in FIG. 18 (a) Unnecessary portions of the outer edge portion are removed using a grinder or the like and turned upside down, and joined to one surface of the support 510 in a face-down state. Then, a portion of the semiconductor substrate 11 ₄ of the rear side of the substrate main body 12 ₄ ground by a grinder or the like to thin the semiconductor substrate 11 _4. Thus, the insulating layer 14A ₄ is exposed on the back side of the substrate main body 12 _4. Incidentally, the back surface of the substrate main body 12 ₄ after grinding, for example, _Si 3 _{N 4,} made of SiO 2, SiON or the like, a thickness of about 0.1μm~2.0μm insulating layer (barrier layer), for example, a plasma CVD It can be formed by a method or the like.

Then, in the process shown in FIG. 19 (a), in the same manner as in the step of FIG. 4 (b) ~ FIG 7 (a), on the semiconductor substrate 11 ₁ serving as a base substrate, the substrate laminate (semiconductor substrate 11 ₂ a laminate semiconductor substrate 11 ₃ and the semiconductor substrate 11 ₄ are sequentially stacked) to form a. However, the semiconductor substrate 11 ₂ is formed an insulating layer 14A ₂ similar to the insulating layer 14A _4, the semiconductor substrate 11 ₃ is formed an insulating layer 14A ₃ similar to the insulating layer 14A _4. Then, the insulating layer 14A ₂ of the semiconductor substrate 11 _2, via holes penetrating the insulating layer 14A ₄ of the semiconductor substrate 11 _third insulating layer 14A ₃ and the semiconductor substrate 11 _4, to expose the electrode pads 15 ₁ of the upper surface of the semiconductor substrate 11 ₁ 21 (through hole) is formed.

Then, in the process shown in FIG. 19 (b), an insulating layer 23 to expose the holes 21 in the main surface of the semiconductor substrate 11 _4, further penetrating electrode 20 filling the opening and the via hole 21 of the insulating layer 23 Form. The electrode pads that are in contact with the through electrode 20 are electrically connected to each other. The through electrode 20 and each semiconductor substrate are insulated by the insulating layer 14A. Then, FIGS. 14 (a) and 14 in the same manner as steps (b), the semiconductor substrate 11 is ground by a grinder or the like a part of the semiconductor substrate 11 ₁ of the rear side of the substrate main body 12 ₁ optionally ₁ Is cut into pieces by cutting at a cutting position C with a dicing blade or the like, thereby producing a plurality of semiconductor devices 10A shown in FIG.

  As described above, in the second embodiment, the insulating layer 14A of each semiconductor substrate excluding the base substrate is also formed in the region where the via hole 21 in the substrate body 12 and the semiconductor integrated circuit 13 is provided. ), The insulating layer 14A is exposed on the side wall of the via hole 21 of each semiconductor substrate. Therefore, the process of forming and processing the insulating layer 22 as shown in FIGS. 9 and 10 of the first embodiment can be omitted. As a result, the manufacturing process can be further simplified, and the cost of the manufactured semiconductor device can be further reduced. Other effects are the same as those of the first embodiment.

<Third Embodiment>
In the third embodiment, an example of another method (chip-on-wafer: COW) for manufacturing the semiconductor device according to the first embodiment will be described. Note that in the third embodiment, description of the same components as those of the already described embodiments may be omitted.

20 and 21 are diagrams illustrating the manufacturing process of the semiconductor device according to the third embodiment. First, in the process shown in FIG. 20A, the semiconductor substrate 11 ₄ , the semiconductor substrate 11 _3, and the semiconductor substrate 11 ₂ are formed on the support 510 in the same manner as in the processes in FIGS. 3A to 5B. A substrate laminate in which is sequentially laminated is manufactured. Then, the produced substrate laminate is placed on a support film 530 such as a die attach film, cut at a cutting position C, and separated into individual regions where the semiconductor chips 110 are laminated, and a plurality of laminates of the semiconductor chips 110 are formed. Make one.

Next, in a step shown in FIG. 20 (b), laminating the stack of semiconductor chips 110 in a predetermined position of the semiconductor substrate 11 ₁ of the main surface of the base substrate. At this time, it directs the main surface of the laminate of the semiconductor chip 110, the main surface in the same direction of the semiconductor substrate 11 ₁ serving as a base substrate. Specifically, remove the stack of semiconductor chip 110 from the support film 530, the back side of the laminate of the semiconductor chip 110 to a predetermined position on the main surface of the semiconductor substrate 11 ₁ serving as a base substrate by surface activated bonding or the like Join. Electrode pads 15 of the stack of semiconductor chip 110 is bonded after being aligned to come to positions corresponding to the electrode pads 15 ₁ of the semiconductor substrate 11 ₁ serving as a base substrate.

Next, in a step shown in FIG. 21A, a resin layer 30 that covers the side surface of the stacked body of the semiconductor chips 110 is formed. Specifically, for example, the side surface of the stacked body of the semiconductor chips 110 is filled with a resin that becomes the resin layer 30 using a dispenser or the like, and the filled resin is heated to a predetermined temperature and cured. In this case, providing a frame member for defining the shape of the resin layer 30 formed on the outer peripheral side of the semiconductor substrate 11 ₁ may be disposed on the outer peripheral side of the semiconductor substrate 11 _1.

  Next, a plurality of semiconductor devices 10B shown in FIG. 21B are manufactured by performing the same processes as those in FIGS. 7A to 14B. The semiconductor device 10B is different from the semiconductor device 10 shown in FIG. 1 in that the resin layer 30 is formed. However, the semiconductor device 10 shown in FIG. 1 is also made of a resin similar to the semiconductor device shown in FIG. Layer 30 may be formed.

Thus, the semiconductor substrate 11 ₁ on the main surface of the base substrate, bonding the stack of semiconductor chips 110 which is sectioned, then, may be a step of forming a via hole 21 and the through electrode 20. Also in this case, since the via hole that penetrates the stacked body of the semiconductor chips 110 at once is formed and the through electrode is formed in the via hole, the manufacturing process can be simplified as in the first embodiment, and the manufacturing process can be simplified. Cost reduction of the semiconductor device to be realized can be realized.

  In the third embodiment, the insulating layer 14A described in the second embodiment may be used instead of the insulating layer 14. In this case, the manufacturing process can be further simplified, and the cost of the manufactured semiconductor device can be further reduced.

  The preferred embodiment has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and replacements can be added to the above-described embodiment without departing from the scope described in the claims.

For example, in the above embodiment, for convenience, the stacked semiconductor substrates (semiconductor chips) are denoted by the same reference numerals, but the stacked semiconductor substrates (semiconductor chips) may have the same function or different functions. Good. For example, the semiconductor substrate 11 ₁ serving as a foundation and MPU (Micro-Processing Unit), can be each semiconductor substrate 11 to be stacked thereon and DRAM (Dynamic Random Access Memory).

  In the above embodiment, the case where a semiconductor substrate (silicon wafer) having a circular shape in plan view is used has been described as an example. However, the semiconductor substrate is not limited to a circular shape in plan view. You may use.

  Further, instead of a semiconductor substrate having a semiconductor chip, a substrate including a structural layer not having a semiconductor chip may be partially laminated.

  Further, the material of the semiconductor substrate is not limited to silicon, and for example, germanium or sapphire may be used.

10, 10A, 10B Semiconductor device 11 Semiconductor substrate (wafer)
DESCRIPTION OF SYMBOLS 12 Substrate body 13 Semiconductor integrated circuit 14, 14A, 22, 23 Insulating layer 15 Electrode pad 15x Opening 20 Through electrode 21 Via hole 24, 25 Metal layer 30 Resin layer 41 Separation groove 42 Wiring 110 Semiconductor chip 510 Support body 520 Resist film 530 Support film

Claims (8)

A method of manufacturing a semiconductor device in which a plurality of semiconductor substrates on which a plurality of semiconductor chips are formed are stacked, semiconductor chips of different layers are connected so as to be able to transmit signals, and a portion where the semiconductor chips are stacked is separated into pieces. ,
Preparing a base substrate which is a semiconductor substrate having a plurality of semiconductor chips and serves as a base; and a plurality of stacked substrates which are semiconductor substrates having a plurality of semiconductor chips and are stacked on the base substrate. Selectively forming electrode pads on the laminated substrate;
A step of producing a substrate laminate in which a plurality of the laminated substrates whose back sides are thinned are laminated with their main surfaces oriented in the same direction;
A step of laminating the substrate laminate on the main surface of the base substrate with the main surface of each of the multi-layer substrates oriented in the same direction as the main surface of the base substrate;
Forming a via hole penetrating the substrate laminate;
Forming a through electrode in the via hole, and electrically connecting the selectively formed electrode pad and the through electrode.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of selectively forming the electrode pad, an electrode pad having an opening through which the through electrode passes is formed. The opening area of the opening of the electrode pad of the laminated substrate laminated on the side close to the base substrate is larger than the opening area of the opening of the electrode pad of the laminated substrate laminated on the side far from the base substrate. Formed small,
3. The semiconductor device according to claim 2, wherein in the step of forming the via hole, the via hole is formed in a lump by removing the laminated substrate exposed in the opening of the electrode pad by etching using each of the electrode pads as a mask. Manufacturing method.   4. The semiconductor device according to claim 1, wherein, in the step of manufacturing the substrate laminate, the bonding surfaces of the objects to be bonded are activated, and the bonding surfaces are directly bonded in a vacuum atmosphere. Manufacturing method. Before the step of producing the substrate laminate, the step of forming an insulating layer in the region where the via hole of each of the laminate substrates is formed,
5. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the through electrode, the through electrode is formed so that the through electrode and the laminated substrate are insulated by the insulating layer. . A step of forming an insulating layer on an inner wall of the via hole between the step of forming the via hole and the step of forming the through electrode;
5. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the through electrode, the through electrode is formed so that the through electrode and the laminated substrate are insulated by the insulating layer. . The step of producing the substrate laminate is as follows:
Preparing a support, bonding the multilayer substrate to the support with the main surface facing the support, and thinning the back side of the multilayer substrate bonded to the support;
The step of thinning the back side by laminating the other laminated substrate in the same direction on the laminated substrate whose back side is thinned;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the support. Between the step of producing the substrate laminate and the step of laminating the substrate laminate, the substrate laminate has a step of dividing into individual regions where semiconductor chips are laminated,
In the step of laminating the substrate laminate, each of the individual substrate laminates separated into the main surface of the base substrate is directed in the same direction as the main surface of the base substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate laminate is laminated.

Images