JP6360299B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, semiconductor application products have been rapidly reduced in size, thickness and weight for various mobile devices such as smartphones. Along with this, semiconductor devices mounted on semiconductor application products are also required to be downsized and densified. Therefore, in order to meet the demand, for example, a wafer-on-wafer (hereinafter referred to as WOW) in which a plurality of semiconductor substrates (wafers) on which a plurality of semiconductor chips are formed are stacked in a semiconductor substrate (wafer) state via an adhesive layer. A method of manufacturing a semiconductor device having a structure has been proposed. Further, there is a demand for further thinning the stacked semiconductor substrates.

JP 2008-153499 A

  However, if the semiconductor substrate is made thinner, two problems are concerned. The first problem is that the semiconductor substrate is difficult to handle and easily cracked, that is, the bending strength is reduced. The second problem is that it becomes weak against metal contamination from the back surface of the semiconductor substrate, that is, the gettering property is lowered.

  The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a semiconductor device and the like that can ensure bending strength and improve gettering properties.

In this method of manufacturing a semiconductor device, a plurality of semiconductor substrates on which a plurality of semiconductor chips are formed are stacked, semiconductor chips of different layers are connected so as to be able to transmit signals, and a portion where the semiconductor chips are stacked is separated into pieces. A method of manufacturing a semiconductor device, which is a semiconductor substrate having a plurality of semiconductor chips and serving as a base, a semiconductor substrate having a plurality of semiconductor chips and stacked on the base substrate, A step of thinning the back side of the laminated substrate, a step of forming a crystal defect layer on the back side of the thinned laminated substrate, and the crystal defect on the main surface of the base substrate fixing a rear surface of the laminated substrate layer is formed, the turned into the back side of the base substrate thin, having a step of forming a crystal defect layer on the back side of the base substrate which is thinned, wherein the laminate wherein the rear side of the substrate In the step of forming a crystal defect layer, crushed layer is formed on the outside of the thinned thickness direction of the multilayer substrate, the crushing layer thicker strained layer than is formed inside, on the back side of the base substrate The step of forming the crystal defect layer requires that a crushed layer is formed on the outer side of the thinned base substrate in the thickness direction, and a strained layer thicker than the crushed layer is formed on the inner side .

  According to the disclosed technology, it is possible to provide a method for manufacturing a semiconductor device and the like that can ensure bending strength and improve gettering performance.

It is sectional drawing which illustrates the semiconductor device which concerns on this Embodiment. It is a figure which illustrates the relationship between gettering capability and bending strength. It is a figure which shows the example which forms a crystal defect layer partially in the back side of a semiconductor substrate. FIG. 6 is a first diagram illustrating a manufacturing process of a semiconductor device according to the embodiment; FIG. 10 is a second diagram illustrating a manufacturing process of the semiconductor device according to the embodiment; FIG. 10 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor device according to the embodiment; FIG. 10 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor device according to the embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor device according to the embodiment; FIG. 10 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor device according to the embodiment;

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

[Structure of Semiconductor Device According to this Embodiment]
First, the structure of the semiconductor device according to this embodiment will be described. FIG. 1 is a cross-sectional view illustrating a semiconductor device according to this embodiment. FIG. 1B shows an enlarged view of the crystal defect layer 19 shown in FIG. Referring to FIG. 1, in a semiconductor device 10 according to the present embodiment, a plurality of semiconductor chips 110 are stacked with an adhesive layer 16 facing the main surface in the same direction, and semiconductor chips 110 of different layers penetrate each other. The electrodes 17 are connected so as to be able to transmit signals.

  Each semiconductor chip 110 includes a substrate body 12, a semiconductor integrated circuit 13, an electrode pad 15, and a crystal defect layer 19. The substrate body 12 is made of, for example, silicon. The semiconductor integrated circuit 13 is formed by forming a diffusion layer (not shown), an insulating layer (not shown), a via hole (not shown), a wiring layer (not shown), etc. in silicon or the like, for example. It is provided on one surface side of the substrate body 12.

  In the semiconductor chip 110 or the like, the surface on which the semiconductor integrated circuit 13 is provided may be referred to as a main surface. Further, the surface opposite to the main surface may be referred to as the back surface. The planar view refers to viewing the object from the normal direction of the main surface of the semiconductor chip 110 and the like, and the planar shape refers to the shape of the object viewed from the normal direction of the main surface of the semiconductor chip 110 and the like. Shall point to.

  The electrode pad 15 is provided on the semiconductor integrated circuit 13 via an insulating layer (not shown). The electrode pad 15 is electrically connected to a wiring layer (not shown) provided in the semiconductor integrated circuit 13. As the electrode pad 15, for example, a laminated body in which an Au layer is laminated on a Ti layer can be used. As the electrode pad 15, a laminate in which an Au layer is laminated on a Ni layer, a laminate in which a Pd layer and an Au layer are sequentially laminated on a Ni layer, and a high melting point metal such as Co, Ta, Ti, TiN instead of Ni A layered body in which a Cu layer or an Al layer is stacked on the same layer, a damascene structure wiring, or the like may be used.

  The crystal defect layer 19 is a layer for capturing metal impurities formed on the back side of the substrate body 12, and includes a crushed layer 19a and a strained layer 19b. The crushed layer 19a is a layer including an amorphous region, a polycrystalline region, a region where fine cracks are gathered, and the like. The strained layer 19b is a layer with broken crystallinity, that is, a layer whose lattice constant is substantially different from the nominal lattice constant of the material constituting the substrate body 12. In the strained layer 19b, the strain decreases as the depth from the back surface of the substrate body 12 increases, and the strain disappears at a certain depth.

  The thickness of the crush layer 19a can be, for example, about 0.05 μm to several μm. The thickness of the strained layer 19b can be, for example, about several μm to 10 μm. By forming the crystal defect layer 19 on the back side of the substrate body 12, the possibility that the semiconductor chip 110 is contaminated with metal impurities from the back side can be reduced. That is, gettering ability can be improved.

  By the way, as shown in FIG. 2, when the thickness of the crystal defect layer is increased to increase the gettering ability, the bending strength is lowered. On the other hand, when the bending strength is increased, the gettering ability is lowered. Therefore, it is difficult to make both compatible. In the present embodiment, as shown in FIG. 3, the crystal defect layer 19 is formed in a region excluding the outer edge portion on the back side of the substrate body 12.

  Thus, by forming the crystal defect layer 19 partially on the back side of the substrate body 12, the gettering ability can be improved while ensuring the bending strength. In addition, the area | region which forms the crystal defect layer 19 partially may be arbitrary, and is not limited to the area | region except the outer edge part of the back side of the board | substrate body 12. FIG. Further, when the semiconductor chip 110 is relatively thick and it is easy to ensure the bending strength, the crystal defect layer 19 may be formed in the entire region on the back side of the substrate body 12.

  Returning to FIG. 1, the semiconductor chips 110 that are vertically adjacent to each other are bonded together via an adhesive layer 16 that is an insulating layer. Connected. As the material of the adhesive layer 16, for example, a thermosetting insulating resin whose main composition is benzocyclobutene (for example, divinylsiloxane benzocyclobutene: DVS-BCB) can be used. Further, as the material of the adhesive layer 16, a thermosetting insulating resin whose main composition is an epoxy resin, an acrylic resin, a polyimide resin, an insulating composite material to which a solid fine powder such as silica is added, and the like are used. It doesn't matter.

[Manufacturing Process of Semiconductor Device According to this Embodiment]
Next, a manufacturing process of the semiconductor device according to the present embodiment will be described. 4A to 4G are diagrams illustrating a manufacturing process of the semiconductor device according to this embodiment.

  First, in the step shown in FIG. 4A (a), an unthinned semiconductor substrate 11 (wafer) on which a plurality of semiconductor chips 110 are formed is prepared. The semiconductor substrate 11 prepared in the step shown in FIG. 4A (a) is a semiconductor substrate having a plurality of semiconductor chips, and is a stacked substrate that is stacked on a base substrate in the stacked body (semiconductor device 10). The semiconductor substrate 11 is circular, for example, and its diameter is, for example, 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm), or the like. The thickness of the semiconductor substrate 11 is, for example, 0.625 mm (in the case of 6 inches), 0.725 mm (in the case of 8 inches), 0.775 mm (in the case of 12 inches), or the like. The semiconductor substrate 11 includes a substrate body 12, a semiconductor integrated circuit 13, and electrode pads 15.

  C indicates a position where the dicing blade or the like cuts the semiconductor substrate 11 into pieces (hereinafter referred to as “cutting position C”). That is, each region separated by the cutting position C is a chip region that is finally separated into one semiconductor chip 110 (see FIG. 1). The vicinity of the cutting position C is a scribe area.

  Next, in the step shown in FIG. 4A (b), a support 510 is prepared, and an adhesive layer 520 is formed on one surface of the support 510. Then, unnecessary portions of the outer edge portion of the semiconductor substrate 11 shown in FIG. 4A are removed using a grinder or the like and turned upside down, and bonded to one surface of the support 510 in a face-down state via the adhesive layer 520. (Temporarily fixed).

  As the support 510, it is preferable to use a substrate that transmits light during alignment. For example, a quartz glass substrate or the like can be used. As the adhesive layer 520, for example, an adhesive that softens at a heating temperature (an adhesive that softens at about 200 ° C. or lower) in a step shown in FIG. 4C (b) described later can be used. The adhesive layer 520 can be formed on one surface of the support 510 by, for example, spin coating. The adhesive layer 520 may be formed on one surface of the support 510 by using a method of attaching a film adhesive instead of the spin coating method.

  Next, in the step shown in FIG. 4B (a), a part of the substrate body 12 on the back side of the semiconductor substrate 11 is ground with a grinder or the like to thin the semiconductor substrate 11. The thickness of the thinned semiconductor substrate 11 can be, for example, about 2 μm to 100 μm, preferably 50 μm or less, and more preferably about 3 μm to 10 μm. This is because when the substrate volume is reduced, the processing time of the through electrode (TSV) is significantly shortened, and the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved.

  Next, in the step shown in FIG. 4B (b), a crystal defect layer 19 is formed on the back side of the thinned semiconductor substrate 11. Specifically, for example, a photosensitive resist film is formed so as to cover the entire back surface of the semiconductor substrate 11, the resist film is exposed, and then the exposed resist film is developed, whereby the back surface of the semiconductor substrate 11 is developed. A lattice-like resist film that covers the outer edge of each chip region is formed. For example, a lattice-like resist film wider than the scribe region is formed along the scribe region of the semiconductor substrate 11.

  Then, a crystal defect layer 19 is formed by sandblasting on the back side of the semiconductor substrate 11 using the resist film as a mask. In each chip region on the back surface of the semiconductor substrate 11, for example, as shown in FIG. 3, a crystal defect layer 19 is formed in a region excluding the outer edge portion. A region where the crystal defect layer 19 at the outer edge portion in FIG. 3 is not formed corresponds to a region masked with a resist film. As shown in FIG. 1B, the crystal defect layer 19 has a structure in which a crushed layer 19a is formed on the outer side in the thickness direction and a strained layer 19b is formed on the inner side.

  Instead of sandblasting, the crystal defect layer 19 may be formed on the back side of the thinned semiconductor substrate 11 by laser irradiation. For example, an excimer laser or the like can be used to form the crystal defect layer 19. In this case, it is possible to irradiate a laser beam at an arbitrary position by moving the laser irradiation device on the irradiation target (it is possible to draw an arbitrary position), so that a resist film serving as a mask formed in the case of sandblasting Is unnecessary. In other words, for example, the crystal defect layer 19 can be formed by irradiating a region other than the outer edge portion of FIG.

  Further, the crystal defect layer 19 may be formed on the back side of the thinned semiconductor substrate 11 by lapping (lapping). However, since it is difficult to partially form the crystal defect layer 19 with wrapping, it is preferable to form the crystal defect layer 19 over the entire back surface of the thinned semiconductor substrate 11 when using wrapping.

  Next, in the step shown in FIG. 4C (a), a non-thinned semiconductor substrate 11 similar to that shown in FIG. 4A (a) is prepared. The semiconductor substrate 11 prepared in the step shown in FIG. 4C (a) is a semiconductor substrate having a plurality of semiconductor chips and serves as a base substrate that serves as a base in the stacked body. Then, a semi-cured adhesive layer 16 is formed on the main surface of the prepared semiconductor substrate 11. Specifically, for example, after applying, for example, a thermosetting insulating resin on the semiconductor substrate 11 by spin coating, or after applying squeegee treatment, the semiconductor substrate 11 is heated to a predetermined temperature or higher to be in a semi-cured state. The semi-cured adhesive layer 16 is formed on the main surface of the semiconductor substrate 11. The adhesive layer 16 may be formed using a vapor phase growth method instead of the spin coating method, or may be formed using a method of attaching a semi-cured film-like thermosetting insulating resin. It doesn't matter. Note that suitable materials for the adhesive layer 16 are as described above.

Then, in the process shown in FIG. 4C (b), the main surface of the semiconductor substrate 11 ₁ (base substrate) to secure the back surface of the semiconductor substrate 11 ₂ crystal defect layer 19 ₂ is formed (laminated substrate). Specifically, the structure shown in FIG. 4B (b) is turned upside down, temporarily adhered to the semiconductor substrate 11 ₂ to the support 510, the main surface of the semiconductor substrate 11 ₁ serving as a base, an adhesive layer 16 ₁ And laminated in a face-up state. Positioning the semiconductor substrate 11 ₁ and the semiconductor substrate 11 ₂ may be carried out in a known manner with respect to the alignment marks formed in advance. The alignment accuracy can be set to 2 μm or less, for example.

Then, for example, while heating at 250 ° C., and pressed from a direction in the semiconductor substrate 11 ₁ side of the support 510 the structure shown in FIG. 4C (b), crimped and back of the semiconductor substrate 11 ₂ and the adhesive layer 16 ₁ Let Thus, the adhesive layer 16 ₁ is cured, the back side of the semiconductor substrate 11 ₂ is joined to the main surface side of the semiconductor substrate 11 _1. In addition, although heating temperature is good also as 300 degreeC or more, it is desirable to set it as 200 degrees C or less. This is because when a high temperature such as 300 ° C. is used, stress is generated due to a difference in thermal expansion, and peeling or a crack of the semiconductor substrate is caused as the number of stacked layers is increased.

In FIG. 4C (b) (the same applies to the following figures), in order to distinguish the semiconductor substrate 11 of each layer, for convenience, the semiconductor substrate 11 of each layer is shown as a semiconductor substrate 11 _n (where n is stacked). Natural number). For example, the semiconductor substrate 11 ₁ denotes a semiconductor substrate 11 of the first layer functioning as a base, the semiconductor substrate _{11. 2} shows a semiconductor substrate 11 of the second layer laminated on the semiconductor substrate 11 _1. The same applies to the substrate body 12, the semiconductor integrated circuit 13, the electrode pad 15, the adhesive layer 16, and the crystal defect layer 19.

Next, in the step shown in FIG. 4D (a), the support 510 and the adhesive layer 520 shown in FIG. 4C (b) are removed. As described above, as the adhesive layer 520, it is preferable to use an adhesive that softens at a heating temperature in the process shown in FIG. 4C (b) (an adhesive that softens at about 200 ° C. or lower). After bonding the back side of the semiconductor substrate 11 ₂ to the adhesive layer 16 ₁ and cured main surface of the semiconductor substrate 11 _1, because the support 510 can be easily removed. In this case, the step shown in FIG. 4C (b) and the step shown in FIG. 4D (a) are a series of steps.

Then, in the process shown in FIG. 4D (b), the electrode pads 15 and _second semiconductor substrate 11 _first electrode pad 15 ₁ and the semiconductor substrate 11 ₂ are connected via the through electrode 17. Details of the process shown in FIG. 4D (b) will be described with reference to FIGS. 4E and 4F. 4E and 4F, only a part of the structure shown in FIG. 4D (b) (near the electrode pad 15) is shown in an enlarged manner for convenience of explanation.

In the step shown in FIG. 4E (a), to form a photosensitive resist film 530 so as to cover the main surface of the semiconductor substrate 11 _2, exposing the resist film 530, and then developing the resist film 530 exposure process Thus, an opening 530x is formed in the resist film 530. Resist film 530 is formed, for example, by applying a liquid resist to the semiconductor substrate 11 _{and second} major surface. The thickness of the resist film 530 can be about 10 μm, for example. Reference numeral 14 denotes an insulating layer which is not shown in FIGS. 4A (a) to 4D (b). The insulating layer 14 is made of, for example, Si ₃ N ₄ , SiO ₂ , SiON or the like. The thickness of the insulating layer 14 can be set to, for example, about 0.1 μm to 2.0 μm so that electrical insulation from the semiconductor integrated circuit 13 is achieved.

Then, in the process shown in FIG. 4E (b), the resist film 530 is removed by a predetermined portion exposed in the opening portion 530x for example, dry etching or the like as a mask, the electrode pads 15 ₁ on the surface of the semiconductor substrate 11 ₁ An exposed via hole 18 is formed. The via hole 18 has a circular planar shape, for example, and can have a diameter of about 1 μm to 30 μm, for example.

  However, the diameter of the via hole 18 is preferably set to such a value that the aspect ratio (ratio of depth to diameter) is 0.5 or more and 5 or less. By setting the aspect ratio to a value not less than 0.5 and not more than 5, the etching processing speed (throughput) when forming the via hole 18 is improved, and the metal layer described later is easily embedded in the via hole 18. This is because improvement can be realized.

Then, in the process shown in FIG. 4E (c), removing the resist film 530 shown in FIG. 4E (b), to continuously form an insulating film 51 on the via hole 18 and the semiconductor substrate 11 _2. The insulating film 51 can be formed by, for example, a plasma CVD method. As the material of the insulating film 51, for example, Si ₃ N ₄ , SiO ₂ , SiON, or the like can be used. The thickness of the insulating film 51 can be, for example, about 0.1 μm to 2.0 μm.

Next, in the step shown in FIG. 4E (d), the insulating film 51 in a portion excluding the wall surface (side wall) of the via hole 18 is removed. The insulating film 51 can be removed by, for example, RIE (Reactive Ion Etching). This step is a step of removing only a predetermined portion of the insulating film 51 without using a photomask, and is called a self-alignment process. The self-alignment process, a via hole 18 and the electrode pads 15 and _second semiconductor substrate 11 _first electrode pads 15 ₁ and the semiconductor substrate 11 ₂ can be accurately positioned. Further, by using a design in which electrode pads are not partially provided, for example, etching proceeds where there are no electrode pads, and further, via holes of different semiconductor substrates provided in lower layers are etched to form via holes having different depths.

Then, in the process shown in FIG. 4F (a), to form the metal layer 52 on the via hole 18 and the semiconductor substrate 11 _2. The metal layer 52 can be formed by, for example, an electroless plating method. The metal layer 52 may be formed using, for example, a sputtering method, a CVD method, or the like. As the metal layer 52, for example, a laminated body in which a Cu layer is laminated on a Ti layer can be used. As the metal layer 52, for example, a stacked body in which a Cu layer is stacked on a Ta layer may be used. Further, the material to be embedded may be a conductor that satisfies the design criteria, and W, Al, doped polysilicon, a carbon material such as carbon nanotube, or a conductive polymer can be used instead of Cu. If the insulating layer has sufficient insulation, a combination of embedded wirings that do not use a barrier metal layer can be selected.

Then, in the process shown in FIG. 4F (b), by the photosensitive resist film 540 is formed on the semiconductor substrate 11 _2, exposing the resist film 540, and then developing the resist film 540 exposure process, An opening 540x is formed in the resist film 540 to expose the inside of the via hole 18 and its peripheral portion. Then, a metal layer 53 that fills the via hole 18 is formed in the opening 540x. The metal layer 53 can be formed by, for example, an electrolytic plating method using the metal layer 52 as a power feeding layer. As the plating film constituting the metal layer 53, for example, a Cu plating film can be used. The opening 540x has, for example, a circular planar shape, and a diameter of about 1 μm to 30 μm, for example.

  Next, in the step shown in FIG. 4F (c), the resist film 540 is removed, and further, the portion of the metal layer 52 not covered with the metal layer 53 is removed. The metal layer 52 can be removed by wet etching, for example.

Then, in the process shown in FIG. 4F (d), to form the metal layer 54 to cover the outer edge portion and the metal layer 53 of the semiconductor substrate 11 _{and second} electrode pads 15 _2. Metal layer 54, for example, a resist film is formed for opening the outer portion and the metal layer 53 of the semiconductor substrate 11 _{and second} electrode pads 15 _2, the electrode pads 15 ₂ and the metal layer 53 electrolytic plating method using as a power supply layer, the opening It can be formed by depositing and growing a plating film so as to fill the portion. Thereafter, the resist film is removed. As the metal layer 54, for example, a laminated body in which an Au layer is laminated on a Ti layer can be used. As the metal layer 54, for example, a stacked body in which a Pd layer and an Au layer are sequentially stacked on a Ni layer, a layer made of a refractory metal such as Co or Ta is used instead of Ni, and a Cu layer or an Al layer is formed on the same layer. You may use the laminated body etc. which were laminated | stacked.

In this way, the steps shown in FIGS. 4E and 4F, it is formed through electrode 17 with metal layers 52 and 53, and 54, the semiconductor substrate 11 _first electrode pad 15 ₁ and the electrode pads 15 of the semiconductor substrate 11 _{2 2} is connected through the through electrode 17. The process shown in FIGS. 4E and 4F is an example. For example, the through electrode 17 may be formed by a process (damascene process) in which the upper surface of the metal layer filled with the via hole is cut by CMP (Chemical Mechanical Polishing) or the like. Absent.

Next, in the step shown in FIG. 4G (a), a semiconductor substrate is further laminated through an adhesive layer. Specifically, laminated after forming the adhesive layer 16 ₂ on the main surface of the semiconductor substrate 11 _2, in the same manner as in FIG. 4A (a) ~ FIG 4D (a), the semiconductor substrate 11 ₃ on the semiconductor substrate 11 ₂ To do. Then, to connect via the electrode pads 15 ₂ and the semiconductor substrate 11 ₃ of the electrode pads 15 ₃ and the through electrodes 17 of the semiconductor substrate 11 ₂ in the same manner as in FIG. 4D (b). Further, after forming the adhesive layer 16 ₃ on the main surface of the semiconductor substrate 11 _3, as in FIG. 4A (a) ~ FIG 4D (a), stacking the semiconductor substrate 11 ₄ on the semiconductor substrate 11 _3. Then, to connect through the semiconductor substrate 11 ₃ of the electrode pads 15 ₃ and the semiconductor substrate 11 _fourth electrode pads 15 ₄ and the through electrode 17 in the same manner as in FIG. 4D (b). Thereafter, as many semiconductor substrates as necessary are stacked.

Then, in the process shown in FIG. 4G (b), a part of the semiconductor substrate 11 ₁ of the rear side of the substrate main body 12 ₁ is ground by a grinder or the like, the semiconductor substrate 11 ₂ to the semiconductor substrate which are laminated semiconductor substrate 11 ₁ 11 ₄ thinned to the same extent. Then, a crystal defect layer 19 ₁ is formed on the back side of the thinned semiconductor substrate 11 _{1 in} the same manner as in the step shown in FIG. 4B (b). Thereafter, the semiconductor device 10 shown in FIG. 1 is manufactured by cutting into pieces by cutting at a cutting position C with a dicing blade or the like.

  Thus, in this embodiment mode, the gettering ability can be improved by forming the crystal defect layer on the back side of the thinned semiconductor substrate (laminated substrate). This is effective when the semiconductor substrate (laminated substrate) is relatively thick and it is easy to ensure the bending strength.

  In addition, when the semiconductor substrate (laminated substrate) is relatively thin, a crystal defect layer is partially formed on the back side of the thinned semiconductor substrate (laminated substrate), so that the getter strength is ensured while ensuring the bending strength. Ring ability can be improved.

  Further, by using a method such as sandblasting or laser irradiation for forming a partial crystal defect layer, it is possible to improve the gettering ability at a low cost.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

  For example, in the above embodiment, the case where a semiconductor substrate (silicon wafer) having a circular shape in plan view is used has been described as an example. However, the semiconductor substrate is not limited to a circular shape in plan view. You may use.

  Further, instead of a semiconductor substrate having a semiconductor chip, a substrate including a structural layer not having a semiconductor chip may be partially laminated.

  Further, the material of the semiconductor substrate is not limited to silicon, and for example, germanium or sapphire may be used.

  In the above embodiment, the example in which the stacked semiconductor chips are connected to each other by the electrical signal through the metal layer formed in the via hole is shown. It is not limited, For example, you may connect by an optical signal. At this time, an optical waveguide may be formed in the via hole instead of the metal layer.

10 Semiconductor Device 11 Semiconductor Substrate (Wafer)
DESCRIPTION OF SYMBOLS 12 Substrate body 13 Semiconductor integrated circuit 14 Insulating layer 15 Electrode pad 16, 520 Adhesive layer 17 Through electrode 18 Via hole 19 Crystal defect layer 19a Shatter layer 19b Strain layer
51 Insulating film 52, 53, 54 Metal layer 110 Semiconductor chip 510 Support body 530, 540 Resist film 530x, 540x Opening

Claims (9)

A method of manufacturing a semiconductor device in which a plurality of semiconductor substrates on which a plurality of semiconductor chips are formed are stacked, semiconductor chips of different layers are connected so as to be able to transmit signals, and a portion where the semiconductor chips are stacked is separated into pieces. ,
Preparing a base substrate that is a semiconductor substrate having a plurality of semiconductor chips, and a laminated substrate that is a semiconductor substrate having a plurality of semiconductor chips and is stacked on the base substrate;
Thinning the back side of the laminated substrate;
Forming a crystal defect layer on the back side of the thinned laminated substrate;
The back surface of the multilayer substrate on which the crystal defect layer is formed is fixed to the main surface of the base substrate, the back surface side of the base substrate is thinned , and the crystal defect layer is formed on the back surface side of the thinned base substrate. Forming , and
In the step of forming the crystal defect layer on the back side of the multilayer substrate, a crushed layer is formed outside the thinned multilayer substrate in the thickness direction, and a strain layer thicker than the crushed layer is formed inside. In the step of forming the crystal defect layer on the back side of the base substrate, a crushed layer is formed on the outer side in the thickness direction of the thinned base substrate, and a strain layer thicker than the crushed layer is formed on the inner side. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the crystal defect layer, the crystal defect layer is partially formed on a back side of the thinned laminated substrate.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the crystal defect layer, the crystal defect layer is formed by sandblasting on the back side of the thinned laminated substrate.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the crystal defect layer, the crystal defect layer is formed on the back side of the thinned laminated substrate by laser irradiation.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the crystal defect layer, the crystal defect layer is formed by wrapping on the back side of the thinned laminated substrate. The step of thinning the back side of the multilayer substrate, the step of forming the crystal defect layer, and the step of fixing the back surface of the multilayer substrate are:
Preparing a support, temporarily fixing the laminated substrate to the support with the main surface facing the support,
Thinning the back side of the laminated substrate temporarily fixed to the support,
Forming a crystal defect layer on the back side of the thinned laminated substrate temporarily fixed to the support;
The main surface of the base substrate is fixed to the back surface of the multilayer substrate on which the crystal defect layer temporarily fixed to the support is formed,
The method for manufacturing a semiconductor device according to claim 1, comprising a step of removing the support. After the step of fixing the back surface of the laminated substrate,
A step of preparing another laminated substrate that is a semiconductor substrate having a plurality of semiconductor chips and is laminated on the base substrate;
Thinning the back side of the other multilayer substrate;
Forming a crystal defect layer on the back side of the thinned other laminated substrate;
The method for manufacturing a semiconductor device according to claim 1, further comprising: adhering a back surface of the other multilayer substrate on which the crystal defect layer is formed to a main surface of the multilayer substrate. A plurality of semiconductor chips and base substrates laminated with their main surfaces facing in the same direction;
A through electrode connecting the semiconductor chip and the base substrate of each layer, and
A crystal defect layer is formed on the back side of the semiconductor chip and the base substrate of each layer,
The said crystal defect layer is a semiconductor device containing the crushing layer formed in the outer side of the thickness direction of the said semiconductor chip or the said base substrate , and the distortion layer thicker than the said crushing layer formed inside. The semiconductor device according to claim 8, wherein the crystal defect layer is partially formed on a back side of a semiconductor chip of each layer.

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