JP2013115285A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure contact area of a through electrode and wiring regardless of whether the through electrode is covered with an insulating film.SOLUTION: A semiconductor device according to an embodiment comprises: a first semiconductor chip 200; a second semiconductor chip 300 laminated on the first semiconductor chip 200; and a through electrode 120 connecting the first semiconductor chip 200 and the second semiconductor chip 300. The through electrode 120 has a first through electrode part 122 and a second through electrode part 124. The first through electrode part 122 is provided on the second semiconductor chip 300 from a top face of a second insulation film 42 to an upper part of second wiring 32. The second through electrode part 124 is linked to an undersurface of the first through electrode part 122 and provided from the same layer with the second wiring 32 to an upper part of the first wiring 30 of the second semiconductor chip 300. A pore diameter of the first through electrode part 122 is larger than a pore diameter of the second through electrode part 124 when viewed from above.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  With the high integration of semiconductor devices, three-dimensional mounting is being studied. In a three-dimensionally mounted semiconductor device, electrodes are provided so as to penetrate a plurality of semiconductor chips (for example, Patent Document 1). By doing so, a plurality of semiconductor chips can be electrically connected and a large current can flow.

JP 2002-237468 A

  In the technique disclosed in Patent Document 1, the through electrode is in contact with only the side surface of the wiring. In this case, since the contact area between the through electrode and the wiring is small, the contact resistance is increased. For this reason, this inventor acquired the knowledge that there exists room for improvement in order to use the technique currently disclosed by patent document 1 for the usage method which flows a large electric current.

According to the present invention, a first semiconductor chip;
A second semiconductor chip stacked on the first semiconductor chip;
A through electrode connecting the first semiconductor chip and the second semiconductor chip;
Have
The first semiconductor chip includes a first substrate,
A first wiring provided on the first substrate;
A first insulating film provided on the first wiring;
Including
The second semiconductor chip includes a second substrate,
A second wiring provided on the second substrate;
A second insulating film provided on the second wiring;
In the second semiconductor chip, the through electrode includes a first through electrode portion provided from an upper surface of the second insulating film to an upper portion of the second wiring,
A second through-electrode portion connected to the lower surface of the first through-electrode portion and provided from the same layer as the second wiring to the upper portion of the first wiring of the first semiconductor chip;
Including
A semiconductor device is provided in which the hole diameters of the first through-electrode part and the second through-electrode part are larger in plan view when the hole diameter of the first through-electrode is larger.

Furthermore, according to the present invention, a first substrate, a first wiring provided on the first substrate, and a first insulating film provided on the first wiring are provided. A first semiconductor chip, a second substrate, a second wiring provided on the second substrate, and a second insulating film provided on the second wiring. Preparing a semiconductor chip and pasting it in a state of being insulated from each other;
A first hole forming step of etching the second insulating film of the second semiconductor chip to form a first through electrode hole;
A second hole forming step of forming a second through electrode hole by etching from the first through electrode hole to the upper part of the first wiring of the first semiconductor chip;
A through electrode forming step of forming a through electrode by forming a Cu film in the first through electrode hole and the second through electrode hole;
Have
A method of manufacturing a semiconductor device is provided in which the diameters of the first through electrode hole and the second through electrode hole are larger in plan view when the first through electrode hole is larger.

  According to the present invention, the hole diameter of the electrode penetrating the wiring is made smaller than the electrode connected from above. As a result, the contact area between the through electrode and the wiring can be increased, and the contact resistance can be reduced.

It is sectional drawing of the semiconductor device which concerns on this embodiment, (a) is a general view, (b) is an enlarged view of the dotted-line part in (a). It is sectional drawing for demonstrating the 1st hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the 1st hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the 2nd hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the 2nd hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the 2nd hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the 2nd hole formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the penetration electrode formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the penetration electrode formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the penetration electrode formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the penetration electrode formation process in the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating the contact area and electromigration lifetime of a penetration electrode and wiring in the semiconductor device which concerns on this embodiment. It is sectional drawing of the semiconductor device which concerns on this embodiment. It is sectional drawing of the semiconductor device which concerns on this embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the present embodiment, and is an enlarged view of a dotted line portion shown in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device according to the present embodiment, in which (a) is an overall view and (b) is an enlarged view of a dotted line portion in (a).

  As shown in FIG. 1A, the semiconductor device according to the present embodiment includes a first semiconductor chip 200, a second semiconductor chip 300 stacked on the first semiconductor chip 200, and a first semiconductor chip 200. A through electrode 120 that connects the semiconductor chip 200 and the second semiconductor chip 300 is provided. The first semiconductor chip 200 includes a first substrate 10, a first wiring 30 provided on the first substrate 10, a first insulating film 40 provided on the first wiring 30, Is included. The second semiconductor chip 300 includes a second substrate 12, a second wiring 32 on the second substrate 12, and a second insulating film 42 provided on the second wiring 32. Yes. The through electrode 120 has a first through electrode portion 122 and a second through electrode portion 124. The first through electrode portion 122 is provided from the upper surface of the second insulating film 42 to the upper portion of the second wiring 32 in the second semiconductor chip 300. The second through electrode portion 124 is connected to the lower surface of the first through electrode portion 122, and is provided from the same layer as the second wiring 32 to the upper portion of the first wiring 30 of the second semiconductor chip 300. Yes. The hole diameters of the first through electrode part 122 and the second through electrode part 124 are larger in the plan view when the hole diameter of the first through electrode part 122 is larger.

  In the first semiconductor chip 200, a multilayer wiring layer is provided on the substrate 10. A transistor is formed on the substrate 10, and a first wiring 30 is formed in a part of the multilayer wiring layer. In the second semiconductor chip 300, a multilayer wiring layer is provided on the substrate 12. Transistors are formed on the substrate 12, and second wirings 32 are formed in part of the multilayer wiring layer. The first semiconductor chip 200 and the second semiconductor chip 300 are, for example, an LSI in which Logic LSI (IC), FPGA, DRAM, Flash memory, MRAM, ReRAM, and PRAM are mixedly mounted, or an LSI in which these are combined. is there.

  As shown in FIG. 1B, when the difference in the hole diameters of the first through electrode portion 122 and the second through electrode portion 124 in the inner region of the barrier metal film 110 is A, A / 2 is It is preferable that 20 nm or more and A is 40 nm or more. Moreover, it is preferable that the hole diameter of the 2nd penetration electrode part 124 is 1 micrometer or more. Further, the wirings 30, 32, and 34 provided in the semiconductor device according to the present embodiment are, for example, power supply wirings or ground wirings, but may be signal wirings.

  As shown in FIG. 1, the first semiconductor chip 200 and the second semiconductor chip 300 are respectively provided between the first substrate 10 and the first wiring 30 and between the second substrate 12 and the second substrate 30. Between the wirings 32, insulating films 20 and 22 may be provided. For the insulating films 20 and 22, for example, any one of SiO 2, SiN, SiCN, SiON, SiC, or a laminated film thereof is used.

  The first substrate 10, the second substrate 12, and the third substrate 14 are, for example, Si substrates. For the through electrode 120, for example, Cu, Al, W, Ti, TiN, Any of Ta, TaN, Mn, and Co, or an alloy of these metals is used.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 2 and 3 are sectional views for explaining the first hole forming step, FIGS. 4 to 7 are for the second hole forming step, and FIGS. 8 to 11 are sectional views for explaining the through electrode forming step. is there. 2 to 11 are views showing a method of manufacturing the semiconductor device shown in FIG.

  First, the first semiconductor chip 200 and the second semiconductor chip 300 are prepared, and the second semiconductor chip 300 is stacked on the first semiconductor chip 200 (not shown).

  Next, as shown in FIG. 2, a resist 60 is applied on the second insulating film 42, and a resist pattern for obtaining the first through electrode hole 80 is formed by performing exposure and development. Here, the first through electrode hole 80 is a hole in which the first through electrode portion 122 is embedded.

  Next, as shown in FIG. 3, the second insulating film 42 is etched by using the resist 60 as a mask and the second wiring 32 as an etching stopper. In this way, the first through electrode hole 80 is formed.

  Next, as shown in FIG. 4, an insulating film 70 is formed on the side surface of the first through electrode hole 80. This insulating film 70 serves as a mask for etching the second wiring 32.

  Next, as shown in FIG. 5, the second wiring 32 is etched using the insulating film 70 as a mask. Thereby, a pattern for forming the second through electrode hole 90 is formed. Here, the second through electrode hole 90 is a hole in which the second through electrode portion 124 is embedded.

  Next, as shown in FIG. 6, the insulating film 70 is removed.

  Next, as shown in FIG. 7, the upper surface of the first wiring 30 is etched using the second wiring 32 connected to the through electrode 120 as a mask. As a result, the second through electrode hole 90 can be formed. Note that etching may be performed using the insulating film 70 as a mask without removing the above-described insulating film 70.

  Next, as shown in FIG. 8, the insulating film 100 is formed on the surfaces of the first through electrode hole 80 and the second through electrode hole 90. Further, when a Si substrate is used as the first substrate 10 or the second substrate 12, the Si substrate becomes a conductor, and thus the Si substrate and the through electrode 120 may be electrically connected. If the first substrate 10 or the second substrate 12 and the through electrode 120 are connected, the transistor may not function. Therefore, in order to separate the substrate and the through electrode 120, it is better to form the insulating film 100.

  Next, as shown in FIG. 9, etching back is performed so that the insulating film 100 remains only on the side surfaces of the first through electrode hole 80 and the second through electrode hole 90.

  Next, as shown in FIG. 10, a barrier metal film 110 is formed on the upper surface of the second insulating film 42, the surface of the insulating film 100, and the upper surface of the first wiring 10.

  Next, as shown in FIG. 11, copper is deposited in the first through electrode hole 80 and the second through electrode hole 90 by a plating method.

  Next, the through electrode 120 shown in FIG. 1A can be formed by polishing the formed copper so that the surface of the second insulating film 42 is exposed.

  Next, effects of the semiconductor device according to the present embodiment will be described.

  The through electrode 120 is formed in a state where the first through electrode portion 122 and the second through electrode portion 124 are connected to each other. In the through electrode 120, in the first through electrode part 122 and the second through electrode part 124, the hole diameter of the first through electrode part 122 is larger than the hole diameter of the second through electrode part 124. By doing so, the through electrode 120 can be brought into contact with the upper surface of the second wiring 32 as well. That is, the contact area between the through electrode 120 and the second wiring 32 is increased, and the contact resistance can be reduced.

  FIG. 12 is a view for explaining the contact area between the through electrode and the wiring and the electromigration lifetime in the semiconductor device according to the present embodiment.

  As shown in FIG. 12, it can be seen that the electromigration lifetime is extended as the contact area between the through electrode 120 and the second wiring 32 increases. That is, it is possible to improve the reliability by ensuring the contact area between the through electrode 120 and the second wiring 32.

(Second Embodiment)
FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment.
As shown in FIG. 13, the configuration is the same as that of the first embodiment except that the insulating film 100 covering the through electrode 120 is not provided. In the present embodiment, as in the first embodiment, the contact area between the through electrode 120 and the second wiring 32 is increased, and the contact resistance can be reduced.

(Third embodiment)
FIG. 14 is a cross-sectional view of the semiconductor device according to the present embodiment.
As shown in FIG. 14, a third semiconductor chip 400 may be provided in addition to the first semiconductor chip 200 and the second semiconductor chip 300. That is, the semiconductor device of the present embodiment may have a configuration using three or more semiconductor chips. When manufacturing the semiconductor device according to this embodiment, the method includes a step of stacking the third semiconductor chip 400 on the second semiconductor chip 300 and a step of forming three through-electrode holes having different hole diameters. ing. However, the method of forming the through electrode hole is the same as in the first and second embodiments. Here, the third semiconductor chip 400 is provided with a multilayer wiring layer on the substrate 14. Transistors are formed on the substrate 14, and a third wiring 34 is formed in a part of the multilayer wiring layer. Note that the present embodiment can provide the same effects as those of the first embodiment.

(Fourth embodiment)
FIG. 15 is an enlarged cross-sectional view of the semiconductor device according to the present embodiment.
As shown in FIGS. 15 (a) and 15 (b), it differs from the first, second and third embodiments in that the connecting portion of the through electrode 120 and the second wiring 32 is tapered. Yes. Here, the tapered shape includes a case where the corners are rounded as shown in FIG. With such a configuration, the contact between the through electrode 120 and the second wiring 32 is made as compared with the case where the second wiring 32 is processed vertically as in the first, second, and third embodiments. The area increases. Note that the present embodiment can provide the same effects as those of the first, second, and third embodiments.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 10 1st board | substrate 12 2nd board | substrate 14 3rd board | substrate 20 Insulating film 22 Insulating film 24 Insulating film 30 1st wiring 32 2nd wiring 34 3rd wiring 40 1st insulating film 42 2nd insulation Film 44 Third insulating film 50 Substrate connection layer 52 Substrate connection layer 60 Resist 70 Insulating film 80 First through electrode hole 90 Second through electrode hole 100 Insulating film 110 Barrier metal film 120 Through electrode 122 First through electrode Part 124 second through electrode part 200 first semiconductor chip 300 second semiconductor chip 400 third semiconductor chip

Claims (5)

A first semiconductor chip;
A second semiconductor chip stacked on the first semiconductor chip;
A through electrode connecting the first semiconductor chip and the second semiconductor chip;
Have
The first semiconductor chip includes a first substrate,
A first wiring provided on the first substrate;
A first insulating film provided on the first wiring;
Including
The second semiconductor chip includes a second substrate,
A second wiring provided on the second substrate;
A second insulating film provided on the second wiring;
In the second semiconductor chip, the through electrode includes a first through electrode portion provided from an upper surface of the second insulating film to an upper portion of the second wiring,
A second through-electrode portion connected to the lower surface of the first through-electrode portion and provided from the same layer as the second wiring to the upper portion of the first wiring of the first semiconductor chip;
Including
The hole diameter of the said 1st penetration electrode part and the said 2nd penetration electrode part is a semiconductor device with a larger hole diameter of the said 1st penetration electrode in planar view.   2. The semiconductor device according to claim 1, wherein the hole diameters of the first through electrode portion and the second through electrode portion are different by 40 nm or more.   3. The semiconductor device according to claim 1, wherein a connection surface in contact with the through electrode of the second wiring is tapered.   4. The semiconductor device according to claim 1, wherein the first and second wirings are power supply or ground wirings. A first semiconductor chip including a first substrate, a first wiring provided on the first substrate, and a first insulating film provided on the first wiring; And a second semiconductor chip including a second wiring provided on the second substrate, and a second insulating film provided on the second wiring, and insulated from each other A pasting process for pasting in a finished state;
A first hole forming step of etching the second insulating film of the second semiconductor chip to form a first through electrode hole;
A second hole forming step of forming a second through electrode hole by etching from the first through electrode hole to the upper part of the first wiring of the first semiconductor chip;
A through electrode forming step of forming a through electrode by forming a Cu film in the first through electrode hole and the second through electrode hole;
Have
The diameter of the first through electrode hole and the second through electrode hole is a method for manufacturing a semiconductor device in which the first through electrode hole is larger in plan view.

Images