JP2013239569A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a slit-like hole is formed on a surface when an insulation film is embedded in a groove of a high aspect ratio with good coverage, and a composition used in CMP (Chemical Mechanical Polishing), a polished and removed object and other residues are likely to remain in the hole when the surface is planarized by CMP and the residues contribute to dust emission in the subsequent process.SOLUTION: A semiconductor device manufacturing method comprises: forming a groove 2T in an annular shape when viewed from above on a first principal surface of a substrate 1; forming a polysilicon film 202 in the groove; forming a second insulation film 203 having a seam 204 and a recess 205 on a surface; converting an upper part of the polysilicon film 202 to a first insulation film 206 by oxidation to eliminate the seam 204 and make the recess 205 smaller; and subsequently planarizing the substrate 1 to a surface to form an insulating separation part 2 without a recess.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a through electrode penetrating a semiconductor substrate and a manufacturing method thereof.

  2. Description of the Related Art In recent years, semiconductor devices in which a plurality of semiconductor chips are stacked and integrated in the vertical direction have been proposed with the increasing functionality and diversification of semiconductor devices. In such a semiconductor device, each semiconductor chip is configured to be electrically connected by a through electrode (Through Silicon Via: TSV) penetrating the semiconductor substrate of each semiconductor chip.

  On the other hand, since the TSV is formed through the semiconductor substrate, it is necessary to provide insulation between the semiconductor substrate and the TSV. In view of this, it has been proposed to provide a ring-shaped insulating isolation portion (referred to as an insulating ring) around the TSV to isolate it from the semiconductor layer in the element formation region (Patent Document 1).

  In Patent Document 1, in the first step of all the processes, an annular groove (trench) is dug in the depth direction from the element formation surface side of the silicon substrate, and the trench is filled with an insulating film to form an insulating ring. Thereafter, after the element formation on the substrate surface, the wiring layer formation, the surface electrode formation step, and the like, the silicon substrate is ground from the back side to be thinned. At this time, by grinding the back surface until the bottom of the insulating ring is exposed from the back surface of the substrate, the insulating ring penetrates the silicon substrate from the front surface to the back surface. Then, a TSV is formed from the back side so as to penetrate the silicon substrate inside the insulating ring.

  In order to suppress an increase in the aspect ratio of the groove for forming the insulating ring, there is a method in which a polysilicon film is formed in a wide ring-shaped groove with a film thickness that does not bury the groove, and the inside is thermally oxidized. It has been proposed (Patent Document 2). According to the formation method of Patent Document 2, after forming a ring-shaped separation groove (groove width of about 5 μm) on a silicon substrate, a polycrystalline silicon film of about 2 μm is conformally formed by a CVD method. The polycrystalline silicon film is thermally oxidized to form a silicon thermal oxide film having a thickness of about 0.8 μm. Thereafter, a silicon oxide film is formed by a CVD method to fill the gap (see the paragraphs [0021] to [0025] above). Here, in the step of forming the silicon thermal oxide film having a thickness of about 0.8 μm, the polycrystalline silicon film is buried with a silicon thermal oxide film having a thickness of about 1.6 μm in total on both side walls in the trench. In general thermal oxidation, about half is formed on the original silicon side, and the other half is formed in the direction of expanding the original silicon. Accordingly, the gap remaining in the separation groove has a width of about 200 nm and is buried with a CVD silicon oxide film.

JP 2007-123857 A JP 2008-251964 A

  In the insulating ring, for example, a trench (hereinafter referred to as a TSV trench) having a depth of 40 to 50 μm and a width of 2 to 3 μm (aspect ratio 13 to 25) is formed in a silicon substrate, and an insulating material such as a silicon oxide film is formed there. Embed the membrane. Finally, the insulating film deposited on the substrate surface is removed by chemical mechanical polishing (CMP) to complete the process. In this step, as described above, a thick silicon oxide film having a thickness of several μm must be formed in a deep TSV trench having a depth of several tens of μm, resulting in large variations in film thickness and embeddability. Can be low. In particular, when a silicon oxide film is deposited by a method having poor coverage, the opening of the TSV trench is closed first and a large void is formed. On the other hand, even when the silicon oxide film is formed with good coverage, a junction surface (seam) of the silicon oxide film grown from both side walls is formed at an intermediate position viewed from both side walls of the TSV trench. In the seam portion, microscopically small voids can be included. In the upper part of such a seam, as shown in FIG. 9 of Patent Document 1, a slit-like hole (concave portion) is formed in the vicinity of the TSV trench opening. Even after polishing an insulating film such as a silicon oxide film on the surface of the substrate by CMP, it remains as an annular slit on the surface of the insulating ring.

  According to the study of the present inventors, the composition used in the CMP process, the polished removed material, and other residues are likely to remain in the slit remaining on the surface of the insulating ring as described above. There is room for improvement because the residue can cause dust generation in a later process.

According to one embodiment of the present invention,
Forming a groove having a bird's-eye shape in a ring shape on the first main surface of the substrate;
Burying an insulating film in the groove and forming an insulating separation part;
With
The insulating film includes a first insulating film formed by oxidizing at least a part after forming a polysilicon film, and a second insulating film formed with a recess on the surface of the groove central portion at least in the film forming stage. Including an insulating film,
By oxidizing the polysilicon film, a method for manufacturing a semiconductor device is provided, in which the depth of the concave portion in the step of forming the second insulating film is reduced or the concave portion is eliminated.

Also, according to another embodiment of the present invention,
An element formation region formed on the first main surface of the semiconductor substrate;
An insulating separation portion penetrating from the first main surface of the semiconductor substrate to the second main surface facing the semiconductor substrate, and the overhead shape is annular;
Terminals penetrating through the second main surface facing the first main surface of the semiconductor substrate surrounded by the annular insulating separation portion and exposed to the outside of the first main surface and the second main surface A through electrode having,
A semiconductor device comprising:
In the annular insulating isolation part, at least a first insulating film formed by oxidizing a polysilicon film and a second insulating film different from the first insulating film are exposed on the surface of the first main surface. Thus, a semiconductor device is provided in which the first insulating film is not present on the second main surface.

  In the present invention, the polysilicon is oxidized and converted into the first insulating film, so that the concave portion formed in the second insulating film at the film formation stage disappears after the planarization. Can be reduced. As a result, the manufacturing yield of a semiconductor device having a TSV with an insulating ring can be improved.

A schematic sectional view (a), a first main surface side plan view (b), and a second main surface side plan view (c) of a semiconductor chip 50 according to an embodiment of the present invention are shown. (A)-(c) shows process sectional drawing explaining the manufacturing process of the insulating ring which concerns on one Embodiment of this invention. (A)-(c) shows process sectional drawing explaining the manufacturing process of the insulating ring which concerns on another embodiment of this invention. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. Process sectional drawing explaining the manufacturing process of the semiconductor chip 50 which concerns on one Embodiment of this invention is shown. The schematic sectional drawing (a) of the semiconductor module 100 using the semiconductor chip 50 which concerns on one Embodiment of this invention, and its partial enlarged view (b) are shown. The arrangement | positioning of the insulating ring and penetration electrode which were manufactured in the example of 1 embodiment of this invention is demonstrated, (a) is an overhead plan view from the 1st main surface, (b) is from the 2nd main surface. An overhead view of FIG. The arrangement | positioning of the insulating ring and penetration electrode which were manufactured in another example of this invention is demonstrated, (a) is an overhead plan view from the 1st main surface, (b) is the 2nd main surface. An overhead view from above is shown.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to these embodiments.

  1A and 1B show an example of a semiconductor device (semiconductor chip 50) having a TSV structure to which the present invention is applied. FIG. 1A is a schematic cross-sectional view showing a TSV structure portion, and FIGS. Schematic plan views of the first main surface side and the second main surface side of the semiconductor chip 50 are respectively shown. FIG. 1A corresponds to a cross-sectional view taken along line A1-A1 in FIGS.

  The semiconductor substrate 1 is provided with an insulating isolation portion (referred to as an insulating ring) 2 having an annular overhead shape for insulating the TSV from the element region (DA), and a seed layer is formed in the TSV formation region surrounded by the insulating ring 2. A TSV 22 composed of 18 and a Cu plug 20 is formed. In this example, although TSV22 shows the example formed integrally with an external terminal (bump part), you may form separately. A solder film (Sn—Ag alloy layer) 21 is formed on the surface of the bump portion of the TSV 22.

  On the other hand, on the first main surface side where the semiconductor element 5 is formed, a wiring structure 7 including a conductor wiring and a plug is formed in the interlayer insulating film 6. The interlayer insulating film 6 is formed of silicon oxide or the like. The lowermost layer of the wiring structure 7 is a pad electrode connected to the TSV 22 and is formed of a metal such as tungsten, for example. The upper wiring layer can be formed of a conductor such as aluminum. The uppermost part of the wiring structure 7 is covered with a surface protective film (silicon nitride film 8a and passivation film 8b) 8. An opening exposing the uppermost portion of the wiring structure 6 is formed in the surface protective film 8, and a bump electrode 12 is formed in the opening. The bump electrode 12 includes a seed layer 8, a main Cu layer 10, and a Ni layer 11. Here, the TSV structure 23 extends from the TSV 22 on the back surface to the bump electrode 12 on the first main surface side.

  In the example shown in FIG. 1, a structure in which a plurality of TSV structures 23 are arranged in two rows at the center of the semiconductor chip 50 is shown, but the present invention is not limited to this.

(Example 1)
Next, the manufacturing method of the insulating ring 2 which concerns on one Embodiment of this invention is demonstrated with reference to FIG. In the insulating ring 2 according to the present embodiment, the liner silicon nitride film 201 is formed in the annular groove 2T formed in the semiconductor substrate 1, and then the polysilicon film 202 is formed. Thereafter, the polysilicon film 202 other than in the trench 2T and the peripheral portion is removed. Subsequently, a silicon oxide film (NSG film: second insulating film) 203 is formed on the entire surface. The NSG film 203 is formed by a film formation method with good coverage such as a low pressure CVD method using TEOS as a raw material. In this film formation stage, as in the conventional case, a seam 204 is formed at the center of the width of the groove 2T, and a concave portion 205 that is connected to the seam 204 and is depressed on the surface is formed (FIG. 2A).

  Next, heat treatment is performed in an oxidizing atmosphere to oxidize part of the polysilicon film 202 and convert it into a silicon oxide film (first insulating film) 206. Since the volume expands with the conversion from polysilicon to silicon oxide, the NSG film 203 thereon is pushed up, the seam 204 between the silicon oxide films 206 disappears, and the recesses 205 also become smaller (FIG. 2B). . The heat treatment can be performed under the same conditions as the heat treatment performed for densification of the NSG film 203 and does not increase as a process, but the processing time and the like are appropriately adjusted. Since the surface of the semiconductor substrate 1 is protected by the liner silicon nitride film 201, it is not oxidized.

  Thereafter, planarization is performed by CMP. In FIG. 2A, the polysilicon film 202 is removed except for the periphery of the trench 2T because the silicon oxide film (first insulating film) 206 formed by thermal oxidation from the polysilicon film 202 is more than the NSG film 203. This is because the CMP load is large, and by removing the parts other than the necessary portion, the increase in the CMP load is suppressed. As a result, as shown in FIG. 2 (c), the surface of the insulating ring 2 has no recess 205, no polishing residue remains, and dust generation in the subsequent process can be prevented. In addition, the seam 204 near the substrate surface has also disappeared, and the problem that the TSV region is depressed or raised can be improved.

Embodiment 2
FIG. 3 shows a method for manufacturing an insulating ring 2 according to another embodiment of the present invention. In this embodiment, the liner silicon nitride film 201 and the NSG film (second insulating film) 203 are formed in the annular groove 2T formed in the semiconductor substrate 1 as in the conventional case. Thereafter, a polysilicon film 202 is formed, and the polysilicon film 202 other than on the trench 2T and the peripheral portion is removed. The polysilicon film 202 is formed so as to fill the recess 205 of the NSG film 203 (FIG. 3A).

  Next, heat treatment is performed in an oxidizing atmosphere to oxidize the polysilicon film 202 and convert it into a silicon oxide film 206. Since the volume expands with the conversion from polysilicon to silicon oxide, the NSG film 203 and the silicon oxide film (first insulating film) 206 are firmly bonded (FIG. 3B).

  Thereafter, planarization is performed by CMP. As a result, as shown in FIG. 3C, the surface of the insulating ring 2 has no recess 205 and no polishing residue remains, and dust generation in the subsequent process can be prevented. Further, the vicinity of the substrate surface above the seam 204 is firmly bonded by a silicon oxide film 206 converted from polysilicon, and the problem that the TSV region is depressed or raised can be improved.

(Application example)
A manufacturing method of the semiconductor chip 50 and a manufacturing method of the semiconductor module 100 in which a plurality of the semiconductor chips 50 are stacked will be described. 4 to 9 are process cross-sectional views illustrating the manufacturing process of the semiconductor chip 50 shown in FIG. 1, and FIG. 10 is a schematic cross-sectional view of the packaged semiconductor module 100 in which a plurality of semiconductor chips (50a to 50h) are stacked and connected. The figure (a) and its partial enlarged view (b) are shown.

  First, as shown in FIG. 4, a first groove 2 </ b> T for forming the insulating ring 2 from the first main surface side of the semiconductor substrate 1 is formed. The shape of the first groove 2T can be, for example, a width of 2 μm and a depth of 50 μm. Prior to the formation of the first trench 2T, the surface of the semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 3 serving as a hard mask. The patterning of the silicon oxide film 3 is performed by forming a pattern of the first groove 2T by photolithography using a photoresist (not shown), patterning the silicon oxide film 3 by dry etching, and subsequently performing semiconductor etching by dry etching. The substrate 1 is etched to form a first groove 2T having a desired depth.

  Next, as shown in FIG. 5, the insulating ring 2 is formed by embedding an insulating film in the first groove 2T by the method shown in the first or second embodiment.

  Subsequently, as shown in FIG. 6, the semiconductor element 5 is formed on the first main surface of the semiconductor substrate 1 according to a conventional method, and the wiring structure 7 is formed in the interlayer insulating film 6. Further, a capacitor is also formed in a semiconductor device including a DRAM. After forming a silicon nitride film 8a and a polyimide film (passivation film) 8b as the surface protective film 8, an opening for a bump electrode is formed. The opening is formed by first patterning the polyimide film 8b and further etching the silicon nitride film 8a by a photolithography process using a photoresist. Thereafter, a metal seed layer 9 (Cu / Ti) is formed on the entire surface of the first main surface by sputtering.

  Next, as shown in FIG. 7, after forming a resist pattern 10 for forming a bump electrode, a Cu film 11 is formed by electrolytic plating. Further, a Ni / Au film 12 is formed as an electroconductive protective film by an electrolytic plating method.

  The bump electrode 13 is formed by removing the resist pattern 10 for forming the bump electrode and further removing the metal seed layer 9 exposed on the surface. An adhesive layer 14 is applied to the entire first main surface side of the semiconductor substrate, and further attached to a substrate support system (WSS) 16 via a light-to-heat converter (LTHC) 15. As WSS16, a transparent glass plate or a hard resin plate can be used. After this, the second main surface (back surface) side facing the first main surface of the semiconductor substrate 1 is ground (back grind) to a predetermined thickness (about 40 to 100 μm) and thinned, The end portion on the back surface side of the insulating ring 2 previously formed is exposed. Grinding was performed in the order of rough cutting, fine cutting, and CMP.

  Next, the back surface protection film 17 is formed of, for example, a silicon nitride film on the back surface side while being held by the WSS 16. Further, an opening for TSV is formed in a region surrounded by the insulating ring 2 by a photolithography technique and a dry etching technique. At this time, the lowermost tungsten pad of the wiring structure 7 serves as an etching stopper. After the opening is formed, a metal seed layer (Cu / Ti) 18 is formed over the entire second main surface by sputtering (FIG. 8).

  Next, a photoresist film 19 for forming TSV is formed on the metal seed layer 18, and the photoresist film 19 in and around the formed opening is removed. The photoresist film 19 around the opening is appropriately adjusted according to the shape of the bump formed integrally with the TSV. A Cu plug 20 is formed by electrolytic plating, and then a solder film (Sn—Ag alloy layer) 21 is formed by electrolytic plating (FIG. 9).

  Thereafter, the photoresist film 20 for forming TSV is removed, and the metal seed layer 18 exposed on the back surface of the substrate is removed. Thereby, the TSV 22 having the solder film 21 on the surface is formed. Next, annealing is performed (bump reflow) so that the solder film 21 rises (convex) in the center of the bump portion of the TSV 22. The annealing temperature in the bump reflow may be equal to or higher than the temperature at which the solder melts, and is usually performed at 300 ° C. or lower. Further, the LTHC layer 15 is irradiated with a laser to peel off the WSS 16 and the adhesive layer 14 is removed. Finally, dicing is performed to divide the semiconductor chips 50 into individual pieces.

  The individual semiconductor chips (50a to 50h) are stacked as shown in FIG. 10, and the solder film 21 is reflowed in a pressurized state. Here, a state in which semiconductor chips manufactured by the method described above and having a TSV structure having the same structure are joined is shown.

  The bump electrode 13 (Ni / Au film 12) on the first main surface side of each semiconductor chip and the bump portion (solder film 21) of the TSV 22 on the back surface side are aligned and soldered while pressing with a constant pressure. The solder film 21 is reflowed by applying a temperature equal to or higher than the melting point and up to about 300 ° C. As described above, the TSV structures are joined to each other. The pressure (load) applied at the time of joining is performed within a range that does not affect the TSV structure, particularly the wiring structure 7. For example, what is necessary is just to set so that it may become about 10-150g per bump electrode. The heating means may be selected from the use of a reflow oven or oven, the heat radiation of a halogen lamp, the contact of a heating body, etc., and is not particularly limited.

  Finally, underfill resin 24 is filled between the semiconductor chips. Subsequently, the external terminal of the TSV 23 of the lowermost semiconductor chip 50a is connected to the package substrate 26, and a ball grid array (BGA) 27 made of a mold resin 25 and solder balls is formed, whereby the semiconductor module 100 shown in FIG. Is completed. FIG. 10A shows a case where eight chips of the semiconductor chips 50a to 50h are stacked, and FIG. 10B shows a partially enlarged view.

  The arrangement of the insulating ring and the through electrode manufactured by the methods of Embodiments 1 and 2 will be described with reference to FIGS. 11 and 12. In these drawings, (a) is an overhead plan view viewed from the first main surface (element forming surface), and (b) is an overhead plan view viewed from the second main surface (back surface). In the insulating ring 2 (FIG. 11) formed in the first embodiment, the first main surface side is the NSG film 203 surrounded by the liner silicon nitride film 201 and the silicon oxide film 206, and the seam 204 on the surface of the NSG film 203 is Almost disappeared. The second main surface side becomes the NSG film 203 surrounded by the liner silicon nitride film 201 and the polysilicon film 202, and the seam 204 is also observed. In the insulating ring 2 (FIG. 12) formed in Embodiment 2, the first main surface side becomes the liner silicon nitride film 201, the NSG film 203, and the silicon oxide film 206 from the outside, and the seam 204 is not observed. The second main surface side becomes the NSG film 203 surrounded by the liner silicon nitride film 201, and the seam 204 is also observed. In any case, the silicon oxide film 206 formed by thermal oxidation does not exist on the second main surface side. However, in the case of FIG. 11B, a natural oxide film may be formed on the surface of the polysilicon film 202.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulation ring 2T Trench 201 Liner silicon nitride film 202 Polysilicon film 203 NSG film 204 Seam 205 Recess 206 Silicon oxide film 3 Hard mask layer 4 Protection film 5 Semiconductor element 6 Interlayer insulation film 7 Wiring structure 8 Surface protection film 8a Silicon nitride film 8b Passivation film (polyimide film)
9 Metal seed layer 10 Resist pattern 11 Cu film 12 Ni / Au film 13 Bump electrode 14 Adhesive layer 15 Photothermal conversion layer 16 Substrate support system 17 Back surface protective film 18 Metal seed layer 19 Photoresist film 20 Cu plug 21 Solder film 22 TSV
23 Through-electrode 24 Underfill resin 25 Mold resin 26 Package substrate 27 BGA
50 Semiconductor chip 100 Semiconductor module

Claims (19)

Forming a groove having a bird's-eye shape in a ring shape on the first main surface of the substrate;
Burying an insulating film in the groove and forming an insulating separation part;
With
The insulating film includes a first insulating film formed by oxidizing at least a part after forming a polysilicon film, and a second insulating film formed with a recess on the surface of the groove central portion at least in the film forming stage. Including an insulating film,
A method of manufacturing a semiconductor device, comprising: oxidizing the polysilicon film to reduce a depth of a concave portion in a film formation step of the second insulating film or to eliminate the concave portion. Forming a polysilicon film on the first main surface of the substrate and in the groove so as not to close the groove;
Forming the second insulating film on the polysilicon film;
Oxidizing the polysilicon film in the upper part of the groove to convert it into the first insulating film;
The method for manufacturing a semiconductor device according to claim 1, further comprising: removing the second insulating film and the first insulating film on the substrate and planarizing the substrate.   3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of removing the polysilicon film other than the inside of the groove and the periphery of the groove before forming the second insulating film. Forming the second insulating film by filling the groove on the first main surface of the substrate and in the groove;
Forming a polysilicon film by filling the concave portion in the central portion of the groove of the second insulating film with the concave portion;
Oxidizing the polysilicon film to convert it to the first insulating film;
The method for manufacturing a semiconductor device according to claim 1, further comprising: removing the second insulating film and the first insulating film on the substrate and planarizing the substrate.   The method of manufacturing a semiconductor device according to claim 4, further comprising a step of removing the polysilicon film other than on the groove and the periphery of the groove.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is mainly composed of non-doped silicon oxide.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a third insulating film mainly composed of silicon nitride in the trench.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of grinding a second main surface opposite to the first main surface of the substrate to expose the bottom surface of the insulating separation portion. .   And forming a through electrode penetrating from the first main surface to the second main surface in the region surrounded by the annular insulating separation portion. Item 9. A method for manufacturing a semiconductor device according to Item 8. An element formation region formed on the first main surface of the semiconductor substrate;
An insulating separation portion penetrating from the first main surface of the semiconductor substrate to the second main surface facing the semiconductor substrate, and the overhead shape is annular;
Terminals penetrating through the second main surface facing the first main surface of the semiconductor substrate surrounded by the annular insulating separation portion and exposed to the outside of the first main surface and the second main surface A through electrode having,
A semiconductor device comprising:
In the annular insulating isolation part, at least a first insulating film formed by oxidizing a polysilicon film and a second insulating film different from the first insulating film are exposed on the surface of the first main surface. The semiconductor device is characterized in that the first insulating film does not exist on the second main surface.   The semiconductor device according to claim 10, wherein the first insulating film is formed on an inner periphery and an outer periphery side of the annular insulating separation portion.   The semiconductor device according to claim 11, further comprising a polysilicon film below the first insulating film, wherein the second insulating film is surrounded by the polysilicon film.   The second main surface of the insulating isolation portion includes the polysilicon film formed on the inner peripheral side and the outer peripheral side of the annular insulating isolation portion and the second insulating film sandwiched between the polysilicon films. The semiconductor device of Claim 12 containing.   The semiconductor device according to claim 10, wherein the first insulating film is formed in an annular shape at a central portion of a width of the annular insulating separation portion.   The semiconductor device according to claim 10, wherein the second insulating film is an insulating film mainly composed of non-doped silicon oxide.   16. The semiconductor device according to claim 10, further comprising a third insulating film mainly composed of silicon nitride at an outer peripheral end and an inner peripheral end of the insulating isolation part.   The semiconductor device according to claim 1, wherein the through electrode has a plug mainly composed of copper that penetrates the semiconductor substrate from the second main surface to the first main surface.   The terminal exposed to the outside of one of the first main surface and the second main surface of the through electrode has a conductive protective film on the surface, and the terminal exposed on the other has a solder film on the surface. The semiconductor device according to claim 17.   A semiconductor device in which a plurality of the semiconductor devices according to claim 10 are stacked and connected to each other through the through electrodes.

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