JP5913535B1 - Component built-in substrate and manufacturing method thereof - Google Patents

Component built-in substrate and manufacturing method thereof Download PDF

Info

Publication number
JP5913535B1
JP5913535B1 JP2014234748A JP2014234748A JP5913535B1 JP 5913535 B1 JP5913535 B1 JP 5913535B1 JP 2014234748 A JP2014234748 A JP 2014234748A JP 2014234748 A JP2014234748 A JP 2014234748A JP 5913535 B1 JP5913535 B1 JP 5913535B1
Authority
JP
Japan
Prior art keywords
substrate
electronic component
layer
component
sided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014234748A
Other languages
Japanese (ja)
Other versions
JP2016100408A (en
Inventor
隼介 佐藤
隼介 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2014234748A priority Critical patent/JP5913535B1/en
Application granted granted Critical
Publication of JP5913535B1 publication Critical patent/JP5913535B1/en
Publication of JP2016100408A publication Critical patent/JP2016100408A/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

【課題】製造工程を簡素化しつつ全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスの増加を防止できる部品内蔵基板及びその製造方法を提供する。【解決手段】多層構造の部品内蔵基板1は、第1絶縁層11の両面に形成された第1配線層12、第1層間導電層13及び前記第1電子部品91又は前記第2電子部品90が収容された開口部19を有する両面基板10a及び10bと、第2絶縁層21の両面に設けられた第1接着層22及び第2層間導電層23を有する中間基板20とを備え、前記中間基板20の上層及び下層に前記両面基板10a及び10bがそれぞれ配置され、前記中間基板20の上層に位置する前記第1電子部品91の電極91aと、下層に位置する前記第2電子部品90の電極90aは、前記第2層間導電層23を介して直接に接続されている。【選択図】図1Provided are a component-embedded substrate capable of reducing the overall thickness while simplifying the manufacturing process and preventing an increase in impedance and inductance between electrodes, and a method for manufacturing the same. A component-embedded substrate 1 having a multilayer structure includes a first wiring layer 12, a first interlayer conductive layer 13 and a first electronic component 91 or a second electronic component 90 formed on both surfaces of a first insulating layer 11. The double-sided substrates 10a and 10b having the opening 19 in which the first insulating layer 21 is accommodated, and the intermediate substrate 20 having the first adhesive layer 22 and the second interlayer conductive layer 23 provided on both sides of the second insulating layer 21. The double-sided substrates 10a and 10b are respectively disposed on the upper layer and the lower layer of the substrate 20, and the electrode 91a of the first electronic component 91 located on the upper layer of the intermediate substrate 20 and the electrode of the second electronic component 90 located on the lower layer. 90 a is directly connected through the second interlayer conductive layer 23. [Selection] Figure 1

Description

この発明は、電子部品を内蔵した部品内蔵基板及びその製造方法に関する。   The present invention relates to a component-embedded substrate that incorporates an electronic component and a method for manufacturing the same.

近年の小型精密電子機器を中心とした更なる小型化や高性能化の要求に対応するために、基板に搭載される半導体デバイスについても小型化や高集積化が求められている。このような要求に対してCoC(Chip on Chip)、PoP(Package on Package)等の三次元パッケージ技術や部品内蔵基板技術により、半導体デバイスの小型化を進めつつ高集積化に対応する必要性が増している。   In order to meet the demand for further miniaturization and higher performance centered on recent small precision electronic devices, semiconductor devices mounted on a substrate are also required to be miniaturized and highly integrated. In response to such demands, there is a need to cope with high integration while miniaturizing semiconductor devices by using three-dimensional package technology such as CoC (Chip on Chip) and PoP (Package on Package) and component-embedded substrate technology. It is increasing.

部品内蔵基板技術を用いたものとして、下記特許文献1に開示された多層プリント配線板が知られている。この多層プリント配線板は、絶縁基板に配線層が形成された複数のプリント配線板を、両面に接着層を形成した絶縁体スペーサを介して積層し、絶縁スペーサにより形成されるプリント配線板間のスペースに電子部品を内蔵している。   A multilayer printed wiring board disclosed in the following Patent Document 1 is known as one using the component-embedded substrate technology. This multilayer printed wiring board is formed by laminating a plurality of printed wiring boards each having a wiring layer formed on an insulating substrate via insulating spacers having adhesive layers formed on both sides, and between the printed wiring boards formed by the insulating spacers. Electronic components are built into the space.

特開2007−80857号公報JP 2007-80857 A

しかしながら、上述した特許文献1に開示された従来技術の多層プリント配線板では、各プリント配線板間に、内蔵される電子部品の厚さよりも厚い絶縁体スペーサを配置して、各プリント配線板間に電子部品を内蔵するための空隙を形成した状態で多層に積層している。このため、製造工程が煩雑になると共に多層プリント配線板全体の薄型化が図り難く、さらに各電子部品の電極間を接続する導体距離が長くなり、電極間のインピーダンス及びインダクタンスが増加してしまうという問題がある。   However, in the multilayer printed wiring board of the prior art disclosed in Patent Document 1 described above, an insulating spacer thicker than the thickness of the built-in electronic component is disposed between the printed wiring boards, so Are stacked in multiple layers in a state where gaps for incorporating electronic components are formed. For this reason, the manufacturing process becomes complicated and it is difficult to reduce the thickness of the entire multilayer printed wiring board, and further, the conductor distance connecting the electrodes of each electronic component becomes longer, and the impedance and inductance between the electrodes increase. There's a problem.

この発明は、上述した従来技術による問題点を解消し、製造工程を簡素化しつつ全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスが増加することを防ぐことができる部品内蔵基板及びその製造方法を提供することを目的とする。   The present invention eliminates the problems caused by the above-described prior art, can reduce the overall thickness while simplifying the manufacturing process, and can prevent increase in impedance and inductance between electrodes, and It aims at providing the manufacturing method.

本発明に係る部品内蔵基板は、積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板において、第1絶縁層の両面に形成された第1配線層、前記第1絶縁層を貫通し前記第1配線層と接続された第1層間導電層及び前記第1電子部品又は前記第2電子部品が収容された開口部を有する両面基板と、第2絶縁層の両面に設けられた第1接着層及び前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を有する中間基板とを備え、前記中間基板の上層及び下層に前記両面基板がそれぞれ配置され、前記中間基板の上層に位置する前記第1電子部品の電極と、下層に位置する前記第2電子部品の電極は、前記第2層間導電層を介して直接に接続されていることを特徴とする。   A component-embedded substrate according to the present invention is a component-embedded substrate having a multilayer structure in which a first electronic component and a second electronic component are embedded in a stacking direction, the first wiring layer formed on both surfaces of the first insulating layer, A first interlayer conductive layer penetrating the first insulating layer and connected to the first wiring layer; a double-sided substrate having an opening accommodating the first electronic component or the second electronic component; and a second insulating layer An intermediate substrate having a first adhesive layer provided on both sides and a second interlayer conductive layer penetrating the second insulating layer together with the first adhesive layer, and the double-sided substrates on the upper layer and the lower layer of the intermediate substrate, respectively. The electrode of the first electronic component located in the upper layer of the intermediate substrate and the electrode of the second electronic component located in the lower layer are directly connected via the second interlayer conductive layer. Features.

本発明に係る部品内蔵基板によれば、積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板において、第1絶縁層の両面に形成された第1配線層、前記第1絶縁層を貫通し前記第1配線層と接続された第1層間導電層及び前記第1電子部品又は前記第2電子部品が収容された開口部を有する両面基板と、第2絶縁層の両面に設けられた第1接着層及び前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を有する中間基板とを備え、前記中間基板の上層及び下層に前記両面基板がそれぞれ配置され、前記中間基板の上層に位置する前記第1電子部品の電極と、下層に位置する前記第2電子部品の電極は、前記第2層間導電層を介して直接に接続されていることにより、製造工程を簡素化しつつ全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスが増加することを防ぐことができる。   According to the component-embedded substrate according to the present invention, in the component-embedded substrate having a multilayer structure in which the first electronic component and the second electronic component are embedded in the stacking direction, the first wiring layer formed on both surfaces of the first insulating layer. A double-sided substrate having a first interlayer conductive layer penetrating the first insulating layer and connected to the first wiring layer, and an opening accommodating the first electronic component or the second electronic component; and a second insulation A first adhesive layer provided on both sides of the layer, and an intermediate substrate having a second interlayer conductive layer penetrating the second insulating layer together with the first adhesive layer, and the double-sided substrate on an upper layer and a lower layer of the intermediate substrate Are arranged, and the electrode of the first electronic component located in the upper layer of the intermediate substrate and the electrode of the second electronic component located in the lower layer are directly connected via the second interlayer conductive layer. This simplifies the manufacturing process and reduces the overall thickness. It is possible to prevent the impedance and inductance between the electrodes is increased it is possible to achieve reduction.

上記部品内蔵基板において、前記第1電子部品又は前記第2電子部品のいずれか一方は片面のみに電極が形成された半導体チップであり、前記半導体チップは、電極が前記中間基板と対向していてもよい。   In the component-embedded substrate, one of the first electronic component and the second electronic component is a semiconductor chip in which an electrode is formed only on one side, and the semiconductor chip has an electrode facing the intermediate substrate. Also good.

上記部品内蔵基板において、第3絶縁層の一方の面に形成された第2配線層、他方の面に設けられた第2接着層及び前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続された第3層間導電層を有する片面基板を備え、前記第1電子部品又は前記第2電子部品のいずれか一方は両面に電極が形成された電子部品であり、前記片面基板の前記第3層間導電層は、前記両面に電極が形成された電子部品における前記中間基板とは反対の面の電極と接続され、前記片面基板及び前記中間基板が、前記両面に電極が形成された電子部品が開口部に収容された両面基板を挟んで積層されていてもよい。   In the component-embedded substrate, the second wiring layer formed on one surface of the third insulating layer, the second adhesive layer provided on the other surface, and the second adhesive layer pass through the third insulating layer and pass through the third insulating layer. A single-sided substrate having a third interlayer conductive layer connected to the second wiring layer, wherein one of the first electronic component and the second electronic component is an electronic component having electrodes formed on both sides thereof; The third interlayer conductive layer of the substrate is connected to an electrode on a surface opposite to the intermediate substrate in the electronic component having electrodes formed on both surfaces, and the single-sided substrate and the intermediate substrate are formed with electrodes on the both surfaces. The electronic components thus obtained may be stacked with a double-sided board accommodated in the opening.

上記部品内蔵基板において、前記第1電子部品は片面のみに電極が形成された第1の半導体チップであると共に、前記第2電子部品は片面のみに電極が形成された第2の半導体チップであり、前記第1の半導体チップ及び前記第2の半導体チップは、各々の電極が前記中間基板と対向していてもよい。   In the component-embedded substrate, the first electronic component is a first semiconductor chip in which an electrode is formed only on one side, and the second electronic component is a second semiconductor chip in which an electrode is formed only on one side. Each electrode of the first semiconductor chip and the second semiconductor chip may face the intermediate substrate.

上記部品内蔵基板において、第3絶縁層の一方の面に形成された第2配線層、他方の面に設けられた第2接着層及び前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続された第3層間導電層を有する片面基板を備え、前記中間基板の上層又は下層に配置された前記両面基板のいずれか一方の開口部に、両面に電極が形成された第3電子部品が収容され、前記片面基板の前記第3層間導電層は、前記第3電子部品における前記中間基板とは反対の面の電極と接続され、前記片面基板及び前記中間基板が、前記第3電子部品が開口部に収容された両面基板を挟んで積層されていてもよい。   In the component-embedded substrate, the second wiring layer formed on one surface of the third insulating layer, the second adhesive layer provided on the other surface, and the second adhesive layer pass through the third insulating layer and pass through the third insulating layer. A single-sided substrate having a third interlayer conductive layer connected to the second wiring layer is provided, and electrodes are formed on both sides in either one of the openings of the double-sided substrate arranged on the upper layer or lower layer of the intermediate substrate A third electronic component is accommodated, and the third interlayer conductive layer of the single-sided substrate is connected to an electrode on a surface opposite to the intermediate substrate in the third electronic component, and the single-sided substrate and the intermediate substrate are The third electronic component may be stacked with a double-sided substrate accommodated in the opening.

上記部品内蔵基板において、複数の前記第2層間導電層を有し、第1の第2層間導電層と第2の第2層間導電層は径が異なっていてもよい。   The component-embedded substrate may include a plurality of the second interlayer conductive layers, and the first second interlayer conductive layer and the second second interlayer conductive layer may have different diameters.

本発明に係る部品内蔵基板の製造方法は、積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板の製造方法において、第1絶縁層の両面に第1配線層を形成すると共に、前記第1絶縁層を貫通し前記第1配線層と接続される第1層間導電層を形成し、前記第1電子部品又は前記第2電子部品が収容される開口部を形成して両面基板を作製する工程と、第2絶縁層の両面に第1接着層を設けると共に、前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を形成して中間基板を作製する工程と、前記中間基板の上層に前記第1電子部品が収容された両面基板が配置されると共に、前記中間基板の下層に前記第2電子部品が収容された両面基板が配置されるように積層する工程とを備え、前記積層する工程では、前記中間基板の上層に位置する前記第1電子部品の電極と、下層に位置する前記第2電子部品の電極は、前記第2層間導電層を介して直接に接続されるように積層することを特徴とする。   According to another aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate, wherein the first electronic component and the second electronic component are embedded in the stacking direction. Forming a layer, forming a first interlayer conductive layer that penetrates the first insulating layer and is connected to the first wiring layer, and has an opening for accommodating the first electronic component or the second electronic component Forming a double-sided substrate and providing a first adhesive layer on both sides of the second insulating layer, and forming a second interlayer conductive layer penetrating the second insulating layer together with the first adhesive layer; A step of producing a substrate; a double-sided substrate in which the first electronic component is housed in an upper layer of the intermediate substrate; and a double-sided substrate in which the second electronic component is housed in a lower layer of the intermediate substrate. And laminating so that the laminating step The electrodes of the first electronic component located in the upper layer of the intermediate substrate and the electrodes of the second electronic component located in the lower layer are laminated so as to be directly connected via the second interlayer conductive layer. It is characterized by that.

本発明に係る部品内蔵基板の製造方法によれば、本発明に係る部品内蔵基板の製造方法は、積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板の製造方法において、第1絶縁層の両面に第1配線層を形成すると共に、前記第1絶縁層を貫通し前記第1配線層と接続される第1層間導電層を形成し、前記第1電子部品又は前記第2電子部品が収容される開口部を形成して両面基板を作製する工程と、第2絶縁層の両面に第1接着層を設けると共に、前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を形成して中間基板を作製する工程と、前記中間基板の上層に前記第1電子部品が収容された両面基板が配置されると共に、前記中間基板の下層に前記第2電子部品が収容された両面基板が配置されるように積層する工程とを備え、前記積層する工程では、前記中間基板の上層に位置する前記第1電子部品の電極と、下層に位置する前記第2電子部品の電極は、前記第2層間導電層を介して直接に接続されるように積層することにより、製造工程を簡素化しつつ全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスの増加を防ぐ部品内蔵基板を製造することができる。   According to the method for manufacturing a component-embedded substrate according to the present invention, the method for manufacturing a component-embedded substrate according to the present invention includes a multilayer-structured component-embedded substrate in which the first electronic component and the second electronic component are embedded in the stacking direction. In the manufacturing method, a first wiring layer is formed on both surfaces of the first insulating layer, and a first interlayer conductive layer that penetrates the first insulating layer and is connected to the first wiring layer is formed. Forming a double-sided substrate by forming an opening for accommodating a component or the second electronic component; providing a first adhesive layer on both sides of the second insulating layer; and providing the second insulating layer together with the first adhesive layer Forming an intermediate substrate by forming a second interlayer conductive layer penetrating the layer; a double-sided substrate containing the first electronic component disposed in an upper layer of the intermediate substrate; and a lower layer of the intermediate substrate A double-sided board containing the second electronic component is disposed. And laminating, wherein in the laminating step, the electrode of the first electronic component located in the upper layer of the intermediate substrate and the electrode of the second electronic component located in the lower layer are the second interlayer conductive layer By laminating so as to be directly connected via each other, it is possible to reduce the overall thickness while simplifying the manufacturing process, and it is possible to manufacture a component-embedded substrate that prevents an increase in impedance and inductance between electrodes. .

上記部品内蔵基板の製造方法において、前記第1電子部品又は前記第2電子部品のいずれか一方は片面のみに電極が形成された半導体チップであり、前記半導体チップを、電極が前記中間基板と対向するように配置してもよい。   In the method for manufacturing a component-embedded substrate, one of the first electronic component and the second electronic component is a semiconductor chip having an electrode formed on only one side, and the electrode faces the intermediate substrate. You may arrange so that.

上記部品内蔵基板の製造方法において、第3絶縁層の一方の面に第2配線層を形成すると共に、他方の面に第2接着層を設け、前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続される第3層間導電層を形成して片面基板を作製する工程を更に備え、前記第1電子部品又は前記第2電子部品のいずれか一方は両面に電極が形成された電子部品であり、前記積層する工程では、前記片面基板の前記第3層間導電層は、前記両面に電極が形成された電子部品における前記中間基板とは反対の面の電極と接続されると共に、前記片面基板及び前記中間基板が、前記両面に電極が形成された電子部品が開口部に収容された両面基板を挟むように積層してもよい。   In the method for manufacturing a component-embedded substrate, the second wiring layer is formed on one surface of the third insulating layer, the second adhesive layer is provided on the other surface, and the third insulating layer is formed together with the second adhesive layer. A step of forming a single-sided substrate by forming a third interlayer conductive layer that penetrates and is connected to the second wiring layer, wherein either one of the first electronic component and the second electronic component has electrodes on both sides In the stacking step, the third interlayer conductive layer of the single-sided substrate is connected to an electrode on the surface opposite to the intermediate substrate in the electronic component on which the electrodes are formed on both sides. In addition, the single-sided substrate and the intermediate substrate may be laminated so as to sandwich a double-sided substrate in which an electronic component having electrodes formed on both sides is accommodated in an opening.

上記部品内蔵基板の製造方法において、前記第1電子部品は片面のみに電極が形成された第1の半導体チップであると共に、前記第2電子部品は片面のみに電極が形成された第2の半導体チップであり、前記第1の半導体チップ及び前記第2の半導体チップを、各々の電極が前記中間基板と対向するように配置してもよい。   In the method for manufacturing a component-embedded substrate, the first electronic component is a first semiconductor chip in which an electrode is formed only on one side, and the second electronic component is a second semiconductor in which an electrode is formed only on one side. It may be a chip, and the first semiconductor chip and the second semiconductor chip may be arranged such that each electrode faces the intermediate substrate.

上記部品内蔵基板の製造方法において、第3絶縁層の一方の面に第2配線層を形成すると共に、他方の面に第2接着層を設け、前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続される第3層間導電層を形成して片面基板を作製する工程を更に備え、前記中間基板の上層又は下層に配置された前記両面基板のいずれか一方の開口部に、両面に電極が形成された第3電子部品が収容され、前記積層する工程では、前記片面基板の前記第3層間導電層は、前記第3電子部品における前記中間基板とは反対の面の電極と接続されると共に、前記片面基板及び前記中間基板が、前記第3電子部品が開口部に収容された両面基板を挟むように積層してもよい。   In the method for manufacturing a component-embedded substrate, the second wiring layer is formed on one surface of the third insulating layer, the second adhesive layer is provided on the other surface, and the third insulating layer is formed together with the second adhesive layer. A step of forming a single-sided substrate by forming a third interlayer conductive layer that penetrates and is connected to the second wiring layer, and includes either one of the openings of the double-sided substrate disposed in the upper layer or the lower layer of the intermediate substrate In the step, the third electronic component having electrodes formed on both sides is housed, and in the step of laminating, the third interlayer conductive layer of the single-sided substrate is a surface opposite to the intermediate substrate in the third electronic component. The single-sided board and the intermediate board may be laminated so as to sandwich the double-sided board in which the third electronic component is accommodated in the opening.

上記部品内蔵基板の製造方法において、複数の前記第2層間導電層を有し、第1の第2層間導電層と第2の第2層間導電層は径が異なっていてもよい。   In the method for manufacturing a component-embedded substrate, the plurality of second interlayer conductive layers may be provided, and the first second interlayer conductive layer and the second second interlayer conductive layer may have different diameters.

本発明によれば、製造工程を簡素化しつつ部品内蔵基板全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスが増加することを防ぐことができる。   According to the present invention, it is possible to reduce the thickness of the entire component-embedded substrate while simplifying the manufacturing process, and to prevent an increase in impedance and inductance between the electrodes.

本発明の第1の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 1st Embodiment of this invention. 同部品内蔵基板が備える片面基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the single-sided board with which the same component built-in board is provided. 同部品内蔵基板が備える片面基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the single-sided board with which the component built-in board is provided. 同部品内蔵基板が備える両面基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the double-sided board with which the component built-in board | substrate is provided. 同部品内蔵基板が備える両面基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the double-sided board with which the same component built-in board is provided. 同部品内蔵基板が備える中間基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the intermediate board with which the same component built-in board is provided. 同部品内蔵基板が備える中間基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the intermediate board with which the same component built-in board is provided. 同部品内蔵基板の製造工程に含まれる一括積層の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the batch lamination | stacking included in the manufacturing process of the same component built-in substrate. 同部品内蔵基板の製造工程に含まれる一括積層の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the collective lamination | stacking included in the manufacturing process of the same component built-in substrate. 本発明の第2の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 2nd Embodiment of this invention.

以下、添付の図面を参照して、この発明の実施の形態に係る部品内蔵基板及びその製造方法を詳細に説明する。   Hereinafter, a component-embedded substrate and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明の第1の実施形態に係る部品内蔵基板を示す断面図である。図1に示すように、部品内蔵基板1は、複数の単位基板を積層して積層方向に電子部品90〜92を内蔵してなるもので、単位基板としての両面基板10a及び10bと、中間基板20と、片面基板30a及び30bとを、熱圧着により一括積層した構造を備えている。また、部品内蔵基板1において、電子部品90は、両面基板10bに形成された開口部19内に、中間基板20及び片面基板30bに挟まれた状態で内蔵され、電子部品91及び92は、両面基板10aに形成された開口部19内に、中間基板20及び片面基板30aに挟まれた状態で内蔵されている。   FIG. 1 is a cross-sectional view showing a component-embedded substrate according to the first embodiment of the present invention. As shown in FIG. 1, the component-embedded substrate 1 is formed by laminating a plurality of unit substrates and incorporating electronic components 90 to 92 in the stacking direction, and includes double-sided substrates 10a and 10b as unit substrates, and an intermediate substrate. 20 and single-sided substrates 30a and 30b are collectively laminated by thermocompression bonding. In the component built-in substrate 1, the electronic component 90 is built in the opening 19 formed in the double-sided substrate 10b while being sandwiched between the intermediate substrate 20 and the single-sided substrate 30b, and the electronic components 91 and 92 are double-sided. In the opening 19 formed in the board | substrate 10a, it is incorporated in the state pinched | interposed into the intermediate board | substrate 20 and the single-sided board | substrate 30a.

両面基板10aは、フィルム状の第1絶縁層としての樹脂基材11と、この樹脂基材11の両面に形成された第1配線層としての配線12と、中間基板側の配線12及び樹脂基材11を貫通するビアホール2内にめっき形成されて各配線12を接続する第1層間導電層としてのビア13とを備える。また、両面基板10aは、所定箇所において樹脂基材11及び配線12を除去した開口部19を備える。両面基板10bの構成も同様である。   The double-sided board 10a includes a resin base material 11 as a film-like first insulating layer, wirings 12 as first wiring layers formed on both sides of the resin base material 11, wirings 12 and resin bases on the intermediate board side. A via 13 serving as a first interlayer conductive layer is formed by plating in the via hole 2 penetrating the material 11 and connecting each wiring 12. Moreover, the double-sided board 10a includes an opening 19 from which the resin base material 11 and the wiring 12 are removed at a predetermined location. The structure of the double-sided substrate 10b is the same.

中間基板20は、フィルム状の第2絶縁層としての樹脂基材21と、この樹脂基材21の両面に設けられた第1接着層22と、これら第1接着層22及び樹脂基材21を貫通するビアホール3内に充填形成された導電性ペーストからなる第2層間導電層としてのビア23とを備える。   The intermediate substrate 20 includes a resin base material 21 as a film-like second insulating layer, a first adhesive layer 22 provided on both surfaces of the resin base material 21, and the first adhesive layer 22 and the resin base material 21. And a via 23 as a second interlayer conductive layer made of a conductive paste filled in the penetrating via hole 3.

片面基板30aは、フィルム状の第3絶縁層としての樹脂基材31と、この樹脂基材31の片面に形成された第2配線層としての配線32と、樹脂基材31の反対面に設けられた第2接着層22aと、この第2接着層22a及び樹脂基材31を貫通するビアホール4内に充填形成された導電性ペーストからなる第3層間導電層としてのビア33とを備える。片面基板30bの構成も同様である。   The single-sided substrate 30 a is provided on the opposite surface of the resin base 31, the resin base 31 as a film-like third insulating layer, the wiring 32 as the second wiring layer formed on one side of the resin base 31 And a via 33 serving as a third interlayer conductive layer made of a conductive paste filled in the via hole 4 penetrating the second adhesive layer 22a and the resin base material 31. The configuration of the single-sided substrate 30b is the same.

樹脂基材11、21、31は、それぞれ厚さ25μm程度の低誘電率材料の樹脂フィルムにより構成されている。樹脂フィルムとしては、ポリイミド、ポリオレフィン、液晶ポリマー(LCP)等を用いることができる。   The resin base materials 11, 21, and 31 are each composed of a resin film of a low dielectric constant material having a thickness of about 25 μm. As the resin film, polyimide, polyolefin, liquid crystal polymer (LCP), or the like can be used.

配線12、32は、樹脂基材11、31上に形成されている。電子部品90〜92は、トランジスタ、集積回路(IC)、ダイオード等の半導体素子の能動部品や、抵抗器、コンデンサ、リレー、圧電素子等の受動部品からなる。図1に示す電子部品90は半導体チップである。電子部品90の電極形成面には電極90a及び90bが設けられている。また、電子部品91及び92は、両端に電極が形成された能動部品又は受動部品であり、片面基板及び両面基板のいずれの層間導電層とも接続されることができる。   The wirings 12 and 32 are formed on the resin base materials 11 and 31. The electronic components 90 to 92 include active components such as transistors, integrated circuits (ICs), and diodes, and passive components such as resistors, capacitors, relays, and piezoelectric elements. The electronic component 90 shown in FIG. 1 is a semiconductor chip. Electrodes 90 a and 90 b are provided on the electrode forming surface of the electronic component 90. The electronic components 91 and 92 are active components or passive components having electrodes formed at both ends, and can be connected to any one of the interlayer conductive layers of the single-sided substrate and the double-sided substrate.

ビア23、33は、ビアホール3、4内にそれぞれ充填された導電性ペーストからなる。導電性ペーストはニッケル、金、銀、銅、アルミニウム、鉄等からなる選択される少なくとも1種類の金属粒子と、錫、ビスマス、インジウム、鉛等から選択される少なくとも1種類の低融点の金属粒子とを含んでいる。そして、導電性ペーストは、これらの金属粒子にエポキシ、アクリル、ウレタン等を主成分とするバインダ成分を混合したペーストからなる。   The vias 23 and 33 are made of conductive paste filled in the via holes 3 and 4, respectively. The conductive paste is at least one metal particle selected from nickel, gold, silver, copper, aluminum, iron, etc., and at least one low melting metal particle selected from tin, bismuth, indium, lead, etc. Including. The conductive paste is made of a paste obtained by mixing these metal particles with a binder component mainly composed of epoxy, acrylic, urethane or the like.

このように構成された導電性ペーストは、硬化温度が約150℃〜200℃で、硬化後の融点が約260℃以上となる金属焼結型の特性を備え、含有された低融点の金属が200℃以下で溶融し合金を形成することができ、特に銅や銀等とは金属間化合物を形成することができる特性を備えている。従って、ビア23、33と配線12、32との接続部は、一括積層の熱圧着時に金属間化合物により合金化されることとなる。   The conductive paste thus configured has a metal-sintering-type characteristic in which the curing temperature is about 150 ° C. to 200 ° C. and the melting point after curing is about 260 ° C. or more. It can be melted at 200 ° C. or lower to form an alloy, and particularly has the property of forming an intermetallic compound with copper, silver, or the like. Therefore, the connection portions between the vias 23 and 33 and the wirings 12 and 32 are alloyed by an intermetallic compound at the time of batch lamination thermocompression bonding.

なお、導電性ペーストは、粒子径がナノレベルの金、銀、銅、ニッケル等のフィラーが、上記のようなバインダ成分に混合されたナノペーストで構成することもできる。その他、導電性ペーストは、上記ニッケル等の金属粒子が、上記のようなバインダ成分に混合されたペーストで構成することもできる。   The conductive paste can be composed of a nanopaste in which fillers such as gold, silver, copper, and nickel having a nanometer particle size are mixed with the binder component as described above. In addition, the conductive paste can also be configured by a paste in which metal particles such as nickel are mixed with the binder component as described above.

この場合、導電性ペーストは、金属粒子同士が接触することで電気的接続が行なわれる特性となる。なお、導電性ペーストのビアホール3、4内への充填方法としては、印刷工法、スピン塗布工法、スプレー塗布工法、ディスペンス工法、ラミネート工法、及びこれらを併用した工法等を用いることが可能である。   In this case, the conductive paste has a characteristic that electrical connection is made when the metal particles come into contact with each other. As a method for filling the conductive paste into the via holes 3 and 4, it is possible to use a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, and a method using these in combination.

第1の実施形態に係る部品内蔵基板1において、両面基板10a及び10bと片面基板30a及び30bは、中間基板20を挟んで両面基板10a及び10bが配置され、更に片面基板30a及び30bが配置される順番で5層に積層されている。両面基板10bの開口部19に収容された電子部品90は、電極形成面が中間基板20と対向するように配置されている。また、両面基板10aの開口部19に収容された電子部品91及び92の中間基板側の電極91a及び92aは、中間基板20のビア23を介して電子部品90の電極90a及び90bと接続される。   In the component-embedded substrate 1 according to the first embodiment, the double-sided boards 10a and 10b and the single-sided boards 30a and 30b are arranged such that the double-sided boards 10a and 10b are disposed across the intermediate board 20, and the single-sided boards 30a and 30b are further arranged. Are stacked in 5 layers in the order shown. The electronic component 90 housed in the opening 19 of the double-sided board 10b is arranged so that the electrode forming surface faces the intermediate board 20. Further, the electrodes 91a and 92a on the intermediate substrate side of the electronic components 91 and 92 accommodated in the opening 19 of the double-sided substrate 10a are connected to the electrodes 90a and 90b of the electronic component 90 through the vias 23 of the intermediate substrate 20. .

さらに、片面基板30bは、ビア33が両面基板10bの配線12と接続され、配線32が部品内蔵基板1の最外層に位置するように配置されている。片面基板30aは、ビア33の一部が両面基板10aの配線12と接続されると共に他の一部が電子部品91及び92の片面基板側の電極91b及び92bと接続され、配線32が部品内蔵基板1の反対側の最外層に位置するように配置されている。中間基板20と両面基板10a及び10bは、中間基板20の第1接着層22によりそれぞれ接着され、両面基板10a及び10bと片面基板30a及び30bは、片面基板30a及び30bの第2接着層22aによりそれぞれ接着されている。第1及び第2接着層22、22aは、エポキシ系やアクリル系等の揮発成分が含まれた有機系接着材からなる。   Further, the single-sided board 30b is arranged so that the via 33 is connected to the wiring 12 of the double-sided board 10b, and the wiring 32 is located in the outermost layer of the component built-in board 1. In the single-sided board 30a, a part of the via 33 is connected to the wiring 12 of the double-sided board 10a, and the other part is connected to the electrodes 91b and 92b on the single-sided board side of the electronic components 91 and 92. It arrange | positions so that it may be located in the outermost layer of the other side of the board | substrate 1. FIG. The intermediate substrate 20 and the double-sided substrates 10a and 10b are bonded by the first adhesive layer 22 of the intermediate substrate 20, respectively. The double-sided substrates 10a and 10b and the single-sided substrates 30a and 30b are bonded by the second adhesive layer 22a of the single-sided substrates 30a and 30b. Each is glued. The first and second adhesive layers 22 and 22a are made of an organic adhesive material containing a volatile component such as epoxy or acrylic.

本実施形態によれば、積層方向に電子部品90〜92を内蔵してなる多層構造の部品内蔵基板1において、樹脂基材11の両面に形成された配線12、前記樹脂基材11を貫通し前記配線12と接続されたビア13及び前記電子部品91及び92が収容された開口部19を有する両面基板10aと、樹脂基材11の両面に形成された配線12、前記樹脂基材11を貫通し前記配線12と接続されたビア13及び前記電子部品90が収容された開口部19を有する両面基板10bと、樹脂基材21の両面に設けられた第1接着層22及び前記第1接着層22と共に前記樹脂基材21を貫通するビア23を有する中間基板20とを備え、前記中間基板20の上層に前記両面基板10aが、下層に前記両面基板10bがそれぞれ配置され、前記中間基板20の上層に位置する前記電子部品91及び92の電極と、下層に位置する前記電子部品90の電極は、前記ビア23を介して直接に接続されていることにより、製造工程を簡素化しつつ全体の薄型化を図ることができると共に電極間のインピーダンス及びインダクタンスが増加することを防ぐことができる。   According to this embodiment, in the component-embedded substrate 1 having a multilayer structure in which the electronic components 90 to 92 are built in the stacking direction, the wiring 12 formed on both surfaces of the resin base material 11, the resin base material 11 is penetrated. A double-sided board 10a having an opening 19 in which the via 13 connected to the wiring 12 and the electronic components 91 and 92 are accommodated, the wiring 12 formed on both surfaces of the resin base 11, and the resin base 11 are penetrated. The double-sided substrate 10b having the vias 13 connected to the wirings 12 and the openings 19 in which the electronic components 90 are accommodated, the first adhesive layer 22 and the first adhesive layer provided on both surfaces of the resin base 21 22 and an intermediate substrate 20 having a via 23 penetrating through the resin base material 21, the double-sided substrate 10 a is disposed in the upper layer of the intermediate substrate 20, and the double-sided substrate 10 b is disposed in the lower layer. The electrodes of the electronic components 91 and 92 located on the upper layer of the plate 20 and the electrodes of the electronic component 90 located on the lower layer are directly connected via the vias 23, thereby simplifying the manufacturing process. The overall thickness can be reduced, and the impedance and inductance between the electrodes can be prevented from increasing.

また、簡単な構造の両面基板10a及び10b、中間基板20及び片面基板30a及び30bを作製して電子部品90〜92を収容した上で、熱圧着により一括積層して製造することができるので、製造工程を簡素化することができる。更に、開口部19に収容された電子部品90〜92は、周囲を第1及び第2接着層22、22aにより囲まれた状態で内蔵され、電子部品90と電子部品91及び92間には中間基板20の樹脂基材21が介在しているので、積層方向の機械的強度を確保しながら絶縁信頼性を高めることができる。さらに、電子部品90〜92がそれぞれ収容される位置は上記の実施形態に限らず、電子部品90と電子部品91の位置が相互に置き換わったように収容されていてもよい。   In addition, since the double-sided substrates 10a and 10b, the intermediate substrate 20 and the single-sided substrates 30a and 30b having a simple structure are manufactured and the electronic components 90 to 92 are accommodated, they can be collectively laminated and manufactured by thermocompression bonding. The manufacturing process can be simplified. Further, the electronic components 90 to 92 housed in the opening 19 are built in a state surrounded by the first and second adhesive layers 22 and 22 a, and the electronic components 90 and the electronic components 91 and 92 are interposed between them. Since the resin base material 21 of the board | substrate 20 is interposing, insulation reliability can be improved, ensuring the mechanical strength of a lamination direction. Furthermore, the position where each of the electronic components 90 to 92 is accommodated is not limited to the above embodiment, and may be accommodated such that the positions of the electronic component 90 and the electronic component 91 are replaced with each other.

さらに、電子部品90〜92のいずれかの端子に用いられる金属は、接続されるビア23、33の材料と強固な合金を形成するような金属であってもよい。   Furthermore, the metal used for any terminal of the electronic components 90 to 92 may be a metal that forms a strong alloy with the material of the vias 23 and 33 to be connected.

ここで、半導体チップである電子部品90に形成された複数の電極の役割は様々であり、電源供給用、接地用、制御信号用、高周波信号用等がある。制御信号用や高周波信号用の電極は、他の電子部品の電極と配線を介して接続され、その接続先の他の電子部品との間で各種信号の通信が行なわれる。そして、本発明において上記のような通信のための接続形態を実現しようとする場合には、ビア23が、半導体チップである電子部品90と他の電子部品の各電極間を接続する配線の一部を構成する。   Here, the roles of the plurality of electrodes formed on the electronic component 90, which is a semiconductor chip, vary, and include power supply, grounding, control signal, and high-frequency signal. The electrodes for control signals and high-frequency signals are connected to the electrodes of other electronic components via wiring, and various signals are communicated with other electronic components to which the electrodes are connected. In the present invention, when it is intended to realize the connection form for communication as described above, the via 23 is one of the wirings connecting the electronic component 90 which is a semiconductor chip and each electrode of the other electronic component. Parts.

そして、配線の一部を構成するビア23はそれ自体が寄生抵抗や寄生容量を持つため、電子部品90と他の電子部品との間で通信が行なわれる信号の種類によっては、それら寄生抵抗や寄生容量に起因してその信号の波形が影響されることがある。つまり、ビア23内に寄生抵抗が存在し、ビア23とグラウンド間に寄生容量が存在することによりRC等価回路が形成され、信号に対するローパスフィルタとして機能する。但し、このローパスフィルタは悪影響のみならず、好適な影響を及ぼす場合もある。   Since the via 23 constituting a part of the wiring itself has a parasitic resistance and a parasitic capacitance, depending on the type of signal that is communicated between the electronic component 90 and another electronic component, the parasitic resistance or Due to the parasitic capacitance, the signal waveform may be affected. That is, a parasitic resistance exists in the via 23 and a parasitic capacitance exists between the via 23 and the ground, so that an RC equivalent circuit is formed and functions as a low-pass filter for a signal. However, this low-pass filter may not only have an adverse effect but also have a favorable effect.

例えば、電子部品90が他の電子部品と制御信号の通信を行なうためには、そもそも制御信号は低周波のデジタル信号である場合が殆どなので、電極間を接続する配線は高周波信号に対応している必要は無い。このような場合には、ローパスフィルタとして機能することにより制御信号に含まれる高周波のノイズが除去されるので、寄生抵抗や寄生容量は存在した方がよい。逆に、電子部品90が他の電子部品と高周波信号の通信を行なうためには、当然ながらローパスフィルタは通信の阻害要因なので、寄生抵抗や寄生容量の値は小さいほどよい。   For example, in order for the electronic component 90 to communicate control signals with other electronic components, the control signal is mostly a low-frequency digital signal in the first place. Therefore, the wiring connecting the electrodes corresponds to the high-frequency signal. There is no need to be. In such a case, since high frequency noise included in the control signal is removed by functioning as a low-pass filter, it is preferable that a parasitic resistance and a parasitic capacitance exist. On the other hand, in order for the electronic component 90 to communicate high frequency signals with other electronic components, the low-pass filter is naturally a hindrance to communication.

この上で、複数のビア23が存在し、各々に対して要求される寄生抵抗や寄生容量の値が異なる場合もある。すなわち、あるビア23は制御信号の通信用であり、別のビア23は高周波信号の通信用である場合等である。本発明において、ビア23の寄生抵抗や寄生容量の値を異ならせる場合には、ビア23の径を変えることにより寄生抵抗の値を異ならせるのが効率的である。なぜなら、中間基板の厚さは共通なのでビア23の長さを変えることにより寄生抵抗の値を異ならせるのは困難であり、また、寄生容量の値はグラウンドとの距離に大きく左右されるので、寄生容量の値を調整しようとすると設計の自由度が著しく制限されてしまうからである。つまり、制御信号の通信用のビア23は、高周波信号の通信用のビア23よりも相対的に径を小さくすることにより寄生抵抗を大きくすればよいし、高周波信号の通信用のビア23はその逆である。   In addition, there may be a plurality of vias 23, and the values of parasitic resistance and parasitic capacitance required for each may be different. That is, one via 23 is for communication of control signals, and another via 23 is for communication of high-frequency signals. In the present invention, when the values of the parasitic resistance and the parasitic capacitance of the via 23 are made different, it is efficient to make the value of the parasitic resistance different by changing the diameter of the via 23. Because the thickness of the intermediate substrate is common, it is difficult to vary the value of the parasitic resistance by changing the length of the via 23, and the value of the parasitic capacitance greatly depends on the distance from the ground. This is because the degree of freedom of design is significantly limited when the value of the parasitic capacitance is adjusted. That is, the control signal communication via 23 has a relatively smaller diameter than the high-frequency signal communication via 23, and the parasitic resistance can be increased. The reverse is true.

次に、第1の実施形態に係る部品内蔵基板1の製造方法について説明する。図2、図4、図6、図8は、部品内蔵基板を製造工程毎に示す断面図である。また、図3、図5、図7、図9は、部品内蔵基板を製造工程毎に示すフローチャートである。   Next, a manufacturing method of the component built-in substrate 1 according to the first embodiment will be described. 2, 4, 6, and 8 are cross-sectional views showing the component-embedded substrate for each manufacturing process. 3, FIG. 5, FIG. 7, and FIG. 9 are flowcharts showing the component-embedded substrate for each manufacturing process.

まず、図2及び図3を参照することにより片面基板30aの製造工程について説明する。なお、片面基板30bの製造工程についても同様である。   First, the manufacturing process of the single-sided substrate 30a will be described with reference to FIGS. The same applies to the manufacturing process of the single-sided substrate 30b.

図2(a)に示すように、樹脂基材31の片面に銅箔等からなる導体層が形成された片面CCLの導体層上に、フォトリソグラフィによりエッチングレジストを形成後にエッチングを行ない、配線32を形成する(図3のステップS100)。   As shown in FIG. 2A, an etching resist is formed by photolithography on one side CCL conductor layer in which a conductor layer made of copper foil or the like is formed on one side of a resin base material 31, and etching is performed. Is formed (step S100 in FIG. 3).

ここで用いられる片面CCLは、厚さ25μm程度の樹脂基材31に、厚さ12μm程度の銅箔からなる導体層を貼り合わせた構造からなる。この片面CCLとしては、公知のキャスティング法により、銅箔にポリイミドのワニスを塗布してそのワニスを硬化させて作製したものを用いることができる。   The single-sided CCL used here has a structure in which a conductor layer made of a copper foil having a thickness of about 12 μm is bonded to a resin base material 31 having a thickness of about 25 μm. As this single-sided CCL, what was produced by applying a polyimide varnish to a copper foil and curing the varnish by a known casting method can be used.

次に、図2(b)に示すように、樹脂基材31の配線32側と反対面に接着材を貼り付けて、第2接着層22aを形成する(図3のステップS102)。第2接着層22aとしては、厚さ25μm程度のエポキシ系熱硬化性フィルムを用いることができる。なお、接着材は必ずしもフィルム状である必要はなく、ワニス状の樹脂を塗布したものであっても良い。   Next, as shown in FIG. 2B, an adhesive is attached to the surface opposite to the wiring 32 side of the resin base material 31 to form the second adhesive layer 22a (step S102 in FIG. 3). As the second adhesive layer 22a, an epoxy thermosetting film having a thickness of about 25 μm can be used. Note that the adhesive does not necessarily have to be in the form of a film, and may be one in which a varnish-like resin is applied.

そして、図2(c)に示すように、第2接着層22a側から配線32に向かって、UV−YAGレーザ装置を用いてレーザ光を照射して、第2接着層22a及び樹脂基材31を貫通するビアホール4を所定箇所に形成する(図3のステップS104)。なお、形成されたビアホール4内には、形成時にプラズマデスミア処理が施される。   And as shown in FIG.2 (c), it irradiates with a laser beam using the UV-YAG laser apparatus toward the wiring 32 from the 2nd contact bonding layer 22a side, and the 2nd contact bonding layer 22a and the resin base material 31 are shown. A via hole 4 penetrating through is formed at a predetermined location (step S104 in FIG. 3). The formed via hole 4 is subjected to a plasma desmear process at the time of formation.

ビアホール4は、その他、炭酸ガスレーザ(COレーザ)やエキシマレーザ等で形成しても良く、ドリル加工や化学的なエッチング等により形成しても良い。また、プラズマデスミア処理は、CF及びO(四フッ化メタン+酸素)の混合ガスにより行なうことができるが、Ar(アルゴン)等のその他の不活性ガスを用いることもでき、いわゆるドライ処理ではなく、薬液を用いたウェットデスミア処理としても良い。 In addition, the via hole 4 may be formed by a carbon dioxide laser (CO 2 laser), an excimer laser, or the like, or may be formed by drilling or chemical etching. The plasma desmear treatment can be performed with a mixed gas of CF 4 and O 2 (tetrafluoromethane + oxygen), but other inert gas such as Ar (argon) can also be used, so-called dry treatment. Instead, it may be wet desmear treatment using a chemical solution.

ビアホール4を形成後に、図2(d)に示すように、形成したビアホール4内にスクリーン印刷等により導電性ペーストを充填することによりビア33を形成し(図3のステップS106)、第2接着層22aが設けられた樹脂基材31からなる片面基板30aを製造する。   After forming the via hole 4, as shown in FIG. 2D, a via 33 is formed by filling the formed via hole 4 with a conductive paste by screen printing or the like (step S106 in FIG. 3), and the second adhesion A single-sided substrate 30a made of the resin base material 31 provided with the layer 22a is manufactured.

次に、図4及び図5を参照することにより両面基板10a及び10bの製造工程について説明する。まず、樹脂基材11の両面に導体層が形成された両面CCLを準備し(図5のステップS200)、所定箇所にビアホール2を形成して(図5のステップS202)、プラズマデスミア処理を行なう。   Next, a manufacturing process of the double-sided substrates 10a and 10b will be described with reference to FIGS. First, a double-sided CCL having a conductor layer formed on both sides of the resin substrate 11 is prepared (step S200 in FIG. 5), a via hole 2 is formed at a predetermined location (step S202 in FIG. 5), and plasma desmear processing is performed. .

次に、樹脂基材11の全面にめっき処理を施して(図5のステップS204)、導体層上及びビアホール2内にめっき層を形成し、そして、図4(a)に示すように、配線12やビア13を形成する(図5のステップS206)。   Next, the entire surface of the resin base material 11 is plated (step S204 in FIG. 5) to form a plating layer on the conductor layer and in the via hole 2. Then, as shown in FIG. 12 and vias 13 are formed (step S206 in FIG. 5).

その後、図4(b)に示すように、電子部品90〜92が内蔵される部分の樹脂基材11をレーザ光を照射することにより除去し、所定の開口径を有する開口部19を形成して(図5のステップS208)、電子部品90〜92が収容される開口部19を有する両面基板10a及び10bを製造する。   Thereafter, as shown in FIG. 4 (b), the resin base material 11 in the part in which the electronic components 90 to 92 are incorporated is removed by irradiating the laser beam to form an opening 19 having a predetermined opening diameter. (Step S208 in FIG. 5), the double-sided boards 10a and 10b having the openings 19 in which the electronic components 90 to 92 are accommodated are manufactured.

次に、次に、図6及び図7を参照することにより中間基板20の製造工程について説明する。   Next, the manufacturing process of the intermediate substrate 20 will be described with reference to FIGS.

まず、図6(a)に示すように、樹脂基材21の両面に接着材を貼り付けて、第1接着層22を形成する(図7のステップS300)。   First, as shown to Fig.6 (a), an adhesive material is affixed on both surfaces of the resin base material 21, and the 1st contact bonding layer 22 is formed (step S300 of FIG. 7).

次に、図6(b)に示すように、レーザ光を照射して、第1接着層22及び樹脂基材21を貫通するビアホール3を所定箇所に形成し(図7のステップS302)、プラズマデスミア処理を施す。さらに、図6(c)に示すように、形成したビアホール3内に導電性ペーストを充填することによりビア23を形成し(図7のステップS304)、第1接着層22が両面に設けられた樹脂基材21からなる中間基板20を製造する。ここで、上述したように、ビア23の径を変えることにより寄生抵抗の値を異ならせる場合には、図7のステップS302及びS304において形成するビア23の径を変えることになる。   Next, as shown in FIG. 6B, laser light is irradiated to form a via hole 3 penetrating the first adhesive layer 22 and the resin base material 21 at a predetermined location (step S302 in FIG. 7), and plasma Apply desmear treatment. Further, as shown in FIG. 6C, the via 23 is formed by filling the formed via hole 3 with a conductive paste (step S304 in FIG. 7), and the first adhesive layer 22 is provided on both surfaces. The intermediate substrate 20 made of the resin base material 21 is manufactured. Here, as described above, when the value of the parasitic resistance is varied by changing the diameter of the via 23, the diameter of the via 23 formed in steps S302 and S304 in FIG. 7 is changed.

その後、図6(d)に示すように、電子部品90の電極90a及び90bを、中間基板20に形成されたビア23の下側に、電子部品用実装機(図示せず)を用いて位置合わせし、同様に電子部品91及び92の電極91a及び92aをビア23の上側に位置合わせする。そして、中間基板20の第1接着層22及びビア23の導電性ペーストの硬化温度以下の温度で加熱することによって、電子部品90〜92を仮留め接着して搭載する(図7のステップS306)。このようにして電子部品90〜92が搭載された中間基板20を準備しておく。また、電子部品90〜92を中間基板20に搭載する代わりに、電子部品90を片面基板30bに搭載してもよいし、電子部品91及び92を片面基板30aに搭載してもよい。   Thereafter, as shown in FIG. 6D, the electrodes 90a and 90b of the electronic component 90 are positioned below the vias 23 formed in the intermediate substrate 20 using an electronic component mounting machine (not shown). Similarly, the electrodes 91 a and 92 a of the electronic components 91 and 92 are aligned with the upper side of the via 23. Then, the electronic components 90 to 92 are temporarily bonded and mounted by heating at a temperature lower than the curing temperature of the conductive paste of the first adhesive layer 22 and the via 23 of the intermediate substrate 20 (step S306 in FIG. 7). . In this way, the intermediate substrate 20 on which the electronic components 90 to 92 are mounted is prepared. Further, instead of mounting the electronic components 90 to 92 on the intermediate substrate 20, the electronic component 90 may be mounted on the single-sided substrate 30b, or the electronic components 91 and 92 may be mounted on the single-sided substrate 30a.

最後に、図8及び図9を参照することにより一括積層の製造工程について説明する。以上のようにして作製した両面基板10a及び10b、片面基板30a及び30b及び中間基板20を、図8に示すように、中間基板20に搭載された電子部品90〜92と両面基板10a及び10bの各開口部19とを位置合わせすると共に、各ビア33と各配線12及び電子部品91及び92の電極91b及び92bを位置合わせして位置決めし、積層する(図9のステップS400)。   Finally, referring to FIGS. 8 and 9, the manufacturing process of batch lamination will be described. As shown in FIG. 8, the double-sided boards 10a and 10b, the single-sided boards 30a and 30b, and the intermediate board 20 produced as described above are connected to the electronic components 90 to 92 mounted on the intermediate board 20 and the double-sided boards 10a and 10b. The openings 19 are aligned, and the vias 33, the wirings 12, and the electrodes 91b and 92b of the electronic components 91 and 92 are aligned and positioned (step S400 in FIG. 9).

一括積層を熱圧着により行なう場合は真空プレス機を用いて、1kPa以下の減圧雰囲気中にて加熱加圧することで(図9のステップS402)、図1に示すような5層構造の部品内蔵基板1を製造する。一括積層時には、層間や開口部19内の第1及び第2接着層22、22a及び樹脂基材11、21、31等の硬化と同時に、ビアホール3、4内に充填された導電性ペーストの硬化及び合金化が行なわれる。   When batch stacking is performed by thermocompression bonding, a component-embedded substrate having a five-layer structure as shown in FIG. 1 is obtained by applying heat and pressure in a reduced pressure atmosphere of 1 kPa or less using a vacuum press machine (step S402 in FIG. 9). 1 is produced. At the time of collective lamination, the conductive paste filled in the via holes 3 and 4 is cured simultaneously with the curing of the first and second adhesive layers 22 and 22a and the resin base materials 11, 21, and 31 in the openings 19. And alloying takes place.

従って、導電性ペーストからなるビア23、33と、配線12、32や電極90a、90b、91a、91b、92a及び92bとの間には、金属間化合物の合金層が形成される。これにより、ビア23、33と配線12、32等との接続部の機械的強度を高めることができると共に、確実に接続して接続信頼性を高めることができる。ここで、上述したように、電子部品90〜92のいずれかの端子に用いられる金属は、接続されるビア23、33の材料と強固な合金を形成するような金属であってもよい。また、各基板10a及び10b、20、30a及び30bの積層処理は、熱圧着による一括積層に限定されるものではない。   Therefore, an alloy layer of an intermetallic compound is formed between the vias 23 and 33 made of a conductive paste and the wirings 12 and 32 and the electrodes 90a, 90b, 91a, 91b, 92a, and 92b. As a result, the mechanical strength of the connecting portion between the vias 23 and 33 and the wirings 12 and 32 can be increased, and the connection reliability can be increased by reliably connecting. Here, as described above, the metal used for any terminal of the electronic components 90 to 92 may be a metal that forms a strong alloy with the material of the vias 23 and 33 to be connected. Moreover, the lamination process of each board | substrate 10a and 10b, 20, 30a, and 30b is not limited to the batch lamination by thermocompression bonding.

図10は、本発明の第2の実施形態に係る部品内蔵基板を示す断面図である。第2の実施形態に係る部品内蔵基板1Aは、第1の実施形態に係る部品内蔵基板1と比較して電子部品90の代わりに電子部品93が、電子部品91の代わりに電子部品94が搭載されている点が相違する。また、電子部品93及び94は共に半導体チップであり、電極形成面が中間基板20と対向するようにそれぞれ配置されており、電極93a及び93bはそれぞれ中間基板20のビア23を介して電極94a及び94bと接続される。   FIG. 10 is a cross-sectional view showing a component built-in substrate according to a second embodiment of the present invention. Compared with the component built-in substrate 1 according to the first embodiment, the component built-in substrate 1 </ b> A according to the second embodiment includes an electronic component 93 instead of the electronic component 90 and an electronic component 94 instead of the electronic component 91. Is different. The electronic components 93 and 94 are both semiconductor chips, and are arranged so that the electrode formation surface faces the intermediate substrate 20. The electrodes 93 a and 93 b are respectively connected to the electrodes 94 a and 93 via the vias 23 of the intermediate substrate 20. 94b.

第2の実施形態においても、複数のビア23の各々に対して要求される寄生抵抗の値が異なる場合がある。すなわち、あるビア23は制御信号の通信用であり、別のビア23は高周波信号の通信用である場合には、制御信号の通信用のビア23は、高周波信号の通信用のビア23よりも相対的に径を小さくすることにより寄生抵抗を大きくすればよいし、高周波信号の通信用のビア23はその逆である。それにより寄生抵抗の値を異ならせることができる。   Also in the second embodiment, the value of the parasitic resistance required for each of the plurality of vias 23 may be different. That is, when one via 23 is for control signal communication and another via 23 is for high-frequency signal communication, the control signal communication via 23 is higher than the high-frequency signal communication via 23. The parasitic resistance may be increased by relatively reducing the diameter, and the via 23 for high-frequency signal communication is reversed. Thereby, the value of the parasitic resistance can be varied.

なお、以上説明した実施形態は、本発明の理解を容易にするために記載されたものであって、本発明を限定するために記載されたものではない。したがって、上記の実施形態に開示された各要素は、本発明の技術的範囲に属する全ての設計変更や均等物をも含む趣旨である。   The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

1、1A・・・部品内蔵基板
10a、10b・・・両面基板
20・・・中間基板
30a、30b・・・片面基板
11、21、31・・・樹脂基材
12、32・・・配線
2、3、4・・・ビアホール
13、23、33・・・ビア
22、22a・・・接着層
19・・・開口部
90、91、92、93、94・・・電子部品
90a、90b、91a、91b、92a、92b、
93a、93b、93c、94a、94b・・・電極
DESCRIPTION OF SYMBOLS 1, 1A ... Component built-in board 10a, 10b ... Double-sided board 20 ... Intermediate board 30a, 30b ... Single-sided board 11, 21, 31 ... Resin base material 12, 32 ... Wiring 2 3, 4, ... Via holes 13, 23, 33 ... Vias 22, 22a ... Adhesive layer 19 ... Openings 90, 91, 92, 93, 94 ... Electronic components 90a, 90b, 91a 91b, 92a, 92b,
93a, 93b, 93c, 94a, 94b ... electrodes

Claims (12)

積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板において、
第1絶縁層の両面に形成された第1配線層、前記第1絶縁層を貫通し前記第1配線層と接続された第1層間導電層及び前記第1電子部品又は前記第2電子部品が収容された開口部を有する両面基板と、
第2絶縁層の両面に設けられた第1接着層及び前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を有する中間基板とを備え、
前記中間基板の上層及び下層に前記両面基板がそれぞれ配置され、
前記中間基板の上層に位置する前記第1電子部品の電極前記第2層間導電層の上側と直接接続され、下層に位置する前記第2電子部品の電極は、前記第2層間導電層の下側と接接続されている
ことを特徴とする部品内蔵基板。
In the component-embedded substrate having a multilayer structure in which the first electronic component and the second electronic component are built in the stacking direction,
A first wiring layer formed on both surfaces of the first insulating layer; a first interlayer conductive layer penetrating the first insulating layer and connected to the first wiring layer; and the first electronic component or the second electronic component. A double-sided substrate having an accommodated opening;
A first adhesive layer provided on both surfaces of the second insulating layer, and an intermediate substrate having a second interlayer conductive layer penetrating the second insulating layer together with the first adhesive layer;
The double-sided substrates are respectively disposed on the upper layer and the lower layer of the intermediate substrate,
The first electrode of the electronic component positioned in the upper layer of the intermediate substrate, the connected second direct and upper interlayer conductive layer, the second electronic component electrode located on the lower layer, the second interlayer conductive layer a substrate having built-in components, characterized in that it is continued lower and straight Sesse'.
前記第1電子部品又は前記第2電子部品のいずれか一方は片面のみに電極が形成された半導体チップであり、
前記半導体チップは、電極が前記中間基板と対向している
ことを特徴とする請求項1記載の部品内蔵基板。
Either one of the first electronic component or the second electronic component is a semiconductor chip in which an electrode is formed only on one side,
2. The component built-in substrate according to claim 1, wherein the semiconductor chip has an electrode facing the intermediate substrate.
第3絶縁層の一方の面に形成された第2配線層、他方の面に設けられた第2接着層及び前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続された第3層間導電層を有する片面基板を備え、
前記第1電子部品又は前記第2電子部品のいずれか一方は両面に電極が形成された電子部品であり、
前記片面基板の前記第3層間導電層は、前記両面に電極が形成された電子部品における前記中間基板とは反対の面の電極と接続され、
前記片面基板及び前記中間基板が、前記両面に電極が形成された電子部品が開口部に収容された両面基板を挟んで積層されている
ことを特徴とする請求項1又は2記載の部品内蔵基板。
A second wiring layer formed on one surface of the third insulating layer, a second adhesive layer provided on the other surface, and the second adhesive layer penetrating through the third insulating layer and connected to the second wiring layer A single-sided substrate having a third interlayer conductive layer formed,
Either one of the first electronic component or the second electronic component is an electronic component having electrodes formed on both sides,
The third interlayer conductive layer of the single-sided substrate is connected to an electrode on the opposite side of the intermediate substrate in the electronic component having electrodes formed on the both sides,
3. The component-embedded substrate according to claim 1, wherein the single-sided substrate and the intermediate substrate are laminated with a double-sided substrate in which an electronic component having electrodes formed on both sides is accommodated in an opening. .
前記第1電子部品は片面のみに電極が形成された第1の半導体チップであると共に、前記第2電子部品は片面のみに電極が形成された第2の半導体チップであり、
前記第1の半導体チップ及び前記第2の半導体チップは、各々の電極が前記中間基板と対向している
ことを特徴とする請求項1記載の部品内蔵基板。
The first electronic component is a first semiconductor chip in which an electrode is formed only on one side, and the second electronic component is a second semiconductor chip in which an electrode is formed only on one side,
2. The component-embedded substrate according to claim 1, wherein each of the first semiconductor chip and the second semiconductor chip has an electrode facing the intermediate substrate.
第3絶縁層の一方の面に形成された第2配線層、他方の面に設けられた第2接着層及び前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続された第3層間導電層を有する片面基板を備え、
前記中間基板の上層又は下層に配置された前記両面基板のいずれか一方の開口部に、両面に電極が形成された第3電子部品が収容され、
前記片面基板の前記第3層間導電層は、前記第3電子部品における前記中間基板とは反対の面の電極と接続され、
前記片面基板及び前記中間基板が、前記第3電子部品が開口部に収容された両面基板を挟んで積層されている
ことを特徴とする請求項1、2又は4記載の部品内蔵基板。
A second wiring layer formed on one surface of the third insulating layer, a second adhesive layer provided on the other surface, and the second adhesive layer penetrating through the third insulating layer and connected to the second wiring layer A single-sided substrate having a third interlayer conductive layer formed,
Wherein the one opening any of the double-sided substrate disposed on a straight upper or straight lower intermediate substrate, the third electronic component having electrodes formed on both sides is accommodated,
The third interlayer conductive layer of the single-sided substrate is connected to an electrode on a surface opposite to the intermediate substrate in the third electronic component,
5. The component-embedded substrate according to claim 1, wherein the single-sided substrate and the intermediate substrate are stacked with a double-sided substrate in which the third electronic component is accommodated in an opening.
複数の前記第2層間導電層を有し、第1の第2層間導電層と第2の第2層間導電層は径が異なる
ことを特徴とする請求項1ないし5記載の部品内蔵基板。
6. The component-embedded substrate according to claim 1, wherein the component-embedded substrate has a plurality of the second interlayer conductive layers, and the first second interlayer conductive layer and the second second interlayer conductive layer have different diameters.
積層方向に第1電子部品及び第2電子部品を内蔵してなる多層構造の部品内蔵基板の製造方法において、
第1絶縁層の両面に第1配線層を形成すると共に、前記第1絶縁層を貫通し前記第1配線層と接続される第1層間導電層を形成し、前記第1電子部品又は前記第2電子部品が収容される開口部を形成して両面基板を作製する工程と、
第2絶縁層の両面に第1接着層を設けると共に、前記第1接着層と共に前記第2絶縁層を貫通する第2層間導電層を形成して中間基板を作製する工程と、
前記第1電子部品をその電極が前記第2層間導電層の下側と直接接続されるように位置合わせして実装すると共に、前記第2電子部品をその電極が該第2層間導電層の上側と直接接続されるように位置合わせして実装する工程と、
前記第1電子部品及び前記第2電子部品が実装された前記中間基板の上層に前記第1電子部品が前記開口部に収容された状態で両面基板が配置されると共に、前記中間基板の下層に前記第2電子部品が前記開口部に収容された状態で両面基板が配置されるように積層する工程とを備え
ことを特徴とする部品内蔵基板の製造方法。
In the manufacturing method of the component-embedded substrate having a multilayer structure in which the first electronic component and the second electronic component are embedded in the stacking direction,
A first wiring layer is formed on both surfaces of the first insulating layer, and a first interlayer conductive layer that penetrates the first insulating layer and is connected to the first wiring layer is formed, and the first electronic component or the first insulating layer is formed. Forming a double-sided substrate by forming an opening for accommodating two electronic components;
Providing a first adhesive layer on both sides of the second insulating layer, and forming a second interlayer conductive layer penetrating the second insulating layer together with the first adhesive layer to produce an intermediate substrate;
The first electronic component is mounted so that the electrode is directly connected to the lower side of the second interlayer conductive layer, and the second electronic component is mounted on the upper side of the second interlayer conductive layer. A process of aligning and mounting so as to be directly connected to,
With double-sided substrate are arranged in a state where the first electronic component and the first electronic component on the upper layer of the second said intermediate substrate on which electronic parts are mounted is accommodated in the opening, the lower layer of the intermediate substrate method for manufacturing a component-embedded substrate, wherein <br/> said second electronic component and a step of laminating such that double-sided substrate is placed in a state of being accommodated in the opening.
前記第1電子部品又は前記第2電子部品のいずれか一方は片面のみに電極が形成された半導体チップであり、
前記半導体チップを、電極が前記中間基板と対向するように配置する
ことを特徴とする請求項7記載の部品内蔵基板の製造方法。
Either one of the first electronic component or the second electronic component is a semiconductor chip in which an electrode is formed only on one side,
8. The method of manufacturing a component-embedded substrate according to claim 7, wherein the semiconductor chip is disposed so that an electrode faces the intermediate substrate.
第3絶縁層の一方の面に第2配線層を形成すると共に、他方の面に第2接着層を設け、前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続される第3層間導電層を形成して片面基板を作製する工程を更に備え、
前記第1電子部品又は前記第2電子部品のいずれか一方は両面に電極が形成された電子部品であり、
前記積層する工程では、前記片面基板の前記第3層間導電層は、前記両面に電極が形成された電子部品における前記中間基板とは反対の面の電極と接続されると共に、前記片面基板及び前記中間基板が、前記両面に電極が形成された電子部品が開口部に収容された両面基板を挟むように積層する
ことを特徴とする請求項7又は8記載の部品内蔵基板の製造方法。
A second wiring layer is formed on one surface of the third insulating layer, a second adhesive layer is provided on the other surface, and the second insulating layer is connected to the second wiring layer through the third insulating layer together with the second adhesive layer. Forming a single-sided substrate by forming a third interlayer conductive layer,
Either one of the first electronic component or the second electronic component is an electronic component having electrodes formed on both sides,
In the laminating step, the third interlayer conductive layer of the single-sided substrate is connected to an electrode on a surface opposite to the intermediate substrate in the electronic component having electrodes formed on both sides, and the single-sided substrate and the single-sided substrate 9. The method of manufacturing a component built-in substrate according to claim 7, wherein the intermediate substrate is laminated so as to sandwich the double-sided substrate in which the electronic component having electrodes formed on both sides is accommodated in the opening.
前記第1電子部品は片面のみに電極が形成された第1の半導体チップであると共に、前記第2電子部品は片面のみに電極が形成された第2の半導体チップであり、
前記第1の半導体チップ及び前記第2の半導体チップを、各々の電極が前記中間基板と対向するように配置する
ことを特徴とする請求項7記載の部品内蔵基板の製造方法。
The first electronic component is a first semiconductor chip in which an electrode is formed only on one side, and the second electronic component is a second semiconductor chip in which an electrode is formed only on one side,
8. The method of manufacturing a component-embedded board according to claim 7, wherein the first semiconductor chip and the second semiconductor chip are arranged so that each electrode faces the intermediate board.
第3絶縁層の一方の面に第2配線層を形成すると共に、他方の面に第2接着層を設け、前記第2接着層と共に前記第3絶縁層を貫通し前記第2配線層と接続される第3層間導電層を形成して片面基板を作製する工程を更に備え、
前記中間基板の上層又は下層に配置された前記両面基板のいずれか一方の開口部に、両面に電極が形成された第3電子部品が収容され、
前記積層する工程では、前記片面基板の前記第3層間導電層は、前記第3電子部品における前記中間基板とは反対の面の電極と接続されると共に、前記片面基板及び前記中間基板が、前記第3電子部品が開口部に収容された両面基板を挟むように積層する
ことを特徴とする請求項7、8又は10記載の部品内蔵基板の製造方法。
A second wiring layer is formed on one surface of the third insulating layer, a second adhesive layer is provided on the other surface, and the second insulating layer is connected to the second wiring layer through the third insulating layer together with the second adhesive layer. Forming a single-sided substrate by forming a third interlayer conductive layer,
Wherein the one opening any of the double-sided substrate disposed on a straight upper or straight lower intermediate substrate, the third electronic component having electrodes formed on both sides is accommodated,
In the laminating step, the third interlayer conductive layer of the single-sided substrate is connected to an electrode on the surface opposite to the intermediate substrate in the third electronic component, and the single-sided substrate and the intermediate substrate are 11. The method of manufacturing a component-embedded substrate according to claim 7, wherein the third electronic component is laminated so as to sandwich a double-sided substrate accommodated in the opening.
複数の前記第2層間導電層を有し、第1の第2層間導電層と第2の第2層間導電層は径が異なる
ことを特徴とする請求項7ないし11記載の部品内蔵基板の製造方法。
12. The component-embedded substrate according to claim 7, wherein a plurality of the second interlayer conductive layers are provided, and the first second interlayer conductive layer and the second second interlayer conductive layer have different diameters. Method.
JP2014234748A 2014-11-19 2014-11-19 Component built-in substrate and manufacturing method thereof Active JP5913535B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014234748A JP5913535B1 (en) 2014-11-19 2014-11-19 Component built-in substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014234748A JP5913535B1 (en) 2014-11-19 2014-11-19 Component built-in substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP5913535B1 true JP5913535B1 (en) 2016-04-27
JP2016100408A JP2016100408A (en) 2016-05-30

Family

ID=55808287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014234748A Active JP5913535B1 (en) 2014-11-19 2014-11-19 Component built-in substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5913535B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018026435A (en) * 2016-08-09 2018-02-15 株式会社村田製作所 Board with built-in component

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012054436A (en) * 2010-09-02 2012-03-15 Murata Mfg Co Ltd Method of manufacturing substrate with built-in component
WO2012046829A1 (en) * 2010-10-08 2012-04-12 株式会社村田製作所 Substrate with built-in component, and method for producing said substrate
JP2013020993A (en) * 2011-07-07 2013-01-31 Murata Mfg Co Ltd Manufacturing method of component built-in substrate
WO2013047520A1 (en) * 2011-09-30 2013-04-04 株式会社フジクラ Component embedded substrate mounting body, method for manufacturing same and component embedded substrate
JP5526276B1 (en) * 2013-02-19 2014-06-18 株式会社フジクラ Component-embedded substrate, manufacturing method thereof, and mounting body

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012054436A (en) * 2010-09-02 2012-03-15 Murata Mfg Co Ltd Method of manufacturing substrate with built-in component
WO2012046829A1 (en) * 2010-10-08 2012-04-12 株式会社村田製作所 Substrate with built-in component, and method for producing said substrate
JP2013020993A (en) * 2011-07-07 2013-01-31 Murata Mfg Co Ltd Manufacturing method of component built-in substrate
WO2013047520A1 (en) * 2011-09-30 2013-04-04 株式会社フジクラ Component embedded substrate mounting body, method for manufacturing same and component embedded substrate
JP5526276B1 (en) * 2013-02-19 2014-06-18 株式会社フジクラ Component-embedded substrate, manufacturing method thereof, and mounting body

Also Published As

Publication number Publication date
JP2016100408A (en) 2016-05-30

Similar Documents

Publication Publication Date Title
JP5526276B1 (en) Component-embedded substrate, manufacturing method thereof, and mounting body
JP3709882B2 (en) Circuit module and manufacturing method thereof
JP5583828B1 (en) Electronic component built-in multilayer wiring board and method for manufacturing the same
JP3910387B2 (en) Semiconductor package, manufacturing method thereof, and semiconductor device
JPH1145955A (en) Device built-in multilayered printed circuit board and its manufacture
JP2008270532A (en) Substrate with built-in inductor and manufacturing method thereof
US9699921B2 (en) Multi-layer wiring board
US20150351218A1 (en) Component built-in board and method of manufacturing the same, and mounting body
JP5406322B2 (en) Electronic component built-in multilayer wiring board and method for manufacturing the same
JP6315681B2 (en) Component-embedded substrate, manufacturing method thereof, and mounting body
JP5913535B1 (en) Component built-in substrate and manufacturing method thereof
JP5491991B2 (en) Multilayer wiring board and manufacturing method thereof
JP5385699B2 (en) Manufacturing method of multilayer wiring board
JP5836019B2 (en) Component built-in substrate and manufacturing method thereof
JP6998744B2 (en) Built-in component board
JP6062884B2 (en) Component-embedded substrate, manufacturing method thereof, and mounting body
US9826646B2 (en) Component built-in board and method of manufacturing the same, and mounting body
JP6313804B2 (en) Component built-in board
JP5408754B1 (en) Multilayer wiring board and manufacturing method thereof
JP2014045092A (en) Substrate with built-in component
JP2004095851A (en) Wiring board
JP5311162B1 (en) Manufacturing method of component mounting board
JP2014027083A (en) Multilayer printed wiring board
JP2014204088A (en) Multilayer wiring board and method of manufacturing the same
JP2015032694A (en) Manufacturing method for component built-in substrate

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160322

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160401

R150 Certificate of patent or registration of utility model

Ref document number: 5913535

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250