JP6313804B2 - Component built-in board - Google Patents

Description

  The present invention relates to a component-embedded substrate that incorporates an electronic component.

  In order to meet the demand for further miniaturization and higher performance centered on recent small precision electronic devices, semiconductor devices mounted on a substrate are also required to be miniaturized and highly integrated. In response to such demands, there is a need to cope with high integration while miniaturizing semiconductor devices by using three-dimensional package technology such as CoC (Chip on Chip) and PoP (Package on Package) and component-embedded substrate technology. It is increasing.

  Among such techniques, a component-embedded substrate disclosed in Patent Document 1 below is known as a technology using the component-embedded substrate technology. This component-embedded substrate can bond and electrically connect structures disposed above and below the intermediate substrate in the stacking direction by an adhesive layer provided on both sides of the intermediate substrate and an interlayer connection via formed by a through structure. it can. As described above, after batch stacking, a plurality of electronic components are built in different layers by a single cure press, and a component built-in substrate having a complex multilayer structure is manufactured in the same process as the conventional process.

Japanese Patent No. 5526276

  Incidentally, in the component-embedded substrate disclosed in Patent Document 1, an adhesive layer made of an adhesive is used for interlayer connection. For this reason, the adhesive material flows and flows into the gap between the electronic component and the opening that accommodates the electronic component during press curing, and as a result, unevenness of the surface shape occurs. In particular, in this component-embedded substrate, openings and electronic components of different layers are provided at substantially the same position in the stacking direction when viewed from above. Therefore, although formed in different layers, the total volume of the gaps in the overlapping portion in the stacking direction is maximized around the periphery of the electronic component.

  In this case, the flow of the adhesive on the inner layer side is limited to some extent by the intermediate substrate or the like, but the adhesive on the surface layer generally flows into the gaps described above. As a result, compared to a component-embedded substrate in which an electronic component is embedded only in a single layer, deformation due to a surface shape depression on the surface layer side of each gap is increased, and coplanarity (coplanarity: coplanarity, uniformity, flatness) is increased. Sometimes it became extremely bad. Generally, in order to surface-mount a fine-pitch mounting component, good coplanarity is required. Therefore, if surface mounting is performed in a state where the coplanarity is poor, mounting defects may occur during mounting. There is.

  The present invention eliminates the above-mentioned problems caused by the prior art, reduces the overall thickness while simplifying the manufacturing process, and improves the coplanarity of the surface shape to prevent surface mounting defects. The purpose is to provide.

  One component-embedded substrate according to the present invention is a component-embedded substrate having a multilayer structure having a plurality of stacked unit substrates and incorporating a plurality of electronic components in the stacking direction, wherein the plurality of unit substrates are A first substrate having a first insulating layer and having a first opening containing a first electronic component; and a second opening having a second insulating layer and containing a second electronic component. A second substrate provided, and an intermediate substrate disposed between the first and second substrates and provided with a third insulating layer and a first adhesive layer provided on both sides of the third insulating layer, The first and second openings are formed in a state in which the inner peripheral surfaces of the respective openings do not form the same plane along the stacking direction.

  In one embodiment of the present invention, the opening central axes of the first and second openings overlap each other in the stacking direction.

  In another embodiment of the present invention, the opening central axes of the first and second openings do not overlap with the stacking direction.

  In still another embodiment of the present invention, the first and second openings are formed in a state where one of them is rotationally moved in a plane orthogonal to the other opening central axis.

  In still another embodiment of the present invention, the first and second openings are formed such that one of them is translated in a plane perpendicular to the other opening central axis.

  In still another embodiment of the present invention, the first and second electronic components are accommodated in a state in which the outer peripheral surfaces of the respective outer shapes do not form the same plane along the stacking direction.

  In still another embodiment of the present invention, the first and second electronic components are accommodated in a state in which the outer peripheral surfaces of the respective external components form the same plane along the stacking direction.

  Another component-embedded substrate according to the present invention is a component-embedded substrate having a multilayer structure that includes a plurality of stacked unit substrates and that includes a plurality of electronic components in the stacking direction. A first substrate having a first insulating layer and having a first opening containing a first electronic component; and a second opening having a second insulating layer and containing a second electronic component. A second substrate provided, and an intermediate substrate disposed between the first and second substrates and provided with a third insulating layer and a first adhesive layer provided on both sides of the third insulating layer, The first and second electronic components are housed in a state in which their outer peripheral surfaces do not form the same plane along the stacking direction.

  In one embodiment of the present invention, the first and second electronic components have respective component central axes overlapping in the stacking direction.

  In another embodiment of the present invention, the first and second electronic components do not have their component central axes overlapping in the stacking direction.

  In still another embodiment of the present invention, the first and second electronic components are accommodated in a state where one of them is rotationally moved in a plane orthogonal to the other component central axis.

  In still another embodiment of the present invention, the first and second electronic components are accommodated in a state where one of them is translated in a plane orthogonal to the other component central axis.

  In still another embodiment of the present invention, the first and second openings are formed such that the inner peripheral surfaces of the openings form the same plane along the stacking direction.

  In still another embodiment of the present invention described above, the first substrate is formed in a state of penetrating the first wiring layer formed on both sides of the first insulating layer and the first insulating layer. A first double-sided substrate having a first interlayer conductive layer connected to one wiring layer, wherein the second substrate includes a second wiring layer formed on both sides of the second insulating layer and the second insulating layer; A third interlayer conductive layer comprising a second double-sided substrate having a second interlayer conductive layer connected to the second wiring layer in a penetrating state, wherein the intermediate substrate penetrates the third insulating layer together with the first adhesive layer. Having a layer.

  Further, in still another embodiment of the present invention described above, the plurality of unit substrates pass through the third wiring layer and the fourth insulating layer formed on one surface side of the fourth insulating layer. A first single-sided substrate having a fourth interlayer conductive layer connected to the third wiring layer and including a second adhesive layer provided on the other surface side of the fourth insulating layer; In the substrate, a part of the fourth interlayer conductive layer is connected to the first electronic component on the second adhesive layer side.

  Furthermore, in still another embodiment of the present invention described above, the plurality of unit substrates penetrate the fourth wiring layer and the fifth insulating layer formed on one surface side of the fifth insulating layer. A second single-sided substrate having a fifth interlayer conductive layer connected to the fourth wiring layer and having a third adhesive layer provided on the other surface side of the fifth insulating layer; In the substrate, a part of the fifth interlayer conductive layer is connected to the second electronic component on the third adhesive layer side.

  According to the present invention, it is possible to reduce the overall thickness while simplifying the manufacturing process and improve the coplanarity of the surface shape to prevent surface mounting defects.

It is a section and a top view showing a component built-in substrate concerning a 1st embodiment of the present invention. It is sectional drawing which shows the component built-in board | substrate. It is a flowchart which shows the manufacturing process of the same component built-in board. It is a flowchart which shows the manufacturing process of the same component built-in board. It is a flowchart which shows the manufacturing process of the same component built-in board. It is a flowchart which shows the manufacturing process of the same component built-in board. It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. It is sectional drawing which shows the 1st modification of the same component-embedded substrate. It is sectional drawing which shows the 2nd modification of the component built-in board | substrate. It is a top view which shows the other modification of the component built-in board | substrate. It is a section and a top view showing a component built-in substrate concerning a 2nd embodiment of the present invention. It is a section and a top view showing a component built-in substrate concerning a 3rd embodiment of the present invention. It is a top view which shows the modification of the same component built-in board | substrate. It is a section and a top view showing a component built-in substrate concerning a 4th embodiment of the present invention. It is a top view which shows the modification of the same component built-in board | substrate. It is a top view which shows the component built-in board | substrate which concerns on other embodiment of this invention.

  Hereinafter, a component-embedded substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view and a plan view showing a component-embedded substrate 1 according to a first embodiment of the present invention, and FIG. 1 (a) shows a cross-section along the line AA ′ in the plan view of FIG. 1 (b). ing. FIG. 2 is a cross-sectional view showing the component built-in substrate 1 and shows a cross section taken along line BB ′ in the plan view of FIG. Since the cross section shown in FIG. 1A differs from the cross section shown in FIG. 2 in FIG. 1A, in FIG. 1A, an electrode 91 of a second electronic component 90 and a via on the second single-sided board 30B described later. A part of 34 is illustrated by a virtual line in which the formation position and the arrangement position are simplified.

  As shown in FIG. 1A, the component-embedded substrate 1 is formed by stacking a plurality of unit substrates and incorporating a plurality of electronic components in the stacking direction. The component-embedded substrate 1 includes a first double-sided board 10A and a second double-sided board 10B that are a plurality of double-sided boards as unit boards, an intermediate board 20, a first single-sided board 30A that is a plurality of single-sided boards, and a second single-sided board. 30B and the 3rd single-sided board | substrate 30C are provided with the structure laminated | stacked collectively, for example by thermocompression bonding.

  In the component-embedded substrate 1 of this embodiment, a first double-sided board 10A that functions as a first board is disposed below the intermediate board 20 in the stacking direction, and a first single-sided board 30A is disposed below the first double-sided board 10A. ing. On the other hand, a second double-sided substrate 10B that functions as a second substrate is disposed above the intermediate substrate 20 in the stacking direction, and a second single-sided substrate 30B is disposed between the second double-sided substrate 10B and the intermediate substrate 20. Is arranged. The third single-sided substrate 30C is disposed on the uppermost layer.

  As the plurality of electronic components, a first electronic component 80 and a second electronic component 90 are incorporated. The first electronic component 80 is placed in the first opening 89 formed in the first double-sided substrate 10A, for example, with the back surface 81a facing upward in the stacking direction and the electrode forming surface 81b facing downward in the stacking direction. It is housed in a facing state. In the second opening 99 formed in the second double-sided substrate 10B, the second electronic component 90 has a back surface 91a side on the upper side in the stacking direction and an electrode formation surface 91b side in the same manner as the first electronic component 80. Are stored in a state in which they are directed downward in the stacking direction.

  The first and second double-sided substrates 10A and 10B are respectively a film-shaped first insulating layer and a resin base material 11 as a second insulating layer, and first wiring layers formed on both sides of the resin base material 11, respectively. And a wiring 12 as a second wiring layer. Further, the first and second double-sided substrates 10A and 10B include a first interlayer conductive layer formed by plating in the via hole 2 that penetrates the wiring 12 on one surface side of each resin base material 11 together with the resin base material 11, and the first interlayer conductive layer. Vias 13 are provided as two-layer conductive layers. The vias 13 electrically connect the wirings 12 on both sides of the resin base material 11.

  The wiring 12 actually has a double structure in which a plating layer is formed on a conductor layer as described above, but the illustration thereof is omitted. Further, the first and second openings 89 and 99 of the first and second double-sided substrates 10A and 10B are formed by removing the resin base material 11 and the wiring 12 at predetermined locations, respectively.

  The intermediate substrate 20 includes a resin base material 21 as a film-like third insulating layer and an adhesive layer 22 as a first adhesive layer provided on both sides of the resin base material 21. Further, the intermediate substrate 20 includes vias 23 as third interlayer conductive layers made of a conductive paste filled in the via holes 3 penetrating the adhesive layer 22 and the resin base material 21.

  The first and second single-sided substrates 30A and 30B are respectively a resin base 31 as a film-like fourth insulating layer and a fifth insulating layer, and a third wiring formed on one surface side of the resin base 31 And a wiring 32 as a fourth wiring layer. The first and second single-sided substrates 30 </ b> A and 30 </ b> B include a second adhesive layer and an adhesive layer 33 as a third adhesive layer provided on the other surface side of each resin base material 31.

  Further, the first and second single-sided substrates 30A and 30B have via holes 34 as the fourth and fifth interlayer conductive layers filled in the via holes 4 penetrating the resin base material 31 together with the adhesive layer 33, respectively. Prepare. The third single-sided substrate 30C arranged in the uppermost layer is configured in the same manner as the first and second single-sided substrates 30A and 30B.

  Specifically, the third single-sided substrate 30C includes a resin base 31 as a film-like sixth insulating layer, and a wiring 32 as a fifth wiring layer formed on one surface side of the resin base 31. And an adhesive layer 33 as a fourth adhesive layer provided on the other surface side of the resin base 31. The third single-sided substrate 30 </ b> C includes a via 34 as a sixth interlayer conductive layer filled in the via hole 4 penetrating the resin base material 31 together with the adhesive layer 33.

  The first and second double-sided boards 10A and 10B and the intermediate board 20 can be constituted by double-sided CCL, and the first to third single-sided boards 30A to 30C can be constituted by single-sided CCL. The manufacturing method of each of these substrates will be described later. Each resin base material 11, 21, 31 is composed of a resin film of a low dielectric constant material having a thickness of about 25 μm, for example. As the resin film, for example, polyimide, polyolefin, liquid crystal polymer (LCP), or the like can be used.

  The wirings 12 and 32 are made of, for example, a conductive material such as a copper foil patterned on the resin base materials 11 and 31, or a conductive layer obtained by combining this conductive material and a plating material. The first and second electronic components 80 and 90 include active components such as transistors, integrated circuits (ICs), and diodes, and passive components such as resistors, capacitors, relays, and piezoelectric elements.

  The first and second electronic components 80 and 90 shown in FIG. 1 are, for example, WLP (Wafer Level Package) subjected to rewiring. A plurality of rewiring electrodes 81 and 91 formed on pads (not shown) are provided on the electrode forming surfaces 81b and 91b side of the first and second electronic components 80 and 90, respectively. An insulating layer (not shown) is formed around 91.

  The vias 23 and 34 are made of conductive paste filled in the via holes 3 and 4, respectively. The conductive paste contains at least one kind of low electrical resistance metal particles and at least one kind of low melting point metal particles. The conductive paste is made of a paste obtained by mixing a binder component with these metal particles.

  The conductive paste thus configured has, for example, a metal sintered type characteristic in which the curing temperature is about 150 ° C. to 200 ° C. and the melting point after curing is about 260 ° C. or more. For this reason, for example, the contained low melting point metal particles can be melted at 200 ° C. or lower to form an alloy, and in particular, have characteristics that can form an intermetallic compound with copper, silver, or the like. Accordingly, the connection portions between the vias 23 and 34 and the wirings 12 and 32 are alloyed by an intermetallic compound at the time of batch lamination.

  Note that the conductive paste can also be composed of, for example, a nanopaste in which a filler having a nanometer particle size is mixed with the binder component as described above. In addition, the conductive paste can be composed of a paste in which the metal particles are mixed with the binder component as described above.

  In this case, the conductive paste has a characteristic that electrical connection is made when the metal particles come into contact with each other. In addition, as a filling method of the conductive paste into the via holes 3 and 4, for example, a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, and a method using these in combination can be used. As described above, the via 13 is formed by plating applied to the via hole 2 in order to connect the wirings 12 formed on both surfaces of the resin base material 11 to each other.

  As described above, in the component-embedded substrate 1 according to the first embodiment, each substrate has the first single-sided substrate 30A, the first double-sided substrate 10A, and the intermediate substrate 20 from the lower side to the upper side in the stacking direction. Second, the single-sided board 30B, the second double-sided board 10B, and the third single-sided board 30C are arranged in this order. As a result, a component-embedded substrate having a six-layer structure is formed.

  The first single-sided board 30A and the first double-sided board 10A are connected by the adhesive layer 33 of the first single-sided board 30A. The first double-sided board 10 </ b> A and the second single-sided board 30 </ b> B are connected to each other by the adhesive layer 22 of the intermediate board 20. Furthermore, the second double-sided substrate 10B, the second single-sided substrate 30B, and the third single-sided substrate 30C are connected by the adhesive layer 33 of each single-sided substrate 30B, 30C.

  In the first and second single-sided substrates 30A and 30B except for the uppermost third single-sided substrate 30C, a part of the via 34 is connected to the electrodes 81 and 91 of the first and second electronic components 80 and 90, and the wiring 32 is provided. Is arranged so as to be located on the lower side in the stacking direction of the resin base material 31. The adhesive layers 22 and 33 between the respective layers can be made of an organic adhesive material containing a volatile component such as epoxy or acrylic.

  Further, as shown in FIG. 1B, the component-embedded substrate 1 is, for example, based on the arrangement of the first opening 89 and the first electronic component 80 of the first double-sided substrate 10A as a reference. The second opening 99 and the second electronic component 90 are formed so as to be displaced by a predetermined angle in the horizontal direction with respect to the reference.

  That is, in the component-embedded substrate 1 according to the first embodiment, first, as a premise, the component central axes of the first and second electronic components 80 and 90 are P1 and P2, and the first and second openings 89 and 99 are used. When the center axis of the aperture is S1, S2, all these center axes overlap in the stacking direction.

  The first and second openings 89 and 99 are formed such that the inner peripheral surfaces 89a and 99a thereof do not form the same plane along the stacking direction and do not overlap in the stacking direction. The first and second electronic components 80 and 90 have the same outer peripheral surfaces 80a and 90a in the first and second openings 89 and 99 configured as described above, along the stacking direction. Are not formed and do not overlap in the stacking direction.

  Specifically, the second opening 99 is formed in a state where it is rotated by a predetermined angle within a plane orthogonal to the opening center axis S1 of the first opening 89. Further, the second electronic component 90 is accommodated in the second opening 99 while being rotated by a predetermined angle in the same manner as the second opening 99 in a plane orthogonal to the component central axis P1 of the first electronic component 80. ing.

  In the component built-in substrate 1 according to the first embodiment configured as described above, the first gap 89 s between the outer peripheral outer surface 80 a of the first electronic component 80 and the inner peripheral surface 89 a of the first opening 89. And the second gap 99s between the outer peripheral surface 90a of the second electronic component 90 and the inner peripheral surface 99a of the second opening 99 substantially overlaps in the stacking direction except for a part when viewed from above. The entire substrate is formed so that it does not become a state.

  For this reason, the total volume of the overlapping portions of the gaps 89s and 99s formed in the different layers in the stacking direction is compared with the case where the openings of the different layers and the electronic components are provided at substantially the same position in the stacking direction. The first and second electronic components 80 and 90 can be reduced around the first and second electronic parts except for a part.

  That is, in the present invention, depending on the positional relationship between the gaps 89s and 99s in the stacking direction, the adhesive layers 22 and 33 that flow into the gaps 89s and 99s and flow into the gaps 89c during press cure are formed. Attention is paid to the fact that the flow amount of the material can change around the first and second electronic components 80 and 90.

  The flow amount is suppressed as much as possible except for a part, that is, by reducing the total volume of the portions of the gaps 89s and 99s that overlap in the stacking direction over almost the entire circumference of the first and second electronic components 80 and 90. The coplanarity of the same surface shape as that of the component-embedded substrate in which the electronic component is embedded in only a single layer is ensured.

  Specifically, as shown in FIGS. 1A and 2, at the time of batch stacking, for example, with a predetermined pressing force F1 indicated by a white arrow in the drawing from the lower side to the upper side in the stacking direction, From the upper side of the direction to the lower side, thermocompression bonding is performed with a predetermined pressing force F2 indicated by a white arrow in the figure. For example, it is assumed that the pressing force F1 is slightly weaker than the pressing force F2.

When thermocompression bonding is performed under such conditions, as shown in FIG. 2, in the portion where the total volume of the portions of the gaps 89s and 99s overlapping in the stacking direction becomes the largest, the gap 89s indicated by the arrow f _large 1 in the drawing The flow amount f _large 1 of the adhesive layer 33 of the first single-sided substrate 30A flowing into the first flow rate and the flow amount f _large 2 of the adhesive layer 33 of the third single-sided substrate 30C flowing into the gap 99s indicated by the arrow f _large 2 in the figure are: It becomes the largest around the first and second electronic components 80 and 90.

That is, the adhesive layer 33 of the first single-sided board 30A flows into the fluidized amount _{f large} 1 in the gap 89s, a resin substrate 31 of the first single-sided board 30A locations overlapping the stacking direction gap 89s along with this laminated It dents deeply in a convex shape toward the upper side of the direction. The adhesive layer 33 of the third single-sided board 30C flows into the fluidized amount _{f large} 2 in the gap 99s, a resin substrate 31 of the third single-sided board 30C locations overlapping the stacking direction gap 99s along with this laminated It dents deeper than the resin base material 31 of the first single-sided substrate 30A in a convex shape toward the lower side of the direction.

  Since the pressing force F1 is slightly weaker than the pressing force F2 as described above, the resin base material 31 of the second single-sided substrate 30B that overlaps the gap 99s in the stacking direction and the portion that overlaps the gap 89s in the stacking direction. The resin base material 21 of the intermediate substrate 20 is slightly deformed in a convex shape toward the lower side in the stacking direction.

On the other hand, as shown in FIG. 1 (a), the gap 89s indicated by the arrow f _small 1 in the figure is a portion where the total volume of the portions of the gaps 89s and 99s overlapping in the stacking direction is smaller than that shown in FIG. a flow amount _{f small} 1 adhesive layer 33 of the first single-sided board 30A which flows into the inside, the flow amount _{f small} 2 of the adhesive layer 33 of the third single-sided board 30C flow into the gap 99s shown by arrow _{f small} 2 is It becomes smaller than the flow amount f _large 1, f _large 2.

That is, the adhesive layer 33 of the first single-sided substrate 30A flows into the gap 89s with a flow rate f _small 1 and the resin base material 31 of the first single-sided board 30A at the location overlapping with the gap 89s in the stacking direction is laminated. Slightly concave in a convex shape toward the upper side of the direction. Further, the adhesive layer 33 of the third single-sided substrate 30C flows into the gap 99s with a flow amount f _small 2 and accordingly, the resin base material 31 of the third single-sided board 30C at the location overlapping the gap 99s in the laminating direction is laminated. It is recessed slightly more than the resin base material 31 of the first single-sided substrate 30A in a convex shape toward the lower side in the direction.

  The resin base material 31 of the second single-sided substrate 30B that overlaps the gap 99s in the stacking direction and the resin base material 21 of the intermediate substrate 20 that overlaps the gap 89s and the stacking direction have a slight pressing force F1 as described above. Therefore, it is slightly deformed in a convex shape toward the lower side in the stacking direction.

The dent of the resin base 31 of the first single-sided board 30A and the dent of the resin base 31 of the third single-sided board 30C can be factors that affect the coplanarity of the surface shape. In the component-embedded substrate 1 of the first embodiment, there are some portions where the maximum flow amount f _large 1, f _large 2 is around the first and second electronic components 80 and 90, and the flow amount f Most of the locations are _small 1, f _small 2 and locations where the amount of flow is slightly different from the flow amounts f _small 1, f _small 2.

In addition, when thermocompression bonding is performed with the pressing forces F1 and F2 in the same manner as described above, the flow amount of the adhesive layer to the gap between the opening of the component-embedded substrate in which the electronic component is embedded only in the single layer and the electronic component _Is the smallest flow amount f _vsmall 1 + f _vsmall 2, the flow amount f _small 1 + f _small 2 is slightly higher than this.

  Therefore, the deformation due to the depression of the surface shape on the surface layer side in the gaps 89 s and 99 s around the first and second electronic components 80 and 90 embedded in different layers, and the component-embedded substrate in which the electronic components are embedded only in a single layer Since the levels can be made substantially equal, it is possible to improve the coplanarity of the multilayered component-embedded substrate.

  In addition, since the manufacturing process and batch lamination process of each substrate can be realized by the same process as the conventional component built-in substrate, the component built-in substrate 1 according to the first embodiment simplifies the manufacturing process. In addition, the overall thickness can be reduced and the coplanarity of the surface shape can be improved. If the coplanarity of the surface shape can be improved, it is possible to suppress the occurrence of mounting defects when components are mounted on the surface of the component-embedded substrate 1, so that surface mounting defects can be prevented.

  Next, a manufacturing method of the component built-in substrate 1 according to the first embodiment will be described. In the following description including the drawings from FIG. 3 onward, the same reference numerals are assigned to the same components as those described above, and therefore, redundant description is omitted below.

  3, 4, 5, and 6 are flowcharts showing manufacturing steps of the component built-in substrate 1. FIGS. 7, 8, 9, 10, and 11 are cross-sectional views showing the component-embedded substrate 1 for each manufacturing process. First, the manufacturing process of the first single-sided substrate 30A will be described with reference to FIGS. It should be noted that the flowchart of FIG.

  First, as shown in FIG. 3, the wiring 32 is formed on a single-sided CCL (single-sided copper-clad laminate) (step S100). In this step S100, for example, a single-sided CCL in which a conductor layer made of a solid copper foil or the like is formed on one surface of the resin base 31 is prepared. Then, an etching resist is formed on the one-sided CCL conductor by, for example, photolithography, and then etching is performed to form a wiring 32 as shown in FIG. 7A.

  The wiring 32 may be formed by, for example, a semi-additive method. For forming the wiring 32 by the semi-additive method, for example, a conductive thin film is formed on the resin base material 31 by vapor deposition or sputtering, and then a plating resist is formed by photolithography or the like. Thereafter, electrolytic plating is performed, and after removing the plating resist, the conductive thin film previously formed by etching is removed.

  The single-sided CCL that can be used in step S100 includes a structure in which a resin base material 31 having a thickness of about 25 μm is bonded to a conductor layer made of a copper foil having a thickness of about 12 μm, for example. As this single-sided CCL, what was produced by apply | coating a polyimide varnish to copper foil and hardening the varnish by the well-known casting method, for example can be used.

  In addition, as single-sided CCL, a seed layer is formed on a polyimide film by sputtering and copper is grown by plating to form a conductor layer, or rolled or electrolytic copper foil and polyimide film are bonded together with an adhesive. The created one can also be used. In addition, the material of the resin base material 31 is not limited to a polyimide, As mentioned above, plastics, such as a liquid crystal polymer, can also be used. Further, an etchant mainly composed of ferric chloride or cupric chloride can be used for the etching.

  Next, an adhesive is affixed to form the adhesive layer 33 (step S102). In this step S102, for example, an adhesive is attached to the other surface of the resin base 31 opposite to the wiring 32 side by lamination or the like. Examples of the adhesive that can be attached in step S102 include an epoxy thermosetting film having a thickness of about 25 μm. Then, when pasting, for example, using a vacuum laminator, the adhesive is bonded to the resin substrate 31 by performing a heat press at a pressure of 0.3 MPa at a temperature at which the adhesive is not cured in an atmosphere under reduced pressure. Is mentioned.

  The adhesive that can be used for the adhesive layer 33 and the adhesive layer 22 of the intermediate substrate is not limited to the epoxy thermosetting resin, but is a heat represented by an acrylic adhesive or thermoplastic polyimide. Plastic adhesives can also be used. Further, the adhesive is not limited to a film shape, and an adhesive applied with a varnish-like resin can also be used.

  After forming the adhesive layer 33, the via hole 4 is formed (step S104). In this step S104, a laser beam is irradiated to a predetermined location using a UV-YAG laser device from the adhesive layer 33 side toward the wiring 32, for example. Thereby, as shown in FIG.7 (b), the via hole 4 which penetrates the contact bonding layer 33 and the resin base material 31 is formed in a predetermined location. The via hole 4 may be subjected to, for example, a plasma desmear process after the formation.

In addition, the via hole 4 can be formed by a carbon dioxide laser (CO ₂ laser), an excimer laser, or the like, drilling, chemical etching, or the like. The desmear treatment can be performed with a mixed gas of CF ₄ and O ₂ (tetrafluoromethane + oxygen), but other inert gases such as Ar (argon) can also be used. Further, the desmear process may be a wet desmear process using a chemical solution instead of a so-called dry process.

  After the via hole 4 is formed, the conductive paste is filled to form the via 34 as shown in FIG. 7C (step S106). In step S106, the via hole 4 is filled with the conductive paste as described above, for example, by screen printing. Through the steps so far, it is possible to manufacture a plurality of single-sided substrates having wirings, vias, and adhesive layers.

  Finally, the first electronic component is mounted (step S108). In this step S108, for example, the rewiring electrode 81 of the first electronic component 80 manufactured separately in a known semiconductor manufacturing process is placed in a predetermined via 34 of the single-sided substrate as shown in FIG. Align using the component mounting machine. Then, by heating at a temperature lower than the curing temperature of the adhesive of the adhesive layer 33 and the conductive paste of the via 34, the first electronic component 80 is temporarily bonded and mounted as shown by the arrows in FIG. To do.

  In this way, the first single-sided substrate 30A is manufactured. The second single-sided substrate 30B can also be manufactured by the same process as described above. However, in the component-embedded substrate 1 of the first embodiment, the first electronic component 80 and the second electronic component 90 have the component central axes P1 and P2 stacked in the stacking direction. It is built in a state of rotating with respect to the first electronic component 80 in a plane orthogonal to the central axis P2.

  For this reason, in the alignment and temporary bonding using the electronic component mounting machine described above, in the manufacturing process of the first single-sided board 30A and the second single-sided board 30B, the first double-sided board 10A and the second double-sided board described later. According to the formation mode of the first opening 89 and the second opening 99 of the substrate 10B, the arrangement mode of the electronic components 80 and 90 by the alignment and temporary fixing is different. It should be noted that such positioning, temporary bonding, or opening formation can be easily performed by automation in different production lines or a manufacturing robot that assembles parts that have undergone these automations. There is no problem.

  Further, the third single-sided substrate 30C can be manufactured in the same manner as described above. That is, the wiring 32 is formed on one surface side of the resin substrate 31 as shown in FIG. 8A, and the adhesive layer 33 is formed on the other surface side of the resin substrate 31 as shown in FIG. Form. Then, as shown in FIG. 8C, a via hole 4 is formed at a predetermined location, and as shown in FIG. 8D, a conductive paste is filled in the via hole 4 to form a via 34. Thereby, the third single-sided substrate 30C is manufactured. Thus, the 1st-3rd single-sided board | substrates 30A-30C are manufactured and prepared.

  Next, the manufacturing process of the first double-sided substrate 10A will be described with reference to FIGS. Note that the flowchart of FIG. 4 is also referred to as appropriate even if not particularly specified.

  First, as shown in FIG. 4, a double-sided CCL (double-sided copper-clad laminate) in which a conductor layer is formed on both sides of a resin substrate 11 is prepared (step S200), and a via hole is formed at a predetermined location by a laser as described above. 2 is formed (step S202), and for example, a plasma desmear process is performed. Then, panel plating is performed on the entire surface of the resin base material 11 (step S204), a plating layer is formed on the conductor layer and in the via hole 2, and a prototype of the wiring 12 and the via 13 is formed.

  Next, as shown in FIG. 9A, the wiring 12, the via 13, and the like are pattern-formed (step S206). In this step S206, for example, etching is performed on both surfaces of the resin base material 11 to perform pattern formation. Finally, as shown in FIG. 9B, the first opening 89 is formed (step S208).

  In this step S208, for example, the resin base material 11 corresponding to the portion where the first electronic component 80 is accommodated and the portion serving as the gap 89s is irradiated with laser light using the UV-YAG laser device as described above. To form a first opening 89 having a predetermined opening size. In this way, the first double-sided substrate 10A is manufactured. The second double-sided substrate 10B can also be manufactured by the same process as described above.

  However, as shown in FIG. 1B, in the component-embedded substrate 1 of the first embodiment, the first opening 89 and the second opening 99 overlap the opening center axes S1 and S2 in the stacking direction. Also, for example, the second opening 99 is formed in a state of being rotationally moved with respect to the first opening 89 in a plane orthogonal to the opening center axis S2.

  For this reason, in the formation of the opening using the laser device described above, the formation of the openings 89 and 99 is different in the manufacturing process of the first double-sided substrate 10A and the second double-sided substrate 10B. In this way, the first and second double-sided substrates 10A and 10B in which the first and second openings 89 and 99 are formed are manufactured and prepared.

  Next, the manufacturing process of the intermediate substrate 20 will be described with reference to FIGS. It should be noted that the flowchart of FIG.

  First, as shown in FIG. 5, the adhesive layer 22 is formed (step S300). In this step S300, for example, an adhesive layer 22 as shown in FIG. 10A is formed by sticking an adhesive material on both sides of the resin base material 21 made of a polyimide film by lamination or the like. Next, as shown in FIG. 10B, a via hole 3 is formed (step S302).

  In this step S302, the via hole 3 is formed by penetrating the adhesive layer 22 and the resin base material 21 at a predetermined location by the laser as described above, and for example, a plasma desmear process is performed. Finally, as shown in FIG. 10C, the via 23 is formed (step S304). In step S304, the conductive paste is filled into the formed via hole 2 by the above-described screen printing or the like. Thereby, the intermediate substrate 20 is manufactured.

  Next, a manufacturing process for batch stacking of the component-embedded substrate 1 will be described with reference to FIGS. Note that the flowchart of FIG. 6 is also referred to as appropriate even if not particularly specified.

  As described above, when the first and second single-sided boards 30A and 30B on which the first and second double-sided boards 10A and 10B, the intermediate board 20, and the first and second electronic components 80 and 90 are temporarily mounted are manufactured. 11, the first single-sided board 30A, the first double-sided board 10A, the intermediate board 20, the second single-sided board 30B, the second double-sided board 10B, and the third one from the lower side to the upper side in the stacking direction. Each substrate is positioned and stacked in the order of the single-sided substrate 30C (step S400).

  In this step S400, only the positioning at the time of stacking each substrate is performed. As described above, the formation and accommodation positional relationship of the first opening 89 and the first electronic component 80 and the second opening and second electronic component 90 are in advance relative to the first opening 89 and the first electronic component 80. Since the second opening 99 and the second electronic component 90 are formed and temporarily mounted so as to rotate and move in a plane perpendicular to the central axes P2 and S2, in this step S400, the complicated positioning is performed. There is no need to do.

  Finally, each laminated substrate is put into a reduced-pressure atmosphere of 1 kPa or less, and for example, using a vacuum press machine, as shown by predetermined pressing forces F1 and F2 indicated by white arrows in the drawing, It heats, pressing from the upper side toward each other. As a result, thermocompression bonding (step S402) is performed and the layers are stacked together. In this way, the component-embedded substrate 1 having a six-layer structure as shown in FIGS. 1 and 2 is manufactured.

  At the time of collective lamination, the flow of the adhesive layers 22 and 33 into the respective layers and the first and second gaps 89s and 99s and the entire curing including the resin base materials 11, 21, and 31 are simultaneously performed in the via holes 3 and 4. The vias 23 and 34 are hardened and alloyed. And, by the alloy layer of the intermetallic compound, the mechanical strength of the connection portions of the wirings 12, 31 and the vias 23, 34 can be increased, and the connection reliability can be increased.

  Further, the flow of the adhesive layers 22 and 33 into the gaps 89 s and 99 s is the total volume of the portions of the gaps 89 s and 99 s that overlap each other in the stacking direction around the first and second electronic components 80 and 90. Is substantially the same as the volume of the gap in the same portion when the electronic component is built in only a single layer, so that the flow amount can be made almost unchanged.

  For this reason, the deformation of the surface shape of the substrate can be made substantially equivalent to that of the component-embedded substrate in which the electronic component is embedded only in a single layer, and the desired coplanarity can be ensured. Accordingly, it is possible to suppress the occurrence of mounting defects in surface mounting and prevent surface mounting defects.

[Modification of First Embodiment]
FIG. 12 is a cross-sectional view showing a first modification of the component built-in substrate 1, and FIG. 13 is a cross-sectional view showing a second modification of the component built-in substrate 1. These FIG.12 and FIG.13 has shown the cross-sectional location similar to the cross-sectional location shown to Fig.1 (a). 2 is different from the cross section shown in FIG. 2, in FIG. 12 and FIG. 13, the electrode 91 of the second electronic component 90 and a part of the via 34 of the second single-sided board 30 </ b> B are formed and arranged. Is shown by a simplified virtual line.

  As shown in FIG. 12, in the component built-in substrate 1 of the first modification, the pressing force at the time of thermocompression bonding by batch lamination is, for example, a predetermined arrow indicated by an outlined arrow from the upper side to the lower side in the lamination direction. Only the pressing force F2, and the first single-sided substrate 30A side is flattened. Further, as shown in FIG. 13, the component-embedded substrate 1 of the second modified example has a pressing force at the time of thermocompression bonding by batch stacking, for example, indicated by a white arrow in the drawing from the lower side to the upper side in the stacking direction. Only the predetermined pressing force F1 is used, and the third single-sided substrate 30C side is flattened.

In the case shown in FIG. 12, the adhesive layer 33 of the third single-sided substrate 30C flows into the gap 99s with a flow amount f _medium 2 while the surface side of the first single-sided substrate 30A is pressed flat by a jig or the like. Along with this, the resin base 31 of the third single-sided board 30 </ b> C that overlaps the gap 99 s in the stacking direction is slightly recessed in a convex shape toward the lower side in the stacking direction. In addition, the resin base 31 of the second single-sided substrate 30B that overlaps the gap 99s in the stacking direction is slightly recessed in a convex shape toward the lower side in the stacking direction.

  Furthermore, the resin base material 21 of the intermediate substrate 20 at a location overlapping the gap 89s in the stacking direction is slightly recessed in a convex shape toward the lower side in the stacking direction. At this time, since the adhesive layer 22 of the intermediate substrate 20 does not flow so much into the gap 89s, the resin base material 31 of the first single-sided board 30A at a location overlapping the gap 89s in the stacking direction is directed downward in the stacking direction. Flatness is ensured with almost no convex deformation.

Conversely, in the case shown in FIG. 13, in a state where the flat pressing surface layer side of the third single-sided board 30C by a jig or the like, the adhesive layer 33 of the first single-sided board 30A is flow quantity _{f medium} 1 into the gap 89s It flows in. Along with this, the resin base material 31 of the first single-sided substrate 30A at a location overlapping the gap 89s in the stacking direction is slightly recessed in a convex shape toward the upper side in the stacking direction. Further, the resin base material 21 of the intermediate substrate 20 at a location overlapping with the gap 99s in the stacking direction is slightly recessed in a convex shape toward the upper side in the stacking direction.

  Further, the resin base material 21 of the second single-sided substrate 30B that overlaps the gap 99s in the stacking direction is slightly recessed in a convex shape toward the upper side in the stacking direction. At this time, the adhesive layer 33 of the second single-sided substrate 30B does not flow so much into the gap 99s, so the resin base 31 of the third single-sided substrate 30C that overlaps the gap 99s in the laminating direction is on the upper side in the laminating direction. The flatness is ensured in the same manner as described above.

The flow amounts f _medium 1 and f _medium 2 are slightly larger than the flow amounts f _small 1 and f _small 2 and smaller than the flow amounts f _large 1 and f _large 2, respectively. In the following _description , the flow amount f _small 1 and f _medium 1 are collectively referred to as the flow amount f 1, and the flow amount f _small 2 and f _medium 2 are collectively referred to as the flow amount f 2.

  According to the first and second modified examples, the component-embedded substrate in which the electronic component is embedded only in a single layer while the surface shape of one of the substrates is kept almost flat. Can be almost equivalent. As a result, desired coplanarity can be ensured, occurrence of mounting defects in surface mounting can be suppressed, and surface mounting defects can be prevented.

[Other Modifications of First Embodiment]
FIG. 14 is a plan view showing another modification of the component built-in substrate 1.
In the first embodiment described above, the component center axes P1, P2 of the first and second electronic components 80, 90 and the opening center axes S1, S2 of the first and second openings 89, 99 are all in the stacking direction. It is assumed that the second electronic component 90 and the second opening 99 are rotated and moved in a plane perpendicular to the central axes P1 and S1 with respect to the first electronic component 80 and the first opening 89.

  It is desirable that this rotational movement R as indicated by an arrow R in FIG. 14 is performed within a predetermined angle θ with respect to the other. Specifically, the opening inner peripheral surfaces 89a and 99a (or the outer peripheral outer surfaces 80a and 90a) that form the same plane along the stacking direction when the gaps 89s and 99s are all overlapped in the stacking direction are viewed from above. For example, the angle θ is preferably within a range of about 5 ° to about 90 °.

  The rotational movement R is more preferably performed within a range of about 45 ° to about 90 ° including rotation where the angle θ is about 45 ° as shown. Even in this case, the same effect as the above-described effect, that is, the desired coplanarity can be ensured, the occurrence of the mounting failure in the surface mounting can be suppressed, and the surface mounting failure can be prevented.

[Second Embodiment]
FIG. 15 is a cross-sectional view and a plan view showing a component-embedded substrate 1A according to the second embodiment of the present invention, and FIG. 15 (a) shows a cross-section along the line CC ′ in the plan view of FIG. 15 (b). ing.
As illustrated in FIG. 15B, the component-embedded substrate 1 </ b> A according to the second embodiment includes, for example, a formation mode of the second opening 99 with respect to the first opening 89 and the second electronic component 90 with respect to the first electronic component 80. Is different from the first embodiment in the following points.

  That is, in the component-embedded substrate 1A of the second embodiment, the opening center axis S1 of the first opening 89 and the component center axis P1 of the first electronic component 80 overlap in the stacking direction, and the second opening 99 opening center axis | shafts S2 and the component center axis | shaft P2 of the 2nd electronic component 90 have overlapped in the lamination direction.

  However, for example, the second electronic component 90 and the second opening 99 are translated with respect to the first electronic component 80 and the first opening 89 in a plane orthogonal to the central axes P1 and S1, in other words, the center. The entire substrate is formed so that the axes P1 and S1 and the central axes P2 and S2 are translated so as not to overlap in the stacking direction.

  As shown in FIG. 15A, the component-embedded substrate 1A is similar to the component-embedded substrate 1 of the first embodiment in that the first to third single-sided substrates 30A to 30C, the first and second double-sided substrates 10A, 10B, the intermediate substrate 20, and the first and second electronic components 80 and 90, and the stacking order thereof is similarly configured. Moreover, although the thing of illustration shows what applied pressure with the predetermined pressing force from the up-and-down side of the lamination direction, and thermocompression-bonded, what can apply pressure from any one side can also be comprised.

  In the component-embedded substrate 1A configured in this way, as in the first embodiment, most of the gaps 89s and 99s do not overlap in the stacking direction. For this reason, the flow rate f1, f2 of the adhesive layer 33 flowing into the gaps 89s, 99s over almost the entire circumference of the first and second electronic components 80, 90 is the component-embedded substrate in which the electronic components are embedded only in a single layer. Can be almost equivalent. Therefore, the same operational effects as those of the first embodiment can be obtained.

  According to the experiment by the present applicant, in the component-embedded substrate 1A, when the flow distances of the flow amounts f1 and f2 of the first and second electronic components 80 and 90, for example, the adhesive layer 33 are about 100 μm, respectively. When the gaps 89s and 99s all overlap in the stacking direction, they are translated so that the distance d between the pair of outer peripheral surfaces 80a and 90a forming the same plane along the stacking direction is, for example, 100 μm or more. It has been found that it is preferable to arrange in the state. This arrangement is because a coplanarity closer to a component-embedded substrate in which electronic components are embedded in only a single layer can be obtained.

[Third Embodiment]
16A and 16B are a cross-sectional view and a plan view showing a component-embedded substrate according to the third embodiment of the present invention, and FIG. 16A shows a cross-section along the line DD 'in the plan view of FIG. Yes.
As illustrated in FIG. 16A, the component-embedded substrate 1 </ b> B according to the third embodiment includes, for example, a formation mode of the second opening 99 with respect to the first opening 89 and the second electronic component 90 with respect to the first electronic component 80. Is different from the first embodiment in the following points.

  That is, in the component-embedded substrate 1B of the third embodiment, the opening center axis S1 of the first opening 89 and the component center axis P1 of the first electronic component 80 overlap in the stacking direction, and the second opening 99 opening center axis | shafts S2 and the component center axis | shaft P2 of the 2nd electronic component 90 have overlapped in the lamination direction.

  However, for example, the second electronic component 90 and the second opening 99 are rotated and translated in a plane perpendicular to the central axes P1 and S1 with respect to the first electronic component 80 and the first opening 89, in other words, For example, the entire substrate is formed such that the central axes P1 and S1 and the central axes P2 and S2 are rotated and translated so that they do not overlap in the stacking direction. As shown in FIG. 16A, the component built-in substrate 1B has the same substrate configuration as the first and second component built-in substrates 1 and 1A, and the stacking order thereof is also configured similarly. .

  In the component-embedded substrate 1B configured as described above, the first and second electronic components 80 and 90 are the same as in the first and second embodiments because most of the gaps 89s and 99s do not overlap in the stacking direction. The flow amounts f1 and f2 of the adhesive layer 33 flowing into the gaps 89s and 99s over almost the entire circumference can be made substantially equal to those of the component-embedded substrate in which the electronic component is built in only a single layer. Therefore, the same effects as those of the first and second embodiments can be achieved.

[Modification of Third Embodiment]
FIG. 17 is a plan view showing a modification of the component built-in substrate 1B.
In the above-described third embodiment, the component center axis P1 of the first electronic component 80 and the opening center axis S1 of the first opening 89, and the component center axis P2 of the second electronic component 90 and the second opening are included. 99, the opening center axis S2 overlaps with each other in the stacking direction, and the second electronic component 90 and the second opening 99 are orthogonal to the center axes P1 and S1 with respect to the first electronic component 80 and the first opening 89. It was assumed that it was rotated and translated in a plane.

  This parallel movement X, in a two-dimensional direction in a plane orthogonal to the central axes P1, P2, S1, S2, as indicated by an arrow X in FIG. 17 (a) or as indicated by an arrow Y in FIG. Y is preferably performed while maintaining the angle θ within a predetermined range with respect to the other. Even if it does in this way, there can exist an effect similar to the effect mentioned above, a coplanarity can be ensured, and surface mounting failure can be prevented.

[Fourth Embodiment]
18A and 18B are a cross-sectional view and a plan view showing a component-embedded substrate 1C according to the fourth embodiment of the present invention, and FIG. 18A shows a cross-section along the line EE ′ in the plan view of FIG. ing.
As shown in FIG. 18B, the component-embedded substrate 1C according to the fourth embodiment includes component center axes P1, P2 of the first and second electronic components 80, 90, and the first and second openings 89. , 99 are the same as in the first embodiment in that the opening center axes S1 and S2 all overlap in the stacking direction. However, for example, the formation mode of the second opening 99 with respect to the first opening 89 and the arrangement mode of the second electronic component 90 with respect to the first electronic component 80 are different in the following points.

  That is, in the component-embedded substrate 1C of the fourth embodiment, there is no rotational movement or parallel movement as described above, but the first and second openings 89 and 99 have the opening inner peripheral surfaces 89a and 99a. The first and second electronic components 80 and 90 are formed in a state in which they do not form the same plane along the stacking direction and do not overlap in the stacking direction. The outer peripheral surfaces 80a and 90a do not form the same plane along the stacking direction and are accommodated in a state where they do not overlap in the stacking direction. As shown in FIG. 18A, the component-embedded substrate 1C has the same substrate configuration as the first to third component-embedded substrates 1, 1A, 1B, and the stacking order thereof is also configured in the same manner. ing.

  In the component-embedded substrate 1C configured as described above, unlike the first to third embodiments, all the gaps 89s and 99s do not overlap in the stacking direction. Accordingly, the flow amounts f1 and f2 of the adhesive layer 33 flowing into the gaps 89s and 99s over the entire circumference of the first and second electronic components 80 and 90 are equivalent to those of the component-embedded substrate in which the electronic components are embedded only in a single layer. It can be. Therefore, it is possible to obtain a superior coplanarity than the first to third embodiments.

[Modification of Fourth Embodiment]
FIG. 19 is a plan view showing a modification of the component-embedded substrate 1C.
In the fourth embodiment described above, the component center axes P1 and P2 of the first and second electronic components 80 and 90 and the opening center axes S1 and S2 of the first and second openings 89 and 99 are all. For example, the second electronic component 90 and the second opening 99 do not rotate and translate with respect to the first electronic component 80 and the first opening 89.

  However, for example, the second electronic component 90 and the second opening 99 with respect to the first electronic component 80 and the first opening 89 are indicated by an arrow X in FIG. 19A or an arrow Y in FIG. 19B. The combination of the central axes P1 and S1 and the combination of the central axes P2 and S2 as shown in FIG. 6 may be in a state of being translated X and Y within the orthogonal plane so as not to overlap in the stacking direction.

  Further, as shown in FIG. 19C, for example, in the first electronic component 80 and the first opening 89, the component center axes P1 and P2 and the opening center axes S1 and S2 are kept overlapping in the stacking direction. On the other hand, the second electronic component 90 and the second opening 99 may be rotated and moved R within a range of a predetermined angle θ.

  Further, as indicated by an arrow X in FIG. 19D or an arrow Y in FIG. 19E, for example, the second electronic component 90 and the second opening with respect to the first electronic component 80 and the first opening 89 are provided. While maintaining the rotational movement within a predetermined angle θ of 99, the parallel movements X and Y may be performed so that the combination of the central axes P1 and S1 and the combination of the central axes P2 and S2 do not overlap in the stacking direction. good.

  Then, as indicated by an arrow S in FIG. 19 (f), for example, the second electrons with respect to the first electronic component 80 and the first opening 89 are maintained while maintaining the rotational movement within the range of the predetermined angle θ described above. The component 90 and the second opening 99 may be in a state of being translated S to a position where the translations X and Y are combined. Even if it does in this way, there can exist an effect similar to the effect mentioned above, a coplanarity can be ensured, and surface mounting failure can be prevented.

[Other Embodiments]
FIG. 20 is a plan view showing a component-embedded substrate according to another embodiment of the present invention. The component-embedded substrate according to the present invention may have the following configuration in addition to the above. That is, as shown in FIG. 20A, in the component built-in substrate 1D, the first and second openings 89 and 99 are formed so that the inner peripheral surfaces 89a and 99a form the same plane along the stacking direction. The outer peripheral surfaces 80a and 90a of the first and second electronic components 80 and 90 do not form the same plane along the stacking direction and do not overlap in the stacking direction. And accommodated in the first and second openings 89 and 99. In other words, the first and second openings 89 and 99 are formed in the same manner so as to overlap in the stacking direction, but the arrangement modes of the first and second electronic components 80 and 90 do not overlap in the stacking direction. Is different. The arrangement form of the electronic components 80 and 90 includes the rotational movement, the parallel movement, and the movement combining these as described above.

  On the other hand, as shown in FIG. 20B, in the component-embedded substrate 1E, the first and second electronic components 80 and 90 have the outer peripheral surfaces 80a and 90a that form the same plane along the stacking direction and the stacking direction. The inner peripheral surfaces 89a, 99a of the first and second openings 89, 99 do not form the same plane along the stacking direction and do not overlap in the stacking direction. It is formed with. In other words, the arrangement of the first and second electronic components 80 and 90 is the same so as to overlap in the stacking direction, but the formation of the first and second openings 89 and 99 does not overlap in the stacking direction. Is different. The formation mode of the openings 89 and 99 includes the rotational movement, the parallel movement, and the movement combining these as described above.

  20A and 20B, the volume of the portion of the gaps 89s and 99s overlapping in the stacking direction is slightly larger than that of the above-described embodiment. The operational effects substantially similar to the operational effects described above can be achieved.

  As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above-described embodiment, the second electronic component 90 and the second opening 99 are formed so as to be displaced in a predetermined state with respect to the first electronic component 80 and the first opening 89. It was supposed to be. By reversing these relationships, the first electronic component 80 and the first opening 89 may be arranged and formed with the second electronic component 90 and the second opening 99 as a reference. Further, in the above-described embodiment, each of the component-embedded substrates 1 to 1E having a six-layer structure in which a plurality of electronic components 80 and 90 are incorporated in different layers has been described. In addition, if the number of electronic components incorporated is two or more, it can be changed as appropriate.

DESCRIPTION OF SYMBOLS 1 Component built-in board | substrate 10A 1st double-sided board 10B 2nd double-sided board 11 Resin base material 12 Wiring 13 Via 20 Intermediate board 21 Resin base material 22 Adhesive layer 23 Via 30A 1st single-sided board 30B 2nd single-sided board 30C 3rd single-sided board 31 Resin base material 32 Wiring 33 Adhesive layer 34 Via 80 First electronic component 80a Outer outer peripheral surface 89 First opening 89a Opening inner peripheral surface 89s Gap 90 Second electronic component 90a Outer outer peripheral surface 99 Second opening 99a Opening inner peripheral surface 99s gap

Claims (12)

A component-embedded substrate having a multilayer structure having a plurality of unit substrates stacked and having a plurality of electronic components embedded in the stacking direction,
The plurality of unit substrates are:
A first substrate having a first insulating layer and having a first opening in which a first electronic component is accommodated with a first gap;
A second substrate having a second insulating layer and having a second opening in which a second electronic component is accommodated with a second gap;
An intermediate having a first adhesive layer disposed between the first and second substrates, provided on both sides of the third insulating layer and the third insulating layer, and filled in the first and second gaps. Including a substrate,
In the first and second openings, the inner peripheral surfaces of the respective openings do not form the same plane along the stacking direction over the entire circumference, and either one of the opening central axes is in the other opening. And any one of them is formed in a state of rotating and moving in a plane orthogonal to the other opening center axis,
The first and second gaps are configured such that the total volume of the portion overlapping in the stacking direction in the rotationally moved state is smaller than the total volume of the portion overlapping in the stacking direction in the non-rotated state. A component-embedded substrate characterized by being formed. 2. The component-embedded substrate according to claim 1, wherein each of the first opening and the second opening has an opening center axis overlapping in the stacking direction. 2. The component-embedded substrate according to claim 1, wherein each of the first and second openings has an opening center axis that does not overlap in the stacking direction. The said 1st and 2nd electronic component is accommodated in the state in which each external shape outer peripheral surface does not form the same plane along the said lamination direction. Component built-in board. The said 1st and 2nd electronic component is accommodated in the state in which each external shape outer peripheral surface forms the same plane along the said lamination direction. The one of Claims 1-3 characterized by the above-mentioned. Component built-in board. A component-embedded substrate having a multilayer structure having a plurality of unit substrates stacked and having a plurality of electronic components embedded in the stacking direction,
The plurality of unit substrates are:
A first substrate having a first insulating layer and having a first opening in which a first electronic component is accommodated with a first gap;
A second substrate having a second insulating layer and having a second opening in which a second electronic component is accommodated with a second gap;
An intermediate having a first adhesive layer disposed between the first and second substrates, provided on both sides of the third insulating layer and the third insulating layer, and filled in the first and second gaps. Including a substrate,
The first and second electronic components do not form the same plane along the laminating direction over the entire outer periphery of each of the first and second electronic components, and one of the component central axes passes through the other component. And either one is accommodated in a state where it is rotated and moved in a plane orthogonal to the other component central axis,
The first and second gaps are configured such that the total volume of the portion overlapping in the stacking direction in the rotationally moved state is smaller than the total volume of the portion overlapping in the stacking direction in the non-rotated state. A component-embedded substrate characterized by being formed. The component built-in board according to claim 6, wherein the first and second electronic components have respective component central axes overlapping in the stacking direction. The component built-in board according to claim 6, wherein the first and second electronic components have respective component center axes that do not overlap in the stacking direction. The said 1st and 2nd opening part is formed in the state in which each opening inner peripheral surface forms the same plane along the said lamination direction, The any one of Claims 6-8 characterized by the above-mentioned. Component built-in board. The first substrate includes a first wiring layer formed on both sides of the first insulating layer, and a first interlayer conductive layer connected to the first wiring layer in a state of penetrating the first insulating layer. 1 double-sided board,
The second substrate includes a second wiring layer formed on both sides of the second insulating layer and a second interlayer conductive layer connected to the second wiring layer in a state of passing through the second insulating layer. It consists of two double-sided boards,
The component built-in substrate according to claim 1, wherein the intermediate substrate has a third interlayer conductive layer that penetrates the third insulating layer together with the first adhesive layer. The plurality of unit substrates are:
A third wiring layer formed on one surface side of the fourth insulating layer; and a fourth interlayer conductive layer connected to the third wiring layer in a state of penetrating the fourth insulating layer, the fourth insulating layer Including a first single-sided substrate with a second adhesive layer provided on the other side of the layer;
11. The component-embedded substrate according to claim 10, wherein a part of the fourth interlayer conductive layer is connected to the first electronic component on the second adhesive layer side of the first single-sided substrate. The plurality of unit substrates are:
A fifth wiring layer formed on one surface side of the fifth insulating layer; and a fifth interlayer conductive layer connected to the fourth wiring layer in a state of penetrating the fifth insulating layer; Including a second single-sided substrate with a third adhesive layer provided on the other side of the layer;
The component-embedded substrate according to claim 10 or 11, wherein a part of the fifth interlayer conductive layer is connected to the second electronic component on the second adhesive layer side of the second single-sided substrate. .

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