WO2010090316A1 - Semiconductor package and manufacturing method therefor - Google Patents

Semiconductor package and manufacturing method therefor Download PDF

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Publication number
WO2010090316A1
WO2010090316A1 PCT/JP2010/051803 JP2010051803W WO2010090316A1 WO 2010090316 A1 WO2010090316 A1 WO 2010090316A1 JP 2010051803 W JP2010051803 W JP 2010051803W WO 2010090316 A1 WO2010090316 A1 WO 2010090316A1
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WO
WIPO (PCT)
Prior art keywords
wiring layer
wiring
layer
semiconductor package
semiconductor device
Prior art date
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PCT/JP2010/051803
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French (fr)
Japanese (ja)
Inventor
真司 渡邉
連也 川野
洋一郎 栗田
Original Assignee
日本電気株式会社
Ｎｅｃエレクトロニクス株式会社
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Application filed by 日本電気株式会社, Ｎｅｃエレクトロニクス株式会社 filed Critical 日本電気株式会社
Publication of WO2010090316A1 publication Critical patent/WO2010090316A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application No. 2009-027394 (filed on Feb. 9, 2009), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly to a structure of a semiconductor package having a wiring layer around an electronic device and a method for manufacturing the same by a multi-layer lamination method.
  • the present invention also relates to an electronic device using these semiconductor packages.
  • semiconductor packages are also required to be downsized and thinned.
  • a component-embedded substrate in which an electronic component is included in a wiring substrate is being put into practical use as a semiconductor package particularly suitable for a portable device that is required to be downsized.
  • Japanese Patent No. 3867593 proposes a method for manufacturing a substrate incorporating a passive element such as a chip resistor.
  • This includes a plurality of resin films made of a thermoplastic resin in which a via hole is filled with a connection material and wiring is formed, a resin film having a space portion for incorporating a passive element, and a passive film mounted in the space It has been proposed as a technique that can be realized by simultaneously bonding the layers and connecting vias by heating and pressing the elements.
  • Patent Document 1 discloses a manufacturing method (hereinafter, referred to as “batch multi-layer lamination method” or “batch multi-layer connection method”) in which layers are bonded together by aligning each layer and then applying pressure and heating together. .
  • the disadvantage of this manufacturing method is that the via lands cannot be reduced, and therefore it is difficult to narrow the via pitch or to arrange the wiring between the via lands. There are three main reasons.
  • a via pitch of about 300 ⁇ m is a technical limit as defined by the via land size.
  • Japanese Patent Laid-Open No. 2004-260260 a manufacturing method proposed on the assumption of a passive element having about two terminals as a built-in electronic component is acceptable. It was. However, for devices that have hundreds to thousands of terminals such as active components and are arranged in a two-dimensional manner, it is difficult to form wiring between via lands, from the viewpoint of wiring capacity. , Difficult to apply.
  • At least one layer is provided in the wiring layer close to the semiconductor device while using the coarse pitch connection used in the conventional batch multilayer stacking method for connection to the semiconductor device.
  • a small-diameter via land for connecting a fine via formed by plating and a wiring layer including wiring are configured. Therefore, it has the following characteristics.
  • the semiconductor package according to the present invention includes a portion in which at least one semiconductor device, and at least a first wiring layer and a second wiring layer are stacked in this order.
  • the device electrode of the semiconductor device and the first via land of the first wiring layer are connected via the first via, and the device electrode and the first via are in direct contact.
  • the first wiring layer and the second wiring layer are connected to a second via having a smaller diameter than the first via. Further, the first wiring layer and the second wiring layer are configured to protrude from the base substrate layer on both sides of one base substrate layer.
  • an electronic device includes the semiconductor package described above.
  • the method for manufacturing a semiconductor package according to the present invention includes a step of forming a via opening in a base substrate layer, a step of filling the via opening with plating, and both surfaces of the base substrate layer. Forming a protruding wiring layer; forming an insulating resin layer on the base substrate layer and the wiring layer; forming a via opening in the insulating resin layer; and filling the via opening with a connection material And a step of collectively laminating semiconductor devices on the connecting material by heating and pressing.
  • Wiring layers with small via lands are connected by micro vias and placed close to the semiconductor device, which greatly improves wiring capacity. Even when using the multi-layer stacking method, it has been difficult so far.
  • the present invention can be applied to a semiconductor device having hundreds to thousands of terminals such as active parts and having two-dimensionally arranged terminals.
  • a via diameter of about 15 ⁇ m can be realized by plating vias.
  • the patterning of the wiring can form an etching mask or the like based on the plating via. Accordingly, consideration of the alignment of each layer, which has been required in the conventional batch multilayer stacking method, is no longer necessary in the manufacturing method according to the present invention, and as a result, the via land can be reduced in diameter to about 30 ⁇ m using the batch multilayer stacking method. Is possible.
  • the minimum via pitch can be reduced to about 60 ⁇ m.
  • this fine via pitch layer in the wiring layer close to the semiconductor device, when vias are arranged at a rough pitch, for example, 300 ⁇ m pitch in the same batch multilayer stacking method as in the prior art, via land is 30 ⁇ m and wiring width is 40 ⁇ m. Assuming that the wiring interval is 40 ⁇ m, two wirings can be passed between via lands. Therefore, the wiring capacity is dramatically improved, and wiring of a semiconductor device having hundreds to thousands of terminals such as active parts and having terminals arranged two-dimensionally becomes possible.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the wiring layer which concerns on 1st Example of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 1st Example of this invention. It is a schematic sectional drawing of the semiconductor package which concerns on the 2nd Example of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 2nd Example of this invention. It is a schematic sectional drawing of the semiconductor package which concerns on the 3rd Example of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 3rd Example of this invention. It is a schematic sectional drawing which shows the structural example of the semiconductor package which concerns on this invention. It is a schematic sectional drawing which shows the structural example of the semiconductor package using a prior art.
  • the second via land connected to the second via has a smaller diameter than the first via land.
  • first via land and the second wiring layer are connected by the second via, and the second via is arranged at a pitch narrower than the pitch of the first via. preferable.
  • At least one of the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked.
  • the wiring layer located farthest from the semiconductor device among the other wiring layers is adjacent by a third via having a diameter larger than that of the second via. It is preferable to be connected to the wiring layer.
  • the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked.
  • the second vias are arranged at a pitch narrower than the pitch of the first vias, and are located farthest from the semiconductor device in the other wiring layers
  • the wiring layer is preferably connected to the adjacent wiring layer through third vias arranged at a pitch wider than the pitch of the second via.
  • At least one of the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked. Are connected by the second via, and the third via land of the wiring layer located farthest from the semiconductor device among the other wiring layers has a diameter larger than that of the second via land. Is preferred.
  • the first via is formed of a conductive paste.
  • the second via is preferably formed by plating.
  • the material of the base substrate layer can be polyimide.
  • the step of filling the via openings of the base base material layer with plating, and the step of forming wiring layers protruding on both surfaces of the base base material layer include plating and It can carry out collectively by a plating removal process.
  • a plurality of the insulating resin layers on which wiring patterns are formed and the semiconductor devices can be collectively laminated by heating and pressing.
  • a spacer can be arranged around the semiconductor devices, and batch stacking can be performed by heating and pressing.
  • an insulating resin is disposed on the electronic device, and the semiconductor devices can be stacked by heating and pressurizing.
  • FIG. 9 is an example of a semiconductor package using the collective multilayer stacking method according to the prior art.
  • the device electrode 120 of the semiconductor device 100 is connected to the via land 140 via the via 130 in two stages (layers).
  • the diameter of the via 130 is preferably ⁇ 80 to ⁇ 100 ⁇ m from the viewpoint of the filling property of the connection material.
  • the diameter of the via land 140 is about ⁇ 200 to ⁇ 250 ⁇ m, and the via land 140 has a minimum pitch of about 300 ⁇ m.
  • a rule with a wiring width of 40 ⁇ m and a wiring interval of 40 ⁇ m that can be formed by a general subtractive method is used between the via lands 140 arranged in the layer, there is no difference between the via lands 140.
  • the wiring of a book cannot be passed.
  • the pitch is the same as that of each layer via 130 through which wiring does not pass. They can only be connected, and it is completely impossible to change the via pitch or connect the terminals by wiring. For this reason, until now, the pitch of the semiconductor device 100 has to be increased to a pitch that enables wiring formation, and the device size has been increased.
  • FIG. 8 An example of a cross-sectional structure of a semiconductor package according to the present invention is shown in FIG.
  • two (wiring) layers are provided on the upper and lower surfaces of the base substrate layer 8, and the first via land 4 and the second via land 6 are provided on each (wiring) layer.
  • the first via land 4 and the second via land 6 are connected by the second via 7 formed by plating provided on the base substrate layer 8.
  • the second via 7 can be formed with a diameter of about 15 ⁇ m.
  • an etching mask or the like can be formed with reference to the second via 7 which is a plating via. Therefore, it is not necessary to consider the alignment of each layer necessary for the collective multi-layer connection in the prior art.
  • the diameter can be reduced to about ⁇ 30 ⁇ m.
  • the pitch of the first vias 3 is set to 300 ⁇ m, it is restricted by the size of the first via land 4, so that it is difficult to form a wiring layer on this surface.
  • the second via land 6 can be applied to the lower surface layer of the base substrate layer 8 by connecting via the second via 7.
  • the second via land 6 has a diameter of about 30 ⁇ m, if the second via land 6 is arranged at the same 300 ⁇ m as the pitch of the first via land 4, the interval between the second via lands 6 can be ensured to 270 ⁇ m. . Therefore, as shown in the lowermost wiring layer in FIG. 8, even when the rule of the wiring width 40 ⁇ m and the wiring interval 40 ⁇ m is used, at least two wirings 5 can be passed between the second via lands 6. It becomes possible. In this way, the wiring capacity is drastically improved, and it becomes possible to apply to a semiconductor device having a multi-pin and two-dimensionally arranged terminal such as an active component.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
  • a first wiring layer A and a second wiring layer B are disposed on the upper surface and the lower surface of the base substrate layer 8, respectively.
  • the first wiring layer A is provided with a wiring 5, a first via land 4, and a second via land 6.
  • the second wiring layer B is provided with a third via land 20 for connecting to the wiring 5, the second via land 6, and a device or the like disposed below the second wiring layer B.
  • the device electrode 2 of the semiconductor device 1 and the first via land 4 of the first wiring layer A are connected by the first via 3.
  • the via lands 4 and 6 of the first wiring layer A are connected to the via lands 6 and 20 of the second wiring layer B by the second vias 7 disposed inside the base substrate layer 8.
  • An insulating resin 9 is filled between the semiconductor device 1 and the base substrate layer 8.
  • FIG. 2 is a cross-sectional view showing a process until the wiring layers (wiring patterns) A and B are formed on the upper and lower surfaces of the base substrate layer 8.
  • thick film copper 12 is formed in advance on one surface (lower surface) of the base substrate layer 8, and the second via 7 of the base substrate layer 8 is formed.
  • Via openings 14 are formed by laser processing.
  • a polyimide base material can be applied to the base base material layer 8.
  • the diameter of the via opening 14 is preferably about ⁇ 15 ⁇ m to ⁇ 20 ⁇ m.
  • a copper plating layer 13 is formed on both surfaces of the base substrate layer 8 by copper plating. At this time, plating filling of the via opening 14 is simultaneously performed. This portion is a portion that becomes the second via 7.
  • the optimum value of the plating thickness varies depending on the degree of requirement for miniaturization of the wiring, but when the wiring width / wiring interval is aimed at about 30 ⁇ m / 30 ⁇ m, it is preferably about 8 ⁇ m to 12 ⁇ m.
  • a photosensitive resist 15 is formed on the plating.
  • the photosensitive resist 15 at the portion where the copper plating is to be etched is removed by exposure and development, and copper etching is performed. Finally, excess resist is removed, and the formation of the wiring layers A and B on both surfaces of the base substrate layer 8 is completed as shown in FIG.
  • a wiring pattern may be formed using a plating resist by a semi-additive method, for example. In this case, the effect of obtaining a finer wiring pattern can be expected.
  • FIG. 3 shows a cross-sectional view of a process of mounting the semiconductor device 1 on the upper surface wiring layer A of the base substrate layer 8 by a batch lamination method.
  • a prepreg 16 (insulating resin) is formed on the wiring layer A of the base substrate layer 8 (shown in FIG. 3A) on which the wiring layers A and B are formed in the step of FIG. 9).
  • the material is not limited to a prepreg as long as it can be bonded, and may be an epoxy adhesive or a photosensitive polyimide that hardens and solidifies, and a film-like material or a liquid material can also be used.
  • the attachment is performed with a vacuum laminator or a vacuum press, and when it is liquid, it is performed with a spin coater or a curtain coater. Further, after curing once, an adhesive layer may be further formed thereon.
  • a via opening 14 is formed, which is generally performed by a laser if it is not a photosensitive material.
  • the aperture is opened by exposure and development.
  • desmear treatment is performed as necessary to remove organic residues on the bottom surface of the via opening 14.
  • connection material 17 (corresponding to the first via 3).
  • connection material 17 an Ag paste material that is thermosetting or sintered is generally used, but a material that is melted and joined, such as Cu paste or solder, can also be suitably used.
  • the semiconductor device 1 is mounted, and the prepreg 16 and the connection material 17 are cured by heating and pressurization, and the assembly is completed as shown in FIG.
  • the connection material 17 is compressed and hardened, so that a highly reliable connection can be obtained.
  • a semiconductor package having a very high wiring capacity can be realized by applying small-diameter plating vias and via lands while using a multilayer multi-layer lamination technique capable of reducing the cost. It is also possible to reduce the number and to realize a lower cost semiconductor package.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor package according to a second embodiment of the present invention. Since the structure below the device electrode 2 of the semiconductor device 1 is the same as that of the first embodiment, the description thereof is omitted.
  • Example 2 describes a case where the semiconductor device 1 is smaller than the base substrate layer 8.
  • a spacer 10 is arranged around the semiconductor device 1 so that the periphery of the semiconductor device 1 can be uniformly pressurized when the collective multilayer stacking method is used.
  • Resin 11 is filled between the upper surface and the spacer 10 and the semiconductor device 1.
  • the periphery of the semiconductor device 1 is also appropriately pressurized, and the resin 11 is arranged to achieve a uniform pressure in the batch stacking process.
  • FIG. 5 shows a cross-sectional view of the process of mounting the semiconductor device 1 on the base substrate layer 8 by the batch lamination method. Since FIG. 5A to FIG. 5D are the same as in the first embodiment (described in FIG. 3), the description thereof is omitted.
  • the semiconductor device 1 After completion of FIG. 5D, the semiconductor device 1 is mounted, and the spacer 10 is mounted around it. Furthermore, after mounting a resin film (resin 11) on them, the prepreg 16, the connecting material 17, and the resin 11 are cured by heating and pressing, and the assembly is completed as shown in FIG. 5 (e). It is desirable to use a resin film that is liquefied by heating, and the space between the semiconductor device 1 and the spacer 10 is filled with a liquefied resin film (resin 11), and the gap is completely filled. This improves the reliability of the semiconductor package. Further, it is desirable that the semiconductor device 1 and the spacer 10 have the same thickness. As the thickness is equal, a uniform load is applied to the prepreg 16 (insulating resin 9), and a highly reliable connection can be obtained. .
  • FIG. 6 is a schematic sectional view of a semiconductor package according to a third embodiment of the present invention.
  • a further wiring layer and an insulating layer are added below the mounting structure (Example 2) shown in FIG. Since the structure in which the wiring layers A and B are formed on the upper and lower surfaces of the base substrate layer 8 is the same as that of the first embodiment, the description thereof is omitted.
  • the spacer 10 is arranged around the semiconductor device 1, and the resin 11 is filled between the upper surface of the spacer 10 and between the spacer 10 and the semiconductor device 1.
  • the substrate 18 is bonded and fixed via an adhesive 19, and a third wiring layer C is formed thereunder.
  • the wiring layer C and the third via land 20 formed in the wiring layer B are electrically and mechanically connected by the third via 30.
  • the diameter of the third via 30 is larger than the diameter of the second via 7.
  • the third (lowermost layer) wiring layer C (via land) has a structure in which solder bumps 21 for connection to the mother board are formed.
  • FIG. 7 shows a cross-sectional view of the process of mounting the semiconductor device 1 from the base substrate layer 8 by the collective lamination method. Since the manufacturing steps from FIG. 7A to FIG. 7D are the same as those in the first embodiment (described in FIG. 3), description thereof will be omitted.
  • the semiconductor device 1, the spacer 10 around the semiconductor device 1, and a resin film (resin 11) are stacked on them.
  • the adhesive 19 is bonded on the base material 18 whose wiring is patterned on one side, and a via opening opened by laser processing is filled with a connection material (corresponding to the third via 30). Then, as shown in FIG. 7E, these are aligned in the horizontal direction. Finally, the prepreg 16, the connecting material 17, the resin 11 and the adhesive 19 are cured by collectively heating and pressing, and the solder bumps 21 are formed on the lowermost wiring layer C to complete the structure shown in FIG. 6. To do. In this way, it goes without saying that any number of wiring layers can be stacked together.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Disclosed is a semiconductor package for which a semiconductor device is mounted by means of a one-time multilayer lamination method, wherein the via lands can be reduced in diameter, the via pitch can be reduced, and wiring can be arranged between the via lands. This semiconductor package (Figure 6) is characterized by including a portion wherein at least one semiconductor device and at least a first wiring layer and a second wiring layer are stacked in this order, and in that the device electrode of the semiconductor device and a first via land of the first wiring layer are connected by means of a first via; the device electrode and the first via are in direct contact; the first wiring layer and the second wiring layer are connected with a second via that is smaller in diameter than the first via; and the first wiring layer and the second wiring layer are constructed on both sides of one base material layer respectively projecting from the base material layer.

Description

半導体パッケージ及びその製造方法Semiconductor package and manufacturing method thereof
　（関連出願についての記載）
　本発明は、日本国特許出願：特願２００９－０２７３９４号（２００９年２月９日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
　本発明は、半導体パッケージ及びその製造方法に関し、特に電子デバイスの周囲に配線層を備えた構造の半導体パッケージの構造、及びその一括多層積層法による製造方法に関する。また、これらの半導体パッケージを用いた電子機器に関する。 (Description of related applications)
The present invention is based on the priority claim of Japanese Patent Application No. 2009-027394 (filed on Feb. 9, 2009), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly to a structure of a semiconductor package having a wiring layer around an electronic device and a method for manufacturing the same by a multi-layer lamination method. The present invention also relates to an electronic device using these semiconductor packages.
　電子機器の高機能化に伴う部品の増加や機器の小型、薄型化の進展に伴い、半導体パッケージにも小型化、薄型化が要求されている。その中で、特に小型化が要求される携帯機器に適した半導体パッケージとして、電子部品を配線基板の中に内包した部品内蔵基板が実用化されつつある。 伴 い With the increase in the number of parts due to higher functionality of electronic devices and the progress of downsizing and thinning of devices, semiconductor packages are also required to be downsized and thinned. Among them, a component-embedded substrate in which an electronic component is included in a wiring substrate is being put into practical use as a semiconductor package particularly suitable for a portable device that is required to be downsized.
　例えば、特許第３８６７５９３号には、チップ抵抗などの受動素子を内蔵した基板の製造方法が提案されている。これは、ビアホールに接続材料が充填され、かつ配線が形成された熱可塑性樹脂からなる複数の樹脂フィルムと、受動素子を内蔵するための空間部を有した樹脂フィルムと、前記空間に搭載した受動素子とを加熱・加圧によって層間の接着とビアの接続を同時に行うことによって実現する手法として提案されたものである。 For example, Japanese Patent No. 3867593 proposes a method for manufacturing a substrate incorporating a passive element such as a chip resistor. This includes a plurality of resin films made of a thermoplastic resin in which a via hole is filled with a connection material and wiring is formed, a resin film having a space portion for incorporating a passive element, and a passive film mounted in the space It has been proposed as a technique that can be realized by simultaneously bonding the layers and connecting vias by heating and pressing the elements.
特許第３８６７５９３号公報Japanese Patent No. 3867593
　なお、上記特許文献の全開示内容はその引用をもって本書に繰込み記載する。
　以下の分析は、本発明者によってなされたものである。
　特許文献１では、各層を位置合わせした後、一括で加圧・加熱することによって層間を貼り合わせる製造方法（以下「一括多層積層法」又は「一括多層接続法」という。）が開示されている。この製造方法での欠点は、ビアランドを小さくすることができず、そのためビアピッチの狭ピッチ化が困難あるいはビアランド間に配線を配置することが困難なことである。その理由としては、大きく３つ挙げられる。 The entire disclosure of the above patent document is incorporated herein by reference.
The following analysis was made by the present inventors.
Patent Document 1 discloses a manufacturing method (hereinafter, referred to as “batch multi-layer lamination method” or “batch multi-layer connection method”) in which layers are bonded together by aligning each layer and then applying pressure and heating together. . The disadvantage of this manufacturing method is that the via lands cannot be reduced, and therefore it is difficult to narrow the via pitch or to arrange the wiring between the via lands. There are three main reasons.
　まず１つは、各層の位置合わせズレが発生するため、位置ズレを許容できるビアランドサイズとする必要があることからビアランドの小径化が困難なことである。二つ目は、ビアの穴径精度、穴位置精度を許容できるビアランドサイズとする必要があり、各層の位置合わせ精度に加えて、これら精度をも許容できるビアランドサイズとする必要があることである。三つ目は、接続材料をビアホール内に充填する際には、充填性の観点から少なくとも絶縁樹脂層の厚さの２倍以上のビアホール径とする必要があり、引いてはビアランド径のサイズアップが必要となることである。 First, since misalignment of each layer occurs, it is necessary to make the via land size that allows the misalignment, and therefore it is difficult to reduce the via land diameter. Secondly, it is necessary to make the via land size that allows the hole diameter accuracy and hole position accuracy of the via, and in addition to the alignment accuracy of each layer, it is necessary to make the via land size also acceptable. It is. Thirdly, when filling the connection material into the via hole, it is necessary to make the via hole diameter at least twice as large as the thickness of the insulating resin layer from the viewpoint of filling properties, and by extension, the via land diameter is increased. Is necessary.
　これら３つの要因から、ビアランドのサイズから規定されるビアピッチとしては３００μｍピッチ程度が技術的な限界であることが一般的に言われている。特許文献１では、内蔵する電子部品として２端子程度の受動素子を想定して提案された製造手法であることから、ビアのピッチは比較的粗くても許容されるため、大きな問題とはならかった。しかし能動部品のような数百～数千端子を有し、かつ２次元的に端子配置されるデバイスに対しては、ビアランド間に配線を形成することが困難であるという配線収容性の面から、適用が困難である。 From these three factors, it is generally said that a via pitch of about 300 μm is a technical limit as defined by the via land size. In Japanese Patent Laid-Open No. 2004-260260, a manufacturing method proposed on the assumption of a passive element having about two terminals as a built-in electronic component is acceptable. It was. However, for devices that have hundreds to thousands of terminals such as active components and are arranged in a two-dimensional manner, it is difficult to form wiring between via lands, from the viewpoint of wiring capacity. , Difficult to apply.
　本発明では、半導体パッケージ及び一括多層積層法によるその製造方法において、上記欠点の改善が課題となる。 In the present invention, in the semiconductor package and the manufacturing method using the collective multilayer stacking method, improvement of the above-mentioned defects is a problem.
　本発明に係る半導体パッケージ及びその製造方法は、半導体デバイスとの接続には、従来の一括多層積層法で用いられる粗いピッチの接続を用いながら、半導体デバイスに近い配線層には、少なくとも１層の、めっきで形成した微細なビアを接続するための小径のビアランドと配線を含む配線層を含んで構成する。そのため、以下のような特徴を有する。 In the semiconductor package and the manufacturing method thereof according to the present invention, at least one layer is provided in the wiring layer close to the semiconductor device while using the coarse pitch connection used in the conventional batch multilayer stacking method for connection to the semiconductor device. A small-diameter via land for connecting a fine via formed by plating and a wiring layer including wiring are configured. Therefore, it has the following characteristics.
　第１の視点において、本発明に係る半導体パッケージは、少なくとも一つの半導体デバイスと、少なくとも第１の配線層及び第２の配線層とが、この順で積層された部分を含む。該半導体デバイスのデバイス電極と該第１の配線層の第１のビアランドとが第１のビアを介して接続され、かつ該デバイス電極と該第１のビアとが直接接している。また該第１の配線層と該第２の配線層とが、該第１のビアよりも小径な第２のビアと接続される。さらに、該第１の配線層と該第２の配線層は、一つのベース基材層の両面に、それぞれ該ベース基材層から突出して構成されている。 In the first aspect, the semiconductor package according to the present invention includes a portion in which at least one semiconductor device, and at least a first wiring layer and a second wiring layer are stacked in this order. The device electrode of the semiconductor device and the first via land of the first wiring layer are connected via the first via, and the device electrode and the first via are in direct contact. The first wiring layer and the second wiring layer are connected to a second via having a smaller diameter than the first via. Further, the first wiring layer and the second wiring layer are configured to protrude from the base substrate layer on both sides of one base substrate layer.
　また第２の視点において、本発明に係る電子機器は、上記の半導体パッケージを含んで構成される。 In a second aspect, an electronic device according to the present invention includes the semiconductor package described above.
　また第３の視点において、本発明に係る半導体パッケージの製造方法は、ベース基材層にビア開口を形成する工程と、該ビア開口をめっきで充填する工程と、該ベース基材層の両面に突出した配線層を形成する工程と、該ベース基材層及び該配線層の上に絶縁樹脂層を形成する工程と、該絶縁樹脂層にビア開口を形成し、該ビア開口に接続材料を充填する工程と、該接続材料の上部に半導体デバイスを加熱・加圧によって一括積層する工程と、を含む。 In a third aspect, the method for manufacturing a semiconductor package according to the present invention includes a step of forming a via opening in a base substrate layer, a step of filling the via opening with plating, and both surfaces of the base substrate layer. Forming a protruding wiring layer; forming an insulating resin layer on the base substrate layer and the wiring layer; forming a via opening in the insulating resin layer; and filling the via opening with a connection material And a step of collectively laminating semiconductor devices on the connecting material by heating and pressing.
　小径のビアランドを形成した配線層を微小ビアで接続し、半導体デバイスの近くに配置したことにより、配線収容性が飛躍的に向上するため、一括多層積層手法によって構成する場合においても、これまで困難であった能動部品のような数百～数千端子を有し、かつ２次元的に端子配置される半導体デバイスへの適用が可能となる。 Wiring layers with small via lands are connected by micro vias and placed close to the semiconductor device, which greatly improves wiring capacity. Even when using the multi-layer stacking method, it has been difficult so far. Thus, the present invention can be applied to a semiconductor device having hundreds to thousands of terminals such as active parts and having two-dimensionally arranged terminals.
　例えば２５μｍ厚のポリイミド基材を用いた場合、めっきによるビアでは１５μｍ程度のビア径が実現できる。また、配線のパターニングは、めっきビアを基準にエッチングマスク等を形成できる。従って、従来一括多層積層法において必要とされていた、各層の位置合わせの考慮が本発明に係る製造方法では不要となり、その結果、一括多層積層法を用いながらビアランドを３０μｍ程度まで小径化することが可能である。 For example, when a polyimide substrate having a thickness of 25 μm is used, a via diameter of about 15 μm can be realized by plating vias. Further, the patterning of the wiring can form an etching mask or the like based on the plating via. Accordingly, consideration of the alignment of each layer, which has been required in the conventional batch multilayer stacking method, is no longer necessary in the manufacturing method according to the present invention, and as a result, the via land can be reduced in diameter to about 30 μm using the batch multilayer stacking method. Is possible.
　よって、一般的なサブトラクティブ法によるパターン形成手法を用いた場合においても、例えばビアランド間のスペースを例えば３０μｍとした場合に、最小ビアピッチは６０μｍピッチ程度まで微細化することが可能となる。 Therefore, even when a pattern forming method using a general subtractive method is used, for example, when the space between via lands is set to 30 μm, for example, the minimum via pitch can be reduced to about 60 μm.
　この微細なビアピッチの層を半導体デバイスに近い配線層に配置したことにより、従来と同様の一括多層積層法における粗いピッチ、例えば３００μｍピッチでビアを配置した場合には、ビアランドが３０μｍ、配線幅４０μｍ、配線間隔４０μｍと想定すれば、ビアランド間に配線２本を通すことが可能となる。そのため、配線収容性が飛躍的に向上し、能動部品のような数百～数千端子を有し、かつ２次元的に端子配置される半導体デバイスの配線が可能となる。 By arranging this fine via pitch layer in the wiring layer close to the semiconductor device, when vias are arranged at a rough pitch, for example, 300 μm pitch in the same batch multilayer stacking method as in the prior art, via land is 30 μm and wiring width is 40 μm. Assuming that the wiring interval is 40 μm, two wirings can be passed between via lands. Therefore, the wiring capacity is dramatically improved, and wiring of a semiconductor device having hundreds to thousands of terminals such as active parts and having terminals arranged two-dimensionally becomes possible.
本発明の第１の実施例に係る半導体パッケージの概略断面図である。1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention. 本発明の第１の実施例に係る配線層の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the wiring layer which concerns on 1st Example of this invention. 本発明の第１の実施例に係る半導体パッケージの製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 1st Example of this invention. 本発明の第２の実施例に係る半導体パッケージの概略断面図である。It is a schematic sectional drawing of the semiconductor package which concerns on the 2nd Example of this invention. 本発明の第２の実施例に係る半導体パッケージの製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 2nd Example of this invention. 本発明の第３の実施例に係る半導体パッケージの概略断面図である。It is a schematic sectional drawing of the semiconductor package which concerns on the 3rd Example of this invention. 本発明の第３の実施例に係る半導体パッケージの製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor package which concerns on the 3rd Example of this invention. 本発明に係る半導体パッケージの構造例を示す概略断面図である。It is a schematic sectional drawing which shows the structural example of the semiconductor package which concerns on this invention. 従来技術を用いた半導体パッケージの構造例を示す概略断面図である。It is a schematic sectional drawing which shows the structural example of the semiconductor package using a prior art.
　以下に、各視点において可能な実施形態について述べる。まず本発明に係る半導体パッケージについては、前記第２のビアと接続される第２のビアランドは、前記第１のビアランドよりも小さい直径であることが好ましい。 The following describes possible embodiments from each viewpoint. First, in the semiconductor package according to the present invention, it is preferable that the second via land connected to the second via has a smaller diameter than the first via land.
　また、前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該第２のビアは、前記第１のビアのピッチよりも狭いピッチで配列されていることが好ましい。 Further, the first via land and the second wiring layer are connected by the second via, and the second via is arranged at a pitch narrower than the pitch of the first via. preferable.
　また、少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層は、該第２のビアよりも大きな直径を有する第３のビアで隣接配線層と接続されていることが好ましい。 Further, at least one of the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked. Are connected by the second via, and the wiring layer located farthest from the semiconductor device among the other wiring layers is adjacent by a third via having a diameter larger than that of the second via. It is preferable to be connected to the wiring layer.
　また、少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該第２のビアは前記第１のビアのピッチよりも狭いピッチで配列され、該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層は、該第２のビアのピッチよりも広いピッチで配列されている第３のビアで隣接配線層と接続されていることが好ましい。 Further, at least one of the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked. Are connected by the second vias, the second vias are arranged at a pitch narrower than the pitch of the first vias, and are located farthest from the semiconductor device in the other wiring layers The wiring layer is preferably connected to the adjacent wiring layer through third vias arranged at a pitch wider than the pitch of the second via.
　また、少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層の第３のビアランドは、前記第２のビアランドよりも大きい直径を有することが好ましい。 Further, at least one of the semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order, and the first via land and the second wiring layer are stacked. Are connected by the second via, and the third via land of the wiring layer located farthest from the semiconductor device among the other wiring layers has a diameter larger than that of the second via land. Is preferred.
　また、前記第１のビアが導電性ペーストで形成されていることが好ましい。 Further, it is preferable that the first via is formed of a conductive paste.
　また、前記第２のビアはめっきで形成されていることが好ましい。 Further, the second via is preferably formed by plating.
　また、前記ベース基材層の材質はポリイミドとすることができる。 Further, the material of the base substrate layer can be polyimide.
　次に、本発明に係る製造方法については、前記ベース基材層の前記ビア開口をめっきで充填する工程と、前記ベース基材層の両面に突出した配線層を形成する工程とを、めっき及びめっき除去工程によりまとめて行うことができる。　 Next, for the manufacturing method according to the present invention, the step of filling the via openings of the base base material layer with plating, and the step of forming wiring layers protruding on both surfaces of the base base material layer include plating and It can carry out collectively by a plating removal process. *
　また、前記半導体デバイスを一括積層する工程は、配線パターンが形成された複数の前記絶縁樹脂層と前記半導体デバイスとを加熱・加圧によって一括積層することができる。 Further, in the step of collectively laminating the semiconductor devices, a plurality of the insulating resin layers on which wiring patterns are formed and the semiconductor devices can be collectively laminated by heating and pressing.
　また、前記半導体デバイスを一括積層する工程は、前記半導体デバイスの周囲にスペーサを配し、加熱・加圧によって一括積層することができる。 Further, in the step of batch stacking the semiconductor devices, a spacer can be arranged around the semiconductor devices, and batch stacking can be performed by heating and pressing.
　また、前記半導体デバイスを一括積層する工程は、前記電子デバイス上に絶縁樹脂を配して、加熱・加圧によって一括積層することができる。 Further, in the step of batch stacking the semiconductor devices, an insulating resin is disposed on the electronic device, and the semiconductor devices can be stacked by heating and pressurizing.
　次に、本発明の実施例について図面を参照して詳細に説明するが、まず従来技術との差異点を明確にするため、従来技術を用いた構造例及び本発明に係る構造例を比較説明する。好適な実施例はその後に説明する。 Next, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify differences from the prior art, a structural example using the prior art and a structural example according to the present invention will be compared and described. To do. The preferred embodiment will be described later.
（従来技術を用いた構造例）
　図９は、従来技術に係る一括多層積層法を用いた半導体パッケージの一例である。図９では、半導体デバイス１００のデバイス電極１２０がビア１３０を介してビアランド１４０と２段階（層）に接続されている。一括多層積層法による接続である場合には、例えば絶縁樹脂１９０の厚さを４０μｍとしたとき、ビア１３０の直径は接続材料の充填性の観点からφ８０～φ１００μｍであることが望ましい。 (Example of structure using conventional technology)
FIG. 9 is an example of a semiconductor package using the collective multilayer stacking method according to the prior art. In FIG. 9, the device electrode 120 of the semiconductor device 100 is connected to the via land 140 via the via 130 in two stages (layers). In the case of connection by the collective multilayer stacking method, for example, when the thickness of the insulating resin 190 is 40 μm, the diameter of the via 130 is preferably φ80 to φ100 μm from the viewpoint of the filling property of the connection material.
　ここで半導体デバイス１００との位置合わせ精度、ビア形成精度を考慮すればビアランド１４０の直径は、φ２００～φ２５０μｍ程度が妥当であり、ビアランド１４０のピッチは最小で３００μｍピッチ程度となる。この場合には、層内に配されたビアランド１４０同士の間には、一般的なサブトラクティブ法によって形成可能とされる配線幅４０μｍ、配線間隔４０μｍのルールを用いると、ビアランド１４０間には一本の配線も通すことができない。そのため、全ての層に一括多層積層法を用いた場合には、配線の通らない各層ビア１３０と同じピッチとなるため、半導体デバイス１００と半導体パッケージの外部端子とが一対一のストレートビアで層間を接続することしかできず、ビアピッチを変えたり、配線によって端子間を結線したりすることは全く不可能である。そのため、これまでは半導体デバイス１００のピッチを配線形成が可能なピッチまで広げざるを得ず、デバイスサイズが大型化していた。 Here, considering the alignment accuracy with the semiconductor device 100 and via formation accuracy, the diameter of the via land 140 is about φ200 to φ250 μm, and the via land 140 has a minimum pitch of about 300 μm. In this case, if a rule with a wiring width of 40 μm and a wiring interval of 40 μm that can be formed by a general subtractive method is used between the via lands 140 arranged in the layer, there is no difference between the via lands 140. The wiring of a book cannot be passed. For this reason, when the multilayer multi-layer method is used for all the layers, the pitch is the same as that of each layer via 130 through which wiring does not pass. They can only be connected, and it is completely impossible to change the via pitch or connect the terminals by wiring. For this reason, until now, the pitch of the semiconductor device 100 has to be increased to a pitch that enables wiring formation, and the device size has been increased.
（本発明に係る比較構造例）
　本発明に係る半導体パッケージの断面構造例を図８に示す。本構造例では、ベース基材層８の上下面に２つの（配線）層を設け、各（配線）層に第１のビアランド４と第２のビアランド６を設けている。そしてベース基材層８に設けためっき形成による第２のビア７で、第１のビアランド４と第２のビアランド６とを接続している。 (Comparative structure example according to the present invention)
An example of a cross-sectional structure of a semiconductor package according to the present invention is shown in FIG. In this structural example, two (wiring) layers are provided on the upper and lower surfaces of the base substrate layer 8, and the first via land 4 and the second via land 6 are provided on each (wiring) layer. The first via land 4 and the second via land 6 are connected by the second via 7 formed by plating provided on the base substrate layer 8.
　例えば、ベース基材層８に２５μｍ厚のポリイミド材料を用いた場合には、第２のビア７はφ１５μｍ程度で形成可能である。配線のパターニングは、めっきビアである第２のビア７を基準にエッチングマスク等を形成できることから、従来技術における一括多層接続時に必要な各層の位置合わせの考慮が不要となり、第２のビアランド６をφ３０μｍ程度まで小径化することが可能となる。ベース基材層８の上面層では、第１のビア３のピッチを３００μｍとした場合に、第１のビアランド４のサイズによって制約を受けることから、この面での配線層形成は困難であるが、ベース基材層８の下面層では、第２のビア７を介して接続することにより第２のビアランド６が適用可能となる。 For example, when a polyimide material having a thickness of 25 μm is used for the base substrate layer 8, the second via 7 can be formed with a diameter of about 15 μm. In the patterning of the wiring, an etching mask or the like can be formed with reference to the second via 7 which is a plating via. Therefore, it is not necessary to consider the alignment of each layer necessary for the collective multi-layer connection in the prior art. The diameter can be reduced to about φ30 μm. In the upper surface layer of the base substrate layer 8, when the pitch of the first vias 3 is set to 300 μm, it is restricted by the size of the first via land 4, so that it is difficult to form a wiring layer on this surface. The second via land 6 can be applied to the lower surface layer of the base substrate layer 8 by connecting via the second via 7.
　この場合、第２のビアランド６はφ３０μｍ程度であるため、第２のビアランド６を第１のビアランド４のピッチと同じ３００μｍで配置すれば、第２のビアランド６同士の間隔は２７０μｍ確保可能である。よって、図８の最下層の配線層に示すように、配線幅４０μｍ、配線間隔４０μｍのルールを用いた場合においても、第２のビアランド６同士の間に少なくとも２本の配線５を通すことが可能となる。このように配線収容性が飛躍的に高まり、能動部品のような多ピンかつ２次元配置の端子を有する半導体デバイスへの適用が可能となる。 In this case, since the second via land 6 has a diameter of about 30 μm, if the second via land 6 is arranged at the same 300 μm as the pitch of the first via land 4, the interval between the second via lands 6 can be ensured to 270 μm. . Therefore, as shown in the lowermost wiring layer in FIG. 8, even when the rule of the wiring width 40 μm and the wiring interval 40 μm is used, at least two wirings 5 can be passed between the second via lands 6. It becomes possible. In this way, the wiring capacity is drastically improved, and it becomes possible to apply to a semiconductor device having a multi-pin and two-dimensionally arranged terminal such as an active component.
（実施例１）
　図１は、本発明の第１の実施例に係る半導体パッケージの概略断面図を示す。ベース基材層８の上面及び下面には、それぞれ第１の配線層Ａ及び第２の配線層Ｂが配設されている。第１の配線層Ａには、配線５、第１のビアランド４及び第２のビアランド６が設けられている。第２の配線層Ｂには、配線５、第２のビアランド６及び第２の配線層Ｂよりさらに下層に配置するデバイス等に接続するための第３のビアランド２０を設けている。半導体デバイス１のデバイス電極２と、第１の配線層Ａの第１のビアランド４とは、第１のビア３で接続されている。第１の配線層Ａの各ビアランド４、６は、第２の配線層Ｂの各ビアランド６、２０と、ベース基材層８の内部に配設した第２のビア７によって接続されている。半導体デバイス１とベース基材層８の間は絶縁樹脂９が充填されている。 Example 1
FIG. 1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention. A first wiring layer A and a second wiring layer B are disposed on the upper surface and the lower surface of the base substrate layer 8, respectively. The first wiring layer A is provided with a wiring 5, a first via land 4, and a second via land 6. The second wiring layer B is provided with a third via land 20 for connecting to the wiring 5, the second via land 6, and a device or the like disposed below the second wiring layer B. The device electrode 2 of the semiconductor device 1 and the first via land 4 of the first wiring layer A are connected by the first via 3. The via lands 4 and 6 of the first wiring layer A are connected to the via lands 6 and 20 of the second wiring layer B by the second vias 7 disposed inside the base substrate layer 8. An insulating resin 9 is filled between the semiconductor device 1 and the base substrate layer 8.
　次に本発明の第１の実施例における製造方法について説明する。図２は、ベース基材層８の上下面に配線層（配線パターン）Ａ、Ｂを形成するまでの工程を断面で示している。図２（ａ）に示すように、ベース基材層８の片面（下面）に予め厚膜銅１２が形成してあり、ベース基材層８のうちの第２のビア７を形成する箇所にレーザ加工によってビア開口１４を形成する。ベース基材層８には、例えばポリイミド基材が適用でき、２５μｍ厚の基材の場合には、ビア開口１４の径はφ１５μｍ～φ２０μｍ程度が好適である。 Next, the manufacturing method in the first embodiment of the present invention will be described. FIG. 2 is a cross-sectional view showing a process until the wiring layers (wiring patterns) A and B are formed on the upper and lower surfaces of the base substrate layer 8. As shown in FIG. 2A, thick film copper 12 is formed in advance on one surface (lower surface) of the base substrate layer 8, and the second via 7 of the base substrate layer 8 is formed. Via openings 14 are formed by laser processing. For example, a polyimide base material can be applied to the base base material layer 8. In the case of a base material having a thickness of 25 μm, the diameter of the via opening 14 is preferably about φ15 μm to φ20 μm.
　次に、図２（ｂ）に示すようにベース基材層８の両面に銅めっきによって銅めっき層１３を形成する。この際、ビア開口１４のめっき充填も同時に行う。この部分が第２のビア７となる部分である。めっき厚は、配線の微細化要求度によって最適値は異なるが、配線幅／配線間隔が３０μｍ／３０μｍ程度を狙う場合には、８μｍ～１２μｍ程度が望ましい。 Next, as shown in FIG. 2B, a copper plating layer 13 is formed on both surfaces of the base substrate layer 8 by copper plating. At this time, plating filling of the via opening 14 is simultaneously performed. This portion is a portion that becomes the second via 7. The optimum value of the plating thickness varies depending on the degree of requirement for miniaturization of the wiring, but when the wiring width / wiring interval is aimed at about 30 μm / 30 μm, it is preferably about 8 μm to 12 μm.
　次に図２（ｃ）に示すように、めっき上に感光性レジスト１５を形成する。次いで図２（ｄ）に示すように、露光・現像によって、銅めっきをエッチングする箇所の感光性レジスト１５を除去し、銅エッチングを行う。最後に余計なレジストを除去して、図２（ｅ）に示すようにベース基材層８の両面への配線層Ａ、Ｂの形成が完了する。 Next, as shown in FIG. 2C, a photosensitive resist 15 is formed on the plating. Next, as shown in FIG. 2 (d), the photosensitive resist 15 at the portion where the copper plating is to be etched is removed by exposure and development, and copper etching is performed. Finally, excess resist is removed, and the formation of the wiring layers A and B on both surfaces of the base substrate layer 8 is completed as shown in FIG.
　ここでは低コストなプロセスの一例としてエッチングによって配線層を形成する例を示したが、例えばセミアデイティブ工法などによってめっきレジストを用いて配線パターンを形成してもよい。この場合には、より微細な配線パターンが得られるという効果が期待できる。 Here, an example of forming a wiring layer by etching is shown as an example of a low-cost process, but a wiring pattern may be formed using a plating resist by a semi-additive method, for example. In this case, the effect of obtaining a finer wiring pattern can be expected.
　図３は、ベース基材層８の上面配線層Ａに半導体デバイス１を一括積層法によって実装する工程を断面で示している。図２の工程で配線層Ａ、Ｂが形成されたベース基材層８（図３（ａ）に示す）の配線層Ａの上に、図３（ｂ）に示すようにプリプレグ１６（絶縁樹脂９に相当）を貼り付ける。接着可能な材料であればプリプレグに限るものではなく硬化して固体化するエポキシ系の接着材や感光性ポリイミド等でもよく、フィルム状のものや液状のものも利用できる。フィルムの場合の貼り付けは真空ラミネータや真空プレス機で行い、液状の場合にはスピンコータやカーテンコータなどで行う。また、一度硬化させた後にさらにその上に接着剤層を形成してもよい。 FIG. 3 shows a cross-sectional view of a process of mounting the semiconductor device 1 on the upper surface wiring layer A of the base substrate layer 8 by a batch lamination method. As shown in FIG. 3B, a prepreg 16 (insulating resin) is formed on the wiring layer A of the base substrate layer 8 (shown in FIG. 3A) on which the wiring layers A and B are formed in the step of FIG. 9). The material is not limited to a prepreg as long as it can be bonded, and may be an epoxy adhesive or a photosensitive polyimide that hardens and solidifies, and a film-like material or a liquid material can also be used. In the case of a film, the attachment is performed with a vacuum laminator or a vacuum press, and when it is liquid, it is performed with a spin coater or a curtain coater. Further, after curing once, an adhesive layer may be further formed thereon.
　次に図３（ｃ）に示すようにビア開口１４を形成するが、これは感光性材料でない場合にはレーザによって行うのが一般的である。感光性の場合には、露光・現像によって開口する。必要に応じてデスミア処理を行い、ビア開口１４の底面の有機残渣を除去することが望ましい。 Next, as shown in FIG. 3C, a via opening 14 is formed, which is generally performed by a laser if it is not a photosensitive material. In the case of photosensitivity, the aperture is opened by exposure and development. Desirably, desmear treatment is performed as necessary to remove organic residues on the bottom surface of the via opening 14.
　次に図３（ｄ）に示すようにビア開口１４に接続材料１７（第１のビア３に相当）を充填する。接続材料１７には、一般的には熱硬化性あるいは焼結するＡｇペースト材料を用いるが、Ｃｕペーストやはんだのように溶融して接合する材料なども好適に利用できる。 Next, as shown in FIG. 3D, the via opening 14 is filled with a connection material 17 (corresponding to the first via 3). As the connection material 17, an Ag paste material that is thermosetting or sintered is generally used, but a material that is melted and joined, such as Cu paste or solder, can also be suitably used.
　最後に半導体デバイス１を搭載し、加熱・加圧によってプリプレグ１６及び接続材料１７を硬化して図３（ｅ）に示すように組み立てが完了する。特にこの図に示すように、デバイス電極２や第１のビアランド４を突出させていることによって、接続材料１７が圧縮状態となって硬化されるため、信頼性の高い接続を得ることができる。 Finally, the semiconductor device 1 is mounted, and the prepreg 16 and the connection material 17 are cured by heating and pressurization, and the assembly is completed as shown in FIG. In particular, as shown in this figure, by projecting the device electrode 2 and the first via land 4, the connection material 17 is compressed and hardened, so that a highly reliable connection can be obtained.
　以上のように、低コスト化が図れる一括多層積層の技術を用いていながら、小径のめっきビア及びビアランドを適用したことにより、配線収容性の非常に高い半導体パッケージが実現できるとともに、配線層の積層数を減らすことも可能となりより低コストな半導体パッケージを実現できるという効果も有している。 As described above, a semiconductor package having a very high wiring capacity can be realized by applying small-diameter plating vias and via lands while using a multilayer multi-layer lamination technique capable of reducing the cost. It is also possible to reduce the number and to realize a lower cost semiconductor package.
（実施例２）
　次に、本発明の第２の実施例について図面を参照して詳細に説明する。図４は、本発明の第２の実施例に係る半導体パッケージの断面概略図である。半導体デバイス１のデバイス電極２から下層の構造は実施例１と同様であるので説明は省略する。 (Example 2)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a schematic cross-sectional view of a semiconductor package according to a second embodiment of the present invention. Since the structure below the device electrode 2 of the semiconductor device 1 is the same as that of the first embodiment, the description thereof is omitted.
　実施例２では、半導体デバイス１がベース基材層８よりも小さい場合について説明する。この場合、一括多層積層法を用いたときに半導体デバイス１の周辺を均一に加圧できるようにするため、半導体デバイス１の周囲にスペーサ１０を配しており、さらにスペーサ１０と半導体デバイス１の上面及びスペーサ１０と半導体デバイス１の間には樹脂１１を充填している。これにより、半導体デバイス１の周囲も適正に加圧されるとともに、樹脂１１を配したことによって、一括積層過程での圧力の均整化を図っている。 Example 2 describes a case where the semiconductor device 1 is smaller than the base substrate layer 8. In this case, a spacer 10 is arranged around the semiconductor device 1 so that the periphery of the semiconductor device 1 can be uniformly pressurized when the collective multilayer stacking method is used. Resin 11 is filled between the upper surface and the spacer 10 and the semiconductor device 1. As a result, the periphery of the semiconductor device 1 is also appropriately pressurized, and the resin 11 is arranged to achieve a uniform pressure in the batch stacking process.
　次に本発明の第２の実施例における製造方法について説明する。図５は、ベース基材層８に半導体デバイス１を一括積層法によって実装する工程を断面で示している。図５（ａ）から図５（ｄ）までは、実施例１と同様（図３で説明）であるので説明は省略する。 Next, a manufacturing method in the second embodiment of the present invention will be described. FIG. 5 shows a cross-sectional view of the process of mounting the semiconductor device 1 on the base substrate layer 8 by the batch lamination method. Since FIG. 5A to FIG. 5D are the same as in the first embodiment (described in FIG. 3), the description thereof is omitted.
　図５（ｄ）まで完了した後、半導体デバイス１を搭載し、その周囲にスペーサ１０を搭載する。さらにそれらの上に樹脂フィルム（樹脂１１）を搭載した後、加熱・加圧によってプリプレグ１６、接続材料１７、樹脂１１を硬化して、図５（ｅ）に示すように組み立てが完了する。樹脂フィルムには加熱により液化するものを用い、半導体デバイス１とスペーサ１０の間が液化した樹脂フィルム（樹脂１１）で充填され、間隙が完全に充填された状態とすることが望ましい。これにより半導体パッケージの信頼性が向上する。また、半導体デバイス１とスペーサ１０の厚さは等しい厚さとすることが望ましく、厚さが等しいほど、均一な荷重がプリプレグ１６（絶縁樹脂９）に加わり、信頼性の高い接続を得ることができる。 After completion of FIG. 5D, the semiconductor device 1 is mounted, and the spacer 10 is mounted around it. Furthermore, after mounting a resin film (resin 11) on them, the prepreg 16, the connecting material 17, and the resin 11 are cured by heating and pressing, and the assembly is completed as shown in FIG. 5 (e). It is desirable to use a resin film that is liquefied by heating, and the space between the semiconductor device 1 and the spacer 10 is filled with a liquefied resin film (resin 11), and the gap is completely filled. This improves the reliability of the semiconductor package. Further, it is desirable that the semiconductor device 1 and the spacer 10 have the same thickness. As the thickness is equal, a uniform load is applied to the prepreg 16 (insulating resin 9), and a highly reliable connection can be obtained. .
（実施例３）
　図６は、本発明の第３の実施例に係る半導体パッケージの断面概略図である。図４に示す実装構造（実施例２）の下に更に一層の配線層と絶縁層を追加した構造としている。ベース基材層８の上下面に配線層Ａ、Ｂを形成した構造は実施例１と同様であるので説明は省略する。 (Example 3)
FIG. 6 is a schematic sectional view of a semiconductor package according to a third embodiment of the present invention. A further wiring layer and an insulating layer are added below the mounting structure (Example 2) shown in FIG. Since the structure in which the wiring layers A and B are formed on the upper and lower surfaces of the base substrate layer 8 is the same as that of the first embodiment, the description thereof is omitted.
　実施例２と同様、半導体デバイス１が基材８よりも小さいことから一括多層積層手法を用いたときに半導体デバイス１の周辺を均一に加圧できない。従って半導体デバイス１の周囲にスペーサ１０を配しており、さらにスペーサ１０の上面及びスペーサ１０と半導体デバイス１の間には樹脂１１を充填している。 As in Example 2, since the semiconductor device 1 is smaller than the base material 8, the periphery of the semiconductor device 1 cannot be uniformly pressurized when the collective multilayer stacking method is used. Therefore, the spacer 10 is arranged around the semiconductor device 1, and the resin 11 is filled between the upper surface of the spacer 10 and between the spacer 10 and the semiconductor device 1.
　ベース基材層８の下には、接着剤１９を介して基材１８が接着固定されその下には第３の配線層Ｃが形成されている。この配線層Ｃと、配線層Ｂに形成された第３のビアランド２０とが第３のビア３０によって電気的、機械的に接続されている。第３のビア３０の直径は、第２のビア７の直径よりも大きい。第３の（最下層の）配線層Ｃ（ビアランド）にはマザーボードとの接続のためのはんだバンプ２１が形成された構造としている。 Under the base substrate layer 8, the substrate 18 is bonded and fixed via an adhesive 19, and a third wiring layer C is formed thereunder. The wiring layer C and the third via land 20 formed in the wiring layer B are electrically and mechanically connected by the third via 30. The diameter of the third via 30 is larger than the diameter of the second via 7. The third (lowermost layer) wiring layer C (via land) has a structure in which solder bumps 21 for connection to the mother board are formed.
　次に本発明の第３の実施例における製造方法について説明する。図７は、ベース基材層８から半導体デバイス１を一括積層手法によって実装する工程を断面で示している。図７（ａ）から図７（ｄ）までの製造工程は実施例１と同様（図３で説明）であるので説明は省略する。 Next, a manufacturing method according to the third embodiment of the present invention will be described. FIG. 7 shows a cross-sectional view of the process of mounting the semiconductor device 1 from the base substrate layer 8 by the collective lamination method. Since the manufacturing steps from FIG. 7A to FIG. 7D are the same as those in the first embodiment (described in FIG. 3), description thereof will be omitted.
　図７（ｄ）の構造の上方向には、半導体デバイス１と、その周囲にスペーサ１０、さらにそれらの上に樹脂フィルム（樹脂１１）を積み重ねる。一方下方向には、片面に配線がパターニングされた基材１８上に接着剤１９を貼り合わせ、レーザ加工によって開口したビア開口に接続材料（第３のビア３０に相当）を充填したものを配し、図７（ｅ）に示すようにこれらを水平方向の位置合わせを行う。最後に一括して加熱・加圧することによってプリプレグ１６、接続材料１７、樹脂１１及び接着剤１９を硬化し、最下層の配線層Ｃにはんだバンプ２１を形成して、図６に示す構造が完成する。このように、配線層は何層でも一括して積層可能であることはいうまでもない。 7D, the semiconductor device 1, the spacer 10 around the semiconductor device 1, and a resin film (resin 11) are stacked on them. On the other hand, the adhesive 19 is bonded on the base material 18 whose wiring is patterned on one side, and a via opening opened by laser processing is filled with a connection material (corresponding to the third via 30). Then, as shown in FIG. 7E, these are aligned in the horizontal direction. Finally, the prepreg 16, the connecting material 17, the resin 11 and the adhesive 19 are cured by collectively heating and pressing, and the solder bumps 21 are formed on the lowermost wiring layer C to complete the structure shown in FIG. 6. To do. In this way, it goes without saying that any number of wiring layers can be stacked together.
　以上、本発明を上記実施例に即して説明したが、本発明は上記実施例の構成にのみ制限されるものではなく、本発明の範囲内で当業者であればなしうるであろう各種変形、修正を含むことはもちろんである。 Although the present invention has been described with reference to the above embodiments, the present invention is not limited only to the configurations of the above embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.
１　半導体デバイス
２　デバイス電極
３　第１のビア
４　第１のビアランド
５　配線
６　第２のビアランド
７　第２のビア
８　ベース基材層
９　絶縁樹脂
１０　スペーサ
１１　樹脂
１２　厚膜銅
１３　銅めっき
１４　ビア開口
１５　感光性レジスト
１６　プリプレグ
１７　接続材料
１８　基材
１９　接着剤
２０　第３のビアランド
２１　はんだバンプ
３０　第３のビア
１００　半導体デバイス
１２０　デバイス電極
１３０　ビア
１４０　ビアランド
１９０　絶縁樹脂
Ａ　第１の配線層
Ｂ　第２の配線層
Ｃ　第３の配線層 1 Semiconductor Device 2 Device Electrode 3 First Via 4 First Via Land 5 Wiring 6 Second Via Land 7 Second Via 8 Base Base Layer 9 Insulating Resin 10 Spacer 11 Resin 12 Thick Film Copper 13 Copper Plating 14 Via Opening 15 Photosensitive resist 16 Prepreg 17 Connection material 18 Base material 19 Adhesive 20 Third via land 21 Solder bump 30 Third via 100 Semiconductor device 120 Device electrode 130 Via 140 Via land 190 Insulating resin A First wiring layer B Second Wiring layer C of the third wiring layer

Claims (15)

  1. 　少なくとも一つの半導体デバイスと、少なくとも第１の配線層及び第２の配線層とが、この順で積層された部分を含む半導体パッケージであって、
    　該半導体デバイスのデバイス電極と該第１の配線層の第１のビアランドとが第１のビアを介して接続され、かつ該デバイス電極と該第１のビアとが直接接しており、
    　該第１の配線層と該第２の配線層とが、該第１のビアよりも小径な第２のビアと接続され、
    　該第１の配線層と該第２の配線層は、一つのベース基材層の両面に、それぞれ該ベース基材層から突出して構成されている、
    ことを特徴とする半導体パッケージ。     A semiconductor package including a portion in which at least one semiconductor device and at least a first wiring layer and a second wiring layer are stacked in this order;
    A device electrode of the semiconductor device and a first via land of the first wiring layer are connected via a first via, and the device electrode and the first via are in direct contact;
    The first wiring layer and the second wiring layer are connected to a second via having a smaller diameter than the first via;
    The first wiring layer and the second wiring layer are configured to protrude from the base substrate layer on both surfaces of one base substrate layer, respectively.
    A semiconductor package characterized by that.
  2. 　前記第２のビアと接続される第２のビアランドは、前記第１のビアランドよりも小さい直径であることを特徴とする、請求項１に記載の半導体パッケージ。 2. The semiconductor package according to claim 1, wherein the second via land connected to the second via has a smaller diameter than the first via land.
  3. 　前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該第２のビアは、前記第１のビアのピッチよりも狭いピッチで配列されていることを特徴とする、請求項１又は２に記載の半導体パッケージ。 The first via land and the second wiring layer are connected by the second via, and the second via is arranged at a pitch narrower than the pitch of the first via. The semiconductor package according to claim 1 or 2.
  4. 　少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、
    　前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、
    　該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層は、該第２のビアよりも大きな直径を有する第３のビアで隣接配線層と接続されていることを特徴とする、請求項１～３のいずれか一に記載の半導体パッケージ。     At least one semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order,
    The first via land and the second wiring layer are connected by the second via;
    Among the other wiring layers, the wiring layer located farthest from the semiconductor device is connected to the adjacent wiring layer by a third via having a diameter larger than that of the second via. The semiconductor package according to any one of claims 1 to 3.
  5. 　少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、
    　前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、該第２のビアは前記第１のビアのピッチよりも狭いピッチで配列され、
    　該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層は、該第２のビアのピッチよりも広いピッチで配列されている第３のビアで隣接配線層と接続されていることを特徴とする、請求項１～３のいずれか一に記載の半導体パッケージ。     At least one semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order,
    The first via land and the second wiring layer are connected by the second via, and the second via is arranged at a pitch narrower than the pitch of the first via,
    Of the other wiring layers, the wiring layer located farthest from the semiconductor device is connected to the adjacent wiring layer by the third vias arranged at a pitch wider than the pitch of the second vias. The semiconductor package according to any one of claims 1 to 3, wherein the semiconductor package is characterized in that:
  6. 　少なくとも一つの前記半導体デバイス、前記第１の配線層、前記第２の配線層及び１以上の他の配線層が、この順で積層され、
    　前記第１のビアランドと前記第２の配線層とが前記第２のビアで接続され、
    　該他の配線層のうち、該半導体デバイスから最も離れた位置にある配線層の第３のビアランドは、前記第２のビアランドよりも大きい直径を有することを特徴とする、請求項１～３のいずれか一に記載の半導体パッケージ。     At least one semiconductor device, the first wiring layer, the second wiring layer, and one or more other wiring layers are stacked in this order,
    The first via land and the second wiring layer are connected by the second via;
    The third via land of the wiring layer located farthest from the semiconductor device among the other wiring layers has a diameter larger than that of the second via land. The semiconductor package as described in any one.
  7. 　前記第１のビアが導電性ペーストで形成されていることを特徴とする、請求項１～６のいずれか一に記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 6, wherein the first via is formed of a conductive paste.
  8. 　前記第２のビアはめっきで形成されていることを特徴とする、請求項１～７のいずれか一に記載の半導体パッケージ。 8. The semiconductor package according to claim 1, wherein the second via is formed by plating.
  9. 　前記ベース基材層の材質がポリイミドであることを特徴とする、請求項１～８のいずれか一に記載の半導体パッケージ。 9. The semiconductor package according to claim 1, wherein the base substrate layer is made of polyimide.
  10. 　ベース基材層にビア開口を形成する工程と、
    　該ビア開口をめっきで充填する工程と、
    　該ベース基材層の両面に突出した配線層を形成する工程と、
    　該ベース基材層及び該配線層の上に絶縁樹脂層を形成する工程と、
    　該絶縁樹脂層にビア開口を形成し、該ビア開口に接続材料を充填する工程と、
    　該接続材料の上部に半導体デバイスを加熱・加圧によって一括積層する工程と、
    を含む半導体パッケージの製造方法。     Forming via openings in the base substrate layer;
    Filling the via opening with plating;
    Forming a wiring layer protruding on both sides of the base substrate layer;
    Forming an insulating resin layer on the base substrate layer and the wiring layer;
    Forming a via opening in the insulating resin layer, and filling the via opening with a connection material;
    A step of laminating a semiconductor device on top of the connecting material by heating and pressing; and
    A method for manufacturing a semiconductor package comprising:
  11. 　前記ベース基材層の前記ビア開口をめっきで充填する工程と、前記ベース基材層の両面に突出した配線層を形成する工程とを、めっき及びめっき除去工程によりまとめて行うことを特徴とする、請求項１０に記載の製造方法。 The step of filling the via openings of the base base material layer with plating and the step of forming wiring layers protruding on both surfaces of the base base material layer are collectively performed by plating and plating removal steps. The manufacturing method according to claim 10.
  12. 　前記半導体デバイスを一括積層する工程は、配線パターンが形成された複数の前記絶縁樹脂層と前記半導体デバイスとを加熱・加圧によって一括積層する工程である、請求項１０又は１１に記載の製造方法。 The manufacturing method according to claim 10 or 11, wherein the step of batch stacking the semiconductor devices is a step of batch stacking the plurality of insulating resin layers on which wiring patterns are formed and the semiconductor devices by heating and pressing. .
  13. 　前記半導体デバイスを一括積層する工程は、前記半導体デバイスの周囲にスペーサを配し、加熱・加圧によって一括積層する工程を含む、請求項１０～１２のいずれか一に記載の製造方法。 The manufacturing method according to any one of claims 10 to 12, wherein the step of collectively laminating the semiconductor devices includes a step of collectively laminating spacers around the semiconductor devices and laminating them by heating and pressing.
  14. 　前記半導体デバイスを一括積層する工程は、前記電子デバイス上に絶縁樹脂を配して、加熱・加圧によって一括積層する工程を含む、請求項１０～１３のいずれか一に記載の製造方法。 The manufacturing method according to any one of claims 10 to 13, wherein the step of collectively laminating the semiconductor devices includes a step of collectively laminating an insulating resin on the electronic device and heating and pressing.
  15. 　請求項１～９のいずれか一に記載の半導体パッケージを含んで構成された電子機器。 An electronic device comprising the semiconductor package according to any one of claims 1 to 9.
PCT/JP2010/051803 2009-02-09 2010-02-08 Semiconductor package and manufacturing method therefor WO2010090316A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012736A (en) * 1998-06-26 2000-01-14 Ngk Spark Plug Co Ltd Ceramic multilayer wiring board for flip chip
JP2002246752A (en) * 2001-02-19 2002-08-30 Murata Mfg Co Ltd Via hole structure of ceramic multilayer board
JP2008108880A (en) * 2006-10-25 2008-05-08 Matsushita Electric Ind Co Ltd Multilayer printed circuit board and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012736A (en) * 1998-06-26 2000-01-14 Ngk Spark Plug Co Ltd Ceramic multilayer wiring board for flip chip
JP2002246752A (en) * 2001-02-19 2002-08-30 Murata Mfg Co Ltd Via hole structure of ceramic multilayer board
JP2008108880A (en) * 2006-10-25 2008-05-08 Matsushita Electric Ind Co Ltd Multilayer printed circuit board and its manufacturing method

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