JP2000012736A - Ceramic multilayer wiring board for flip chip - Google Patents

Ceramic multilayer wiring board for flip chip

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Publication number
JP2000012736A
JP2000012736A JP18000598A JP18000598A JP2000012736A JP 2000012736 A JP2000012736 A JP 2000012736A JP 18000598 A JP18000598 A JP 18000598A JP 18000598 A JP18000598 A JP 18000598A JP 2000012736 A JP2000012736 A JP 2000012736A
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via conductor
ceramic
layer
conductor
via
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JP3098992B2 (en
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Yoshitoshi Nomura
俊寿 野村
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Ngk Spark Plug Co Ltd
日本特殊陶業株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a ceramic multilayer wiring board for a flip chip, that can surely connect the flip chip to a pad and also can secure the insulation property between a via conductor for forming the pad and a conductor layer inside a board.
SOLUTION: A via conductor being, exposed on the surface of a board consists of an outermost-surface via conductor 12 which is formed in a ceramic layer 2a of an outermost surface and an inner via conductor 11 formed in an inner ceramic layer 2b, the diameter of the outermost-surface via conductor 12 is larger than that of the inner via conductor 11, and at the same time, a pad 13 that consists of a plating layer and connects a flip chip is formed at the upper end part of the outermost surface via conductor 12. The via conductor 12 with the large diameter and the pad 13 allow the flip chip being mounted afterward to be connected surely, and at the same time, the inner via conductor 11 with the small diameter allows a clearance 5 sufficient for insulation to be formed between the inner via conductor 11 and an inner metal planar layer (conductor layer) 3.
COPYRIGHT: (C)2000,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、複数のセラミック層の間に導体層がそれぞれ形成され、且つその表面上に半導体素子等のチップと接続するためのパッドを有するフリップチップ用セラミック多層配線基板に関する。 The present invention relates is formed conductor layer between the plurality of ceramic layers respectively, and the ceramic multilayer wiring board for flip chip having a pad for connection with a chip such as a semiconductor element on its surface on.

【0002】 [0002]

【従来の技術】近年における小型化、高集積化の要求に連れて、フリップチップ用セラミック多層配線基板も小型化、薄肉化に対応するため、配線の高密度化と併せて、フリップチップと接続するパッド同士間のピッチも狭くする傾向にある。 Miniaturization of the Related Art In recent years, as the demand for high integration, even miniaturized ceramic multilayer wiring board for flip-chip, in order to respond to thinning, along with high density wiring, connected to the flip-chip pitch tends to narrow between the pads between the. 一般に、フリップチップを表面上に搭載するセラミック多層配線基板40は、図5(A)に示すように、複数のセラミック層43〜45と、これらの間にタングステン、モリブデン等の高融点金属の導体ペーストをスクリーン印刷して焼成した次述する導体層と有し、追ってその表面42上に半導体素子等のチップ50が搭載される。 In general, the ceramic multi-layer wiring substrate 40 for mounting a flip chip on the surface, as shown in FIG. 5 (A), a plurality of the ceramic layers 43 to 45, tungsten between these conductors of a refractory metal such as molybdenum paste includes a conductive layer which will be described next has been calcined by screen printing, Otte chip 50 such as a semiconductor element is mounted on the surface 42.

【0003】また、フリップチップ接続用のパッドは、 [0003] In addition, the pad for flip-chip connection,
接続の信頼性確保の観点から該パッド径はできる限り大きいことが望ましい。 It is desirable from the standpoint of ensuring reliability of the connection as large as possible is the pad size. このために、パッドに接続する基板内のビア導体の上端部にメタライズ印刷による大径のカバーパッドを形成する方法もあるが、上記印刷は極めて精緻であるため生産性の点で好ましくない。 Therefore, there is a method of forming a large-diameter cover pad according metallization printing on the upper end of the via conductor in the substrate to be connected to the pads, but the print is not preferable in terms of productivity because it is very elaborate. 一方、基板内部のビア導体の径を大きくし、これを直接フリップチップ接続用のパッドとして活用する方法も考えられる。 On the other hand, to increase the diameter of the substrate inside the via conductor is also conceivable a method of utilizing it as a pad for direct flip chip bonding.

【0004】 [0004]

【発明が解決すべき課題】このため、図5(B)及び(b) Therefore THE INVENTION problem to be solved is], and FIG. 5 (B) and (b)
に示すように、パッド51と内部の導体層47とを導通するビア導体48を大径にすると、大径の該パッド51 As shown, when the via conductor 48 to conduct the pad 51 and the inner conductor layer 47 to a larger diameter, the larger diameter the pad 51
は追って搭載されるチップ50との接続が確実になる。 Is ensured connection to the chip 50 to Otte mounted.
しかし、ビア導体48とこれが貫通する最上側のメタルプレーン層(導体層)46との隙間49が小さくなるため、両者間の絶縁性が不十分になるという問題が生じる。 However, since the gap 49 between the uppermost metal plane layers (conductor layers) 46 and via conductor 48 which penetrates decreases, a problem that insulation between them is insufficient arises. 一方、パッドの狭ピッチ化にも対応するため、図5 On the other hand, to cope with narrow pitch of the pad, Figure 5
(C)及び(c)に示すように、パッド54と内部の導体層47を導通するビア導体52を小径にすると、該ビア導体52と最上側のメタルプレーン層46との隙間53を大きくでき、両者間の絶縁性が確保される。 (C) and as (c), when the via conductor 52 to conduct the pad 54 and the internal conductor layer 47 is smaller in diameter, can be increased gap 53 between the via conductor 52 and the top side of the metal plane layer 46 , insulation therebetween can be secured. しかし、係る小径のパッド54では追って搭載されるチップ50との接続が不安定になり易いという問題点があった。 However, there has been a connection liable to become unstable point of the chip 50 which is the pad 54 Otte mounting diameter of.

【0005】本発明は上述の問題点を解決し、フリップチップとパッドとの接続が確実に行え、且つ該パッドを形成するビア導体と基板内部の導体層との間の絶縁性も確保できるフリップチップ用セラミック多層配線基板を提供することを課題とする。 [0005] The present invention solves the above problems, the connection between the flip chip and the pads reliably performed, and flip the insulating can be ensured between the via conductor and the substrate internal conductor layer forming the pad to provide a ceramic multilayer wiring substrate for a chip to an object.

【0006】 [0006]

【課題を解決するための手段】本発明は、上記課題を解決するため、フリップチップ接続用のパッドに導通するビア導体の径を、その上端部と内部とで変化させることに着想して成されたものである。 The present invention SUMMARY OF] In order to solve the above problems, the diameter of the via conductor electrically connected to the pad for flip chip connection, and inspired be varied from the interior to the upper end thereof formed it is those that have been. 即ち、本発明のフリップチップ用セラミック多層配線基板は、基板の表面にフリップチップと接続するパッドを有するフリップチップ用セラミック多層配線基板において、基板の表面に露出するビア導体の上端部の径が該ビア導体の内部の径よりも大きくされ、該ビア導体の上端部にメッキ層からなる上記パッドを形成した、ことを特徴とする。 That is, the ceramic multi-layer wiring board for flip-chip of the present invention, the ceramic multi-layer wiring board for flip chip having a pad to be connected to the flip-chip on the surface of the substrate, the diameter of the upper end of the via conductor exposed on the surface of the substrate is the is larger than the diameter of the interior of the via conductors, the formation of the pad of the plating layer on the upper portion of the via conductors, characterized in that. これによれば、フリップチップとの接続と共に内部の導体層との絶縁の双方を確実に行えるセラミック多層配線基板とすることができる。 According to this, it can be a ceramic multilayer wiring substrate reliably perform both the insulation of the inner conductor layers together with the connection of the flip chip.

【0007】また、前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成された内部ビア導体とからなり、上記最表面ビア導体はその上端部から内部ビア導体に向けて縮径するテーパ形状を有する、フリップチップ用セラミック多層配線基板も含まれる。 Further, the via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, and the via conductor formed inside the ceramic layer made, the outermost surface via conductor has a tapered shape whose diameter decreases toward the inside via conductor from its upper end, also includes a ceramic multilayer wiring board for flip-chip. これによれば、パッドに接する最表面ドア導体にテーパを付すことで、フリップチップとの接続及び内部の導体層との絶縁の双方を確実に得ることができる。 According to this, by subjecting the tapered top surface door conductor in contact with the pad, it is possible to obtain both the insulation between the connection and the inner conductor layers of the flip chip surely. 尚、上記テーパ形状を得るため、後述するように事前にセラミック層に形成するビアホールもプレス又はレーザ照射によりテーパ形状に穿設される。 In order to obtain the tapered shape, even a via hole formed in the ceramic layer in advance as will be described later is formed in a tapered shape by a press or laser irradiation.

【0008】更に、前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成された内部ビア導体とからなり、上記最表面ビア導体の径が上記内部ビア導体の径よりも大きい、フリップチップ用セラミック多層配線基板も含まれる。 Furthermore, the via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, and the via conductor formed inside the ceramic layer consists, diameter of the outermost via conductor is larger than the diameter of the inner via conductors also include ceramic multilayer wiring board for flip-chip. これによれば、セラミック層毎に径の異なるビア導体を形成するので、フリップチップとの接続及び内部の導体層との絶縁の双方を確実に得ることができる。 According to this, since to form the via conductors having different diameters for each ceramic layer, it is possible to obtain both the insulation between the connection and the inner conductor layers of the flip chip surely. この場合、ビア導体の径を2段階以上異ならしめることも可能である。 In this case, it is also possible to made different diameters of the via conductors two or more stages.

【0009】加えて、前記最表面ビア導体及び内部ビア導体とは、金属物質とセラミック物質との混合物質からなり、且つ上記最表面ビア導体中のセラミック物質の含有量が上記内部ビア導体中のそれよりも多い、フリップチップ用セラミック多層配線基板も含まれる。 [0009] In addition, the the uppermost surface via conductors and the via conductors, made of a mixture material of metal material and a ceramic material, and the content of the ceramic material in the outermost surface via conductors in the inner via conductors more above also include ceramic multilayer wiring board for flip-chip. これによれば、最表面ビア導体と内部ビア導体の熱膨張率は、これらを囲むセラミック層に近づくため、焼成後の収縮で間隙を生じにく、基板全体の気密性を保つことができる。 According to this, the thermal expansion coefficient of the outermost surface via conductors and the via conductor, to approach the ceramic layer surrounding these, shrinkage in difficulty occurs a gap after sintering, it is possible to maintain the airtightness of the whole substrate. 特に、径の大きい最表面ビア導体中のセラミック物質の含有量を内部ビア導体中よりも多くしたので、気密性を確実に高めることができる。 In particular, the content of the ceramic material in large outermost surface via conductors of diameter since more than in the via conductor can be improved surely airtightness. 尚、最表面ビア導体はその径が大きいため、含有するセラミック物質による電気抵抗は導通の支障にはならない。 Since the outermost surface via conductor diameter thereof is large, the electrical resistance due to the ceramic materials containing not a hindrance of continuity. また、上記セラミック物質の含有量は、熱膨張率と電気抵抗とを考慮して適宜選定すれば良いが、最表面ビア導体中では17〜22 The content of the ceramic material may be suitably selected in consideration of the thermal expansion coefficient and electric resistance, but in the outermost surface via conductors 17 to 22
wt%、内部ビア導体中では3〜15wt%の範囲がそれぞれ好適である。 wt%, the range of 3 to 15% is in the via conductor is preferred, respectively.

【0010】 [0010]

【発明の実施の形態】以下において本発明の実施に好適な形態を図面と共に説明する。 It is described with reference to the accompanying drawings a preferred form in the following DETAILED DESCRIPTION OF THE INVENTION The practice of the present invention. 図1(A)は、本発明の1 1 (A) is 1 of the present invention
つの形態のフリップチップ用セラミック多層配線基板1 One form of flip chip ceramic multilayer wiring board 1
の要部を示す。 Showing the principal part. この基板1は、主にアルミナからなる複数のセラミック層2,4,6と、これらの間ら形成されたメタルプレーン層3及び導体層7を有する。 The substrate 1 mainly includes a plurality of ceramic layers 2, 4, 6 made of alumina, a metal plane layer 3 and the conductive layer 7 which is formed between them, et al. セラミック層2は、薄い上層(最表面のセラミック層)2aと下層2 Ceramic layer 2 (ceramic uppermost layer) thin upper layer 2a and a lower layer 2
b(内部のセラミック層)とからなる。 It consists and b (the ceramic layer). これらのセラミック層2,4,6内には、メタルプレーン層3、導体層7、 These ceramic layers 2, 4, 6, metal plane layer 3, the conductive layer 7,
又は図示しない内部の導体層と、追って表面上に搭載されるフリップチップとを導通するためのビア導体10, Or an inner conductor layer (not shown), Otte via conductor 10 for electrically connecting the flip chip mounted on the surface,
11,12が形成されている。 11 and 12 are formed. 即ち、図1(A)で右側のビア導体11,12はメタルプレーン層3と、中央のビア導体10,11,12は導体層7と、左側のビア導体1 Thus, the right hand side of the via conductor 11, 12 in FIG. 1 (A) and the metal plane layer 3, a center of the via conductors 10, 11, 12 and the conductive layer 7, the left side of the via conductors 1
0,10,11,12は図示しない内部の導体層と導通している。 0,10,11,12 is electrically connected to the inner conductor layer (not shown).

【0011】上記ビア導体12は本発明の最表面ビア導体で、その径は100μmであり、ビア導体10及びビア導体(内部ビア導体)11の径(76μm)よりも大きい。 [0011] The via conductor 12 is the top surface via conductors of the present invention, the diameter is 100 [mu] m, greater than the via conductors 10 and via conductors diameter (the via conductor) 11 (76 .mu.m). 図示で左側のビア導体10は隙間9を介して導体層7と絶縁され、左側及び中央の内部ビア導体11は、図1(B)に示すように、隙間5を介してメタルプレーン層3とそれぞれ絶縁されいる。 Left via conductor 10 illustrated is insulated from the conductive layer 7 through the gap 9, the left and center of the via conductor 11, as shown in FIG. 1 (B), a metal plane layer 3 through the gap 5 which are each insulated. そして、最表面のセラミック層2aの表面に露出する各最表面ビア導体12の上端部には、Ni及びAuメッキ層からなり、ビア導体12 Then, the upper end of each outermost surface via conductors 12 exposed on the surface of the ceramic layer 2a of the outermost surface consists of Ni and Au plating layer, the via conductor 12
と同径のフリップチップ接続用のパッド13が形成されている。 Pads 13 for flip-chip connection having the same diameter are formed as. 尚、各ビア導体10,11にはモリブデン等の金属成分と共に約12wt%の、ビア導体12には約20 Incidentally, about 12 wt% with the metal components such as molybdenum for each via conductor 10 and 11, the via conductor 12 to about 20
wt%のセラミック成分がそれぞれ含まれている。 wt% of the ceramic components are included, respectively.

【0012】従って、上記大径のパッド13は、メッキにより形成したのでビア導体12上に略同径で位置ずれすることなく確実に形成でき、且つ追って搭載されるフリップチップとの接続が確実に行える。 Accordingly, the above-mentioned large-diameter pad 13, so formed by plating can be reliably formed without positional deviation substantially the same diameter on the via conductor 12, and followed by reliably connection between the flip chip to be mounted It can be carried out. 更に、小径のビア導体11,10により十分な隙間5,9が形成できるので、内部のメタルプレーン層3や導体層7との絶縁性も確保される。 Furthermore, since sufficient clearance 5,9 by small diameter of the via conductors 11 and 10 can be formed, insulation between the interior of the metal plane layer 3 and the conductive layer 7 is ensured. しかも、図1(A)中で左側と中央の各ビア導体10,11は互いに接近して配置される狭ピッチであるが、図1(B)に示すように、両者が貫通する各隙間5,5に挟まれたメタルプレーン層3の中央部分3a Moreover, although FIG. 1 (A) each via conductors 10 and 11 left and central in is narrow pitch is disposed close to each other, as shown in FIG. 1 (B), the gaps both through 5 , metal plane layer 3 sandwiched 5 the central portion 3a
も充分な幅寸法を有するので、その電気的特性の劣化も防止できる。 Since also has sufficient width, thereby preventing deterioration of the electrical characteristics.

【0013】係るセラミック多層配線基板1は次のようにして製造される。 [0013] Ceramic multilayer wiring board 1 according is manufactured as follows. 先ず、アルミナを主成分とする複数のグリーンシートを用意し、それぞれの所定の位置にプレスで孔明けすると共に、各々の表面にタングステンやモリブデン等の高融点金属を含むペーストをスクリーン印刷し、導体ペースト層とする。 First, a plurality of green sheets mainly comprising alumina, as well as drilling by pressing the respective predetermined positions, a paste containing a high melting point metal of tungsten or molybdenum was screen-printed on each surface, the conductor the paste layer. また、上記孔内にメタライズインクを充填する。 Also, filling the metallizing ink in the hole. 尚、セラミック層2の上層2 Incidentally, the upper layer 2 of the ceramic layer 2
aと下層2bとなるグリーンシートは予めその他のグリーンシートの約半分の厚さとされ、且つ上層2aとなるグリーンシートにのみ大径の孔を穿設しておく。 Green sheets for a and lower 2b is a thickness of about half of the pre other green sheets, previously drilled large-diameter hole only the green sheet and the upper layer 2a.

【0014】上記メタライズインクは上記と同様な金属の粉末にアルミナ等のセラミック粉を混ぜたものである。 [0014] The metallizing ink is obtained by mixing a ceramic powder such as alumina powder of similar metal as the above. しかも、セラミック層2の上層2aとなるグリーンシートの大きな孔内及び他の小さい孔内に充填されるメタライズインクには、それぞれ焼成後に約20wt%と約12wt%になるようにセラミック粉が含まれている。 Moreover, the metallizing ink to be filled into the ceramic layer large hole of the green sheet to be the second upper layer 2a and other small holes, the ceramic powder contains so that each about 20 wt% after firing and about 12 wt% ing. そして、上記の各グリーンシートを積層・圧着して焼成すると、各グリーンシートはセラミック層2,4,6に、各導体ペースト層はメタルプレーン層3及び導体層7等に、各メタライズインクはビア導体10,11,12となる。 When firing the laminated and pressure bonded to the green sheets described above, each of the green sheets for the ceramic layers 2, 4, 6, each conductor paste layer to the metal plane layer 3 and the conductive layer 7 and the like, each metallizing ink vias the conductors 10, 11, 12. 尚、上記焼成後に熱収縮を生じるが、各ビア導体1 Although resulting in thermal contraction after the firing, the via conductor 1
0,11,12には上記セラミック成分が含まれているので、隣接するセラミック層2,4,6との間に間隙を生じない。 Since the 0,11,12 contains the ceramic component, no gap between the ceramic layers 2, 4, 6 adjacent. 最後に、最表面のセラミック層2aの表面に露出する各最表面ビア導体12に、NiメッキとAuメッキを施すと厚さ約4〜6μmの各パッド13が形成されて、フリップチップ用セラミック多層配線基板1を得ることができる。 Finally, the outermost surface via conductors 12 exposed on the surface of the ceramic layer 2a of the outermost surface, the pad 13 having a thickness of about 4~6μm when subjected to Ni plating and Au plating is formed, a ceramic multilayer for flip-chip it is possible to obtain the wiring board 1.

【0015】図2(A)は異なる形態のフリップチップ用セラミック多層配線基板20を示す。 [0015] FIG. 2 (A) shows a ceramic multilayer wiring substrate 20 for a different form of flip chip. 尚、前記の形態と共通する部分や要素には同じ符号を用いるものとする。 Incidentally, parts and elements common to the embodiment shall be denoted by the same reference numerals.
この配線基板20も、アルミナからなる複数のセラミック層2,4,6と、これらの間ら形成された金属製のメタルプレーン層3及び導体層7を有する。 The wiring board 20 also comprises a plurality of ceramic layers 2, 4, 6 made of alumina, a metal plane layer 3 and the conductor layer 7 of these between et formed metal. 各セラミック層4,6内には導体層7、又は内部の導体層と、追って表面上に搭載されるフリップチップとを導通する内部ビア導体10が形成されている。 Each the ceramic layers 4 and 6 are internally via conductor 10 is formed to conduct with the conductive layer 7, or inner conductor layer, Otte and flip-chip mounted on the surface. 最表面のセラミック層2内には、上端部から下端部に向けて縮径する全体が略逆円錐状のテーパ形状を有する最表面ビア導体14が形成されている。 The ceramic layer 2 on the outermost surface, the outermost surface via conductors 14 which overall has substantially an inverted conical tapered shape that decreases in diameter toward the lower end portion is formed from the upper end. このビア導体14の下端部は内部ビア導体10 Lower end of the via conductor 14 inside the via conductor 10
又はメタルプレーン層3と導通する。 Or conducting the metal plane layer 3. 尚、各ビア導体1 Incidentally, the via conductor 1
0,14も前記同様にセラミック成分を含み、且つ後者が前者より多く含有する。 0,14 also includes the similarly ceramic component, and the latter contains more than the former. 尚、セラミック層4は、本形態における内部のセラミック層である。 Incidentally, the ceramic layer 4 is the ceramic layer in the present embodiment.

【0016】上記内部ビア導体10と導通する各最表面ビア導体14の下端部は、隙間5を介してメタルプレーン層3と絶縁されている。 The lower end of the inner via conductors 10 each outermost surface via conductor 14 to conduct a is insulated from the metal plane layer 3 through the gap 5. また、図2(A)で左側のビア導体10は隙間9を介して導体層7と絶縁されている。 Also, the left side of the via conductor 10 in FIG. 2 (A) is insulated from the conductive layer 7 through the gap 9.
更に、各最表面ビア導体14の上端部には、Niメッキ層及びAuメッキ層からなる最表面ビア導体14と同径のフリップチップ接続用のパッド13が形成されている。 Further, the upper end portion of the outermost surface via conductors 14, the pad 13 for flip-chip connection of the same diameter as the outermost surface via conductor 14 made of Ni plating layer and an Au plating layer is formed. 従って、この多層配線基板20も上記大径のパッド13により追って搭載されるフリップチップとの接続が確実に行えると共に、最表面ビア導体14の下端部及び小径の内部ビア導体10により十分な隙間5,9が形成できるので、内部のメタルプレーン層3や導体層7との絶縁性も確保される。 Therefore, with this multilayer wiring board 20 also connected to the flip chip Otte mounted by pads 13 of the large diameter can be reliably performed, sufficient clearance 5 by the lower end portion and the small diameter inner via conductors 10 of the outermost via conductor 14 since 9 can be formed, insulation between the interior of the metal plane layer 3 and the conductive layer 7 is ensured. また、前記同様に各隙間5,5に挟まれたメタルプレーン層3の中央部分3aも充分な幅寸法を有するので、その電気的特性の劣化も防止できる。 Further, since the same manner with sufficient width also the central portion 3a of the metal plane layer 3 sandwiched between the respective gaps 5,5, can be prevented and deterioration of its electrical properties.

【0017】図2(B)は、最表面ビア導体14の変形形態である最表面ビア導体14aを示し、このビア導体1 [0017] FIG. 2 (B), the top-surface via conductor 14a which is a variant of the outermost surface via conductors 14, the via conductors 1
4aはそのテーパ形状が上端部から下端部に向けてカーブし且つ下端寄りの傾斜が垂直に近づくようにしたものである。 4a is one whose tapered shape inclined in and near the lower end curves toward the lower portion from the upper end is as close vertically. 係る略ラッパ形のテーパ形状の最表面ビア導体14aとすることにより、図示のように、その上端部では大径にできるため、これと同径のフリップチップ接続用のパッド13をメッキで容易に形成できる。 By the outermost surface via conductor 14a of the substantially trumpet-shaped tapered according, as shown, the order can be larger in diameter at the upper end, the pad 13 for flip-chip connection between this and the same diameter as easily by plating It can be formed. しかも、 In addition,
最表面ビア導体14aの下端部は内部ビア導体10と殆んど同径に縮径されているので、メタルプレーン層3, Since the lower end portion of the outermost surface via conductor 14a is reduced in diameter in the diameter almost the inner via conductor 10, the metal plane layer 3,
3aとの間に絶縁に十分な隙間5を確実に得ることができる。 It is possible to reliably obtain sufficient clearance 5 in the insulation between the 3a.

【0018】図3は上記テーパ形状の最表面ビア導体1 [0018] Figure 3 is outermost via conductor 1 of the tapered
4を得るための製造工程に関する。 4 relates to a manufacturing process for obtaining. 図3(a)及び(A)はプレス16による場合を示し、図3(a)に示すように、 3 (a) and (A) shows a case of press 16, as shown in FIG. 3 (a),
追ってセラミック層2となるグリーンシート2′を下型18上に固定する。 Otte fixing the green sheet 2 'of the ceramic layer 2 on the lower mold 18. この下型18には前記ビア導体14 Wherein in this lower die 18 via conductor 14
の上端部と略同径の抜き孔18aが形成されている。 Upper and substantially the same diameter of holes 18a are formed. また、この抜き孔18aの上方には、これと同心で前記ビア導体14の下端部と略同径であり、且つ抜き孔18a Above the holes 18a, a lower end and substantially the same diameter of the via conductor 14 in concentric therewith, and holes 18a
よりも細径のポンチ17が配置されている。 Punch 17 of small diameter is located than. そして、このポンチ17を図中の矢印のように下降してグリーンシート2′内に進入させる。 Then, to enter the green sheet 2 'is lowered to the punch 17 as indicated by an arrow in FIG. すると、グリーンシート2′ Then, the green sheet 2 '
におけるポンチ17の先端(下端)が当初に衝突した位置と、下型18の抜き孔18aの周縁部との間において円錐状にクラックが形成される。 Cracks are formed in a conical shape in between a position where the tip (lower end) collides with the original punch 17, the peripheral portion of the holes 18a of the lower mold 18 in. その結果、図3(A)に示すように、円錐状のテーパ形状を有するビアホールhが形成される。 As a result, as shown in FIG. 3 (A), via holes h having a conical tapered shape is formed.

【0019】図3(b)及び(B)はレーザ照射による場合を示し、図3(b)に示すように、追ってセラミック層2 [0019] FIGS. 3 (b) and 3 (B) shows the case of laser irradiation, as shown in FIG. 3 (b), Otte ceramic layer 2
となるグリーンシート2′の表面に対し、レーザLを直角に照射する。 Become to the surface of the green sheet 2 'is irradiated with the laser L at a right angle. このレーザLには、炭酸ガスレーザ又はYAGレーザが用いられ、凸レンズ19により、シート2′の表面付近に収束するように焦点を合わせる。 The laser L, a carbon dioxide gas laser or YAG laser is used, by the convex lens 19, focuses to converge to the vicinity of the surface of the sheet 2 '. すると、グリーンシート2′の上表面付近でレーザLのエネルギが最大になり、シート2′の下表面に近づくに連れてエネルギが小さくなる。 Then, the green sheet 2 'energy of the laser L in the vicinity of the surface on the becomes the maximum, sheet 2' energy is reduced him to approach the lower surface of. この結果、図3(B)に示すように、グリーンシート2′の上表面から下表面に向けて縮径するテーパ形状のビアホールhが形成される。 As a result, as shown in FIG. 3 (B), a via hole h of the taper shape that decreases in diameter toward the bottom surface from the top surface of the green sheet 2 'is formed.

【0020】因みに、炭酸ガスレーザLを1200mA [0020] By the way, 1200mA a carbon dioxide gas laser L
×30msのパワーと3パルスのパルス数で、厚さ0. × In power and 3 pulses of the pulse of 30 ms, a thickness of 0.
15mmのグリーンシート2′に対し、その上表面付近で略収束するように凸レンズ19の位置を2箇所で調節して、照射した。 15mm to the green sheet 2 ', the position of the convex lens 19 so as to substantially converge in the vicinity of its upper surface is adjusted in two positions, and irradiated. その結果、上端の内径が75μmの場合、下端の内径がその90%のビアホールhと、上端の内径が90μmの場合、下端の内径がその82%のビアホールhとを得ることができた。 As a result, when the inner diameter of the upper end of the 75 [mu] m, and the via-hole h of the 90% the inside diameter of the lower end, when the inner diameter of the upper end of the 90 [mu] m, it was possible to the inner diameter of the lower end obtain its 82% of the via hole h. 尚、ビアホールhの傾斜度は、レーザLのパワー及びパルス数を小さくするに連れて、緩やかになる傾向がある。 The inclination of the via hole h is taken to reduce the power and number of pulses of the laser L, it tends to become gentle. また、レーザLの照射条件を調整することにより、前記図2(B)に示した略ラッパ形のテーパ形状の最表面ビア導体14aを形成することも可能である。 Further, by adjusting the irradiation conditions of the laser L, and it is also possible to form the outermost surface via conductor 14a of the substantially trumpet-shaped tapered shape shown in FIG. 2 (B). これらのテーパ形状のビアホールhを形成したグリーンシート2′を用いると、前記配線基板1と同様の方法で配線基板20を製造することができる。 With these green sheets 2 formed with holes h tapered ', it is possible to manufacture the wiring substrate 20 in the same manner as the wiring board 1.

【0021】本発明は以上に説明した各形態に限定されるものではない。 [0021] The present invention is not limited to each embodiment described above. 例えば、図4(A)は最外側のセラミック層22内に位置するビア導体30を最表面ビア導体3 For example, FIG. 4 (A) via conductor 30 to the outermost surface via conductors 3 located in the ceramic layer 22 of the outermost
0aと、その下側に2つの小径な内部ビア導体30b,3 0a and, two on the lower small-diameter inner via conductors 30b, 3
0cに分けたセラミック多層配線基板32を示す。 Showing a ceramic multilayer wiring substrate 32 divided into 0c. 即ち、3層のセラミック層22,24,26のうち、セラミック層22を上層(最表面のセラミック層)22a,中層22b,下層22cの3つに分割し、中層22bに位置する内部ビア導体30bの径を最表面ビア導体30aと内部ビア導体30cの径の中間としたものである。 That is, of the ceramic layers 22, 24 and 26 three layers, dividing the ceramic layer 22 layer (ceramic layer of the outermost surface) 22a, middle layer 22b, into three lower 22c, the via conductor 30b located intermediate 22b the diameter is obtained by an intermediate diameter of the outermost via conductor 30a and the via conductor 30c. 尚、 still,
内部ビア導体30cの径は、セラミック層24中に位置するビア導体28と同径であり、十分な隙間25を介してメタルプレーン層23と絶縁されている。 Diameter of the via conductor 30c includes a via conductor 28 located in the ceramic layer 24 have the same diameter, is insulated from the metal plane layer 23 via a sufficient clearance 25. また、最表面ビア導体30aの表面上にはフリップチップ接続用のパッド31が形成されている。 The pad 31 for flip chip connection on the surface of the outermost via conductor 30a is formed. 更に、上記ビア導体28 Furthermore, the via conductor 28
は、導体層27と導通している。 It is electrically connected to the conductor layer 27.

【0022】また、図4(B)は最外側のセラミック層2 Further, FIG. 4 (B) ceramic layers 2 of the outermost
2内に位置するビア導体34を最表面ビア導体34a Outermost surface via conductors 34a via conductors 34 located within 2
と、その下側の小径な内部ビア導体34bに分けたセラミック多層配線基板35を示す。 If shows a ceramic multilayer wiring substrate 35 is divided into a small-diameter inner via conductors 34b of the lower side. 即ち、3層のセラミック層22,24,26のうち、セラミック層22を上層 That is, of the ceramic layers 22, 24 and 26 three layers, the ceramic layer 22 upper layer
(最表面層)22aと下層22bに分割する。 Divided into (outermost surface layer) 22a and the lower layer 22b. 上層22a The upper layer 22a
となるグリーンシートには前記プレス16又はレーザL The press 16 or the laser L is in the green sheet to be the
によりテーパ形状のビアホールを予め形成した後、前記同様の方法でメタライズインクを充填し、グリーンシートと共に焼成すると、上記ビア導体34aになる。 After pre-forming a via hole in the tapered shape by the filling the metallizing ink in a similar way, when firing with the green sheet becomes the via conductors 34a. 尚、 still,
内部ビア導体34bの径は、セラミック層24中に位置するビア導体28と同径で、十分な隙間25を介してメタルプレーン層23と絶縁されている。 Diameter of the via conductor 34b is the same diameter as the via conductor 28 located in the ceramic layer 24 and is insulated from the metal plane layer 23 via a sufficient clearance 25. また、最表面ビア導体34a上にはパッド31が形成され、上記ビア導体28は導体層27と導通する。 The pad 31 is formed on the outermost surface via conductors 34a, the via conductor 28 is electrically connected to the conductive layer 27.

【0023】更に、図4(C)は最表面のセラミック層2 Furthermore, FIG. 4 (C) is the outermost ceramic layer 2
2内に位置する最表面ビア導体36を断面略皿ネジ形状にしたセラミック多層配線基板38を示す。 The outermost surface via conductors 36 located within 2 shows a ceramic multilayer wiring substrate 38 and the cross section countersunk screw shape. 即ち、セラミック層22となるグリーンシートに対し、前記プレス16と同様のものを用いて予め傾斜が緩いテーパ形状のビアホールhを穿設し、次に、図示で下側の小径の開口部に別のやや太いポンチを進入させ、上部及び中部が傾斜し且つ下部が垂直なテーパ形状のビアホール37を形成する。 That is, another to green sheets for the ceramic layers 22, drilled via holes h in advance inclined loose tapered shape with the same as the press 16, then the small diameter of the opening of the lower side shown of it is advanced slightly thicker punch, upper and middle is inclined and bottom to form a via hole 37 of the vertical tapered. このビアホール37を有するグリーンシートを用いると、前記同様の方法で配線基板38を製造することができる。 With the green sheets having the via hole 37, it is possible to manufacture the wiring substrate 38 in the same manner. 即ち、ビアホール37内にはこれに倣った形状の最表面ビア導体36が形成され、その上端部にはパッド31が形成されると共に、その下端部は同径のビア導体28と導通するため、十分な隙間25を介してメタルプレーン層23と絶縁される。 That is, the via hole 37 is the uppermost surface via conductors 36 of a shape conforming to this form, the pad 31 is formed at the upper end, since its lower end is electrically connected to the via conductor 28 of the same diameter, It is insulated from the metal plane layer 23 via a sufficient clearance 25. 尚、上記ビア導体2 Incidentally, the via conductors 2
8は導体層27と導通する。 8 is electrically connected to the conductive layer 27.

【0024】また、配線基板を形成するセラミックとして、アルミナを主成分とする形態を示したが、これに限定されず、例えば窒化アルミニウム(AlN)やガラスセラミック、ムライト等、配線基板を構成できるものであれば、特に限定されない。 Further, as the ceramic forming the wiring substrate, although the form of alumina as a main component, without being limited thereto, such as those that can be configured of aluminum nitride (AlN), glass ceramic, mullite, the wiring substrate if, not particularly limited. 但し、ビア導体中のセラミック物質には、配線基板と同じ材質のものを用いるのが望ましい。 However, the ceramic material in the via conductor, it is desirable to use the same material as the wiring board. 例えば、配線基板がアルミナを主成分とする場合には、ビア導体中のセラミック物質もアルミナが好適である。 For example, when the wiring substrate is composed mainly of alumina, the ceramic material in the via conductor is also alumina are preferred. また、ビア径についても前記の各形態に限定されないことは言うまでもない。 Also, of course, not limited to the form of the also via diameter.

【0025】更に、導体層も、使用するセラミックの材質に適合したものを使用すれば良いし、例示したMoやW等の他、Mo−Mn,Ag,Cu,Ag-Pd,Ag−Pt Furthermore, the conductive layer also may be used to be compatible to the ceramic material to be used, other such illustrated Mo and W, Mo-Mn, Ag, Cu, Ag-Pd, Ag-Pt
その他の材質を用いても良い。 It may be used other materials. 尚、本発明の多層配線基板に搭載されるフリップチップは、一つの半導体素子の他、複数個の半導体素子を固着して用いるマルチチップモジュールも適用することができるし、また、トランジスタ、FET等の半導体素子やコンデンサ、抵抗、インダクタ、SAWフィルタ、その他の電子部品を表面に搭載する場合も含まれる。 Incidentally, flip chip mounted on the multilayer wiring board of the present invention, other one of the semiconductor elements, even a multi-chip module used in fixing a plurality of semiconductor elements to be applied, also, transistor, FET, etc. the semiconductor element and a capacitor, resistor, inductor, but also the case of mounting SAW filters, other electronic components on the surface.

【0026】 [0026]

【発明の効果】以上において説明した本発明のフリップチップ用セラミック多層配線基板によれば、搭載されるフリップチップとパッドとの接続が確実になると共に、 According to the ceramic multi-layer wiring board for flip-chip of the present invention described in the above, according to the present invention, the connection between the flip chip and the pads mounted is ensured,
該パッドと導通するビア導体が基板の内部で導体層と十分な隙間を介して絶縁される。 Via conductors that conduct and the pad is insulated through sufficient clearance and the conductor layer inside the substrate. しかも、ビア導体同士の間隔が狭くても各ビア導体の周囲の隙間同士の間にも十分な導体層を形成できるので、その電気的特性の劣化を防止できる。 Moreover, since even narrow distance between the via conductor can form a sufficient conductive layer also between the gap between the periphery of each via conductor, it is possible to prevent deterioration of the electrical characteristics. また、請求項4のフリップチップ用セラミック多層配線基板によれば、上記に加え、各ビア導体と各セラミック層との間に間隙を生じにくいので、基板全体の気密性を高めることもできる。 Further, according to the ceramic multi-layer wiring substrate for the claim 4 flip chip, in addition to the above, since hardly occurs a gap between the via conductor and the ceramic layer, it is possible to increase the airtightness of the whole substrate.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】(A)は本発明の多層配線基板の要部を示す部分断面図、(B)は(A)中のB−B断面図。 1 (A) is a partial sectional view showing a main part of a multilayer wiring board of the present invention, (B) is sectional view taken along line B-B in (A).

【図2】(A)は異なる形態の多層配線基板の要部を示す部分断面図、(B)は最表面ビア導体の変形形態を示す部分断面図。 Figure 2 (A) is different partial sectional view showing a main part of a multilayer wiring substrate in the form, (B) is a partial sectional view showing a modification of the outermost surface via conductors.

【図3】(a)と(A)及び(b)と(B)は共に図2(A)の多層配線基板を得るための製造工程を示す概略図。 3 (a) and a schematic diagram showing a manufacturing process for obtaining a multilayer wiring board (A) and (b) and (B) are both FIG 2 (A).

【図4】(A)乃至(C)は更に異なる形態の多層配線基板の各要部を示す部分断面図。 [4] (A) to (C) partial sectional views showing the main portion of the multilayer wiring board further different forms.

【図5】(A)は一般的なフリップチップ用セラミック多層配線基板の断面図、(B)及び(C)は従来の技術を示す [5] (A) is a cross-sectional view of a typical flip chip ceramic multilayer wiring substrate, shows the prior art (B) and (C)
(A)中の一点鎖線部分B,Cを示す拡大断面図、(b)は (A) enlarged sectional view showing one-dot chain line portion B, and C in, (b) is
(B)中のb−b断面図、(c)は(C)中のc−c断面図。 (B) b-b cross section in, (c) is c-c sectional view in (C).

【符号の説明】 DESCRIPTION OF SYMBOLS

1,20,32,35,38………………………セラミック多層配線基板 2,4,6,22,24,26……………………セラミック層 10,28,30,34…………………………ビア導体 10,11,30b,30c,34b……………ビア導体 1,20,32,35,38 ........................... ceramic multilayer wiring substrate 2,4,6,22,24,26 ........................ ceramic layer 10,28,30,34 .............................. via conductor 10,11,30b, 30c, 34b ............... via conductors
(内部ビア導体) 12,14,14a,30a,34a,36……ビア導体 (The via conductor) 12,14,14a, 30a, 34a, 36 ...... via conductors
(最表面ビア導体) 13,31………………………………………パッド (Outermost surface via conductor) 13, 31 ............................................. pad

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【手続補正書】 [Procedure amendment]

【提出日】平成11年9月1日(1999.9.1) [Filing date] 1999 September 1 (1999.9.1)

【手続補正1】 [Amendment 1]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】請求項1 [Correction target item name] according to claim 1,

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【手続補正2】 [Amendment 2]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】請求項2 [Correction target item name] claim 2

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【手続補正3】 [Amendment 3]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】請求項3 [Correction target item name] claim 3

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【手続補正4】 [Amendment 4]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】0006 [Correction target item name] 0006

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【0006】 [0006]

【課題を解決するための手段】本発明は、上記課題を解決するため、フリップチップ接続用のパッドに導通するビア導体の径を、その上端部と内部とで変化させることに着想して成されたものである。 The present invention SUMMARY OF] In order to solve the above problems, the diameter of the via conductor electrically connected to the pad for flip chip connection, and inspired be varied from the interior to the upper end thereof formed it is those that have been. 即ち、本発明のフリップチップ用セラミック多層配線基板は、基板の表面にフリップチップと接続するパッドを有するフリップチップ用セラミック多層配線基板において、基板の表面に露出するビア導体の上端部の径が該ビア導体のうち導体層 That is, the ceramic multi-layer wiring board for flip-chip of the present invention, the ceramic multi-layer wiring board for flip chip having a pad to be connected to the flip-chip on the surface of the substrate, the diameter of the upper end of the via conductor exposed on the surface of the substrate, conductor layer of the via conductors
を隙間を介して貫通する内部の径よりも大きくされ、該ビア導体の上端部にメッキ層からなる上記パッドを形成した、ことを特徴とする。 The is larger than the diameter of the inner penetrating through the gap, the formation of the pad of the plating layer on the upper portion of the via conductors, characterized in that. これによれば、フリップチップとの接続と共に内部の導体層との絶縁の双方を確実に行えるセラミック多層配線基板とすることができる。 According to this, it can be a ceramic multilayer wiring substrate reliably perform both the insulation of the inner conductor layers together with the connection of the flip chip.

【手続補正5】 [Amendment 5]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】0007 [Correction target item name] 0007

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【0007】また、前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成され且つ前記導体層を隙間を介して貫通する内部ビア導体とからなり、上記最表面ビア導体はその上端部から内部ビア導体に向けて縮径するテーパ形状を有する、フリップチップ用セラミック多層配線基板も含まれる。 Further, the via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, a and is formed inside the ceramic layer in said conductor layer consists of a inner via conductors penetrating through the gap, the outermost surface via conductor has a tapered shape whose diameter decreases toward the inside via conductor from its upper end, also includes a ceramic multilayer wiring board for flip-chip. これによれば、パッドに接する最表面ドア導体にテーパを付すことで、フリップチップとの接続及び内部の導体層との絶縁の双方を確実に得ることができる。 According to this, by subjecting the tapered top surface door conductor in contact with the pad, it is possible to obtain both the insulation between the connection and the inner conductor layers of the flip chip surely. 尚、上記テーパ形状を得るため、後述するように事前にセラミック層に形成するビアホールもプレス又はレーザ照射によりテーパ形状に穿設される。 In order to obtain the tapered shape, even a via hole formed in the ceramic layer in advance as will be described later is formed in a tapered shape by a press or laser irradiation.

【手続補正6】 [Amendment 6]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】0008 [Correction target item name] 0008

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【0008】更に、前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成され且つ前記導体層を隙間を介して貫通する内部ビア導体とからなり、上記最表面ビア導体の径が上記内部ビア導体の径よりも大きい、フリップチップ用セラミック多層配線基板も含まれる。 Furthermore, the via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, a and the conductor layer is formed inside the ceramic layer consists of a inner via conductors penetrating through the gap, the diameter of the outermost via conductor is larger than the diameter of the inner via conductors also include ceramic multilayer wiring board for flip-chip. これによれば、セラミック層毎に径の異なるビア導体を形成するので、フリップチップとの接続及び内部の導体層との絶縁の双方を確実に得ることができる。 According to this, since to form the via conductors having different diameters for each ceramic layer, it is possible to obtain both the insulation between the connection and the inner conductor layers of the flip chip surely. この場合、ビア導体の径を2段階以上異ならしめることも可能である。 In this case, it is also possible to made different diameters of the via conductors two or more stages.

【手続補正7】 [Amendment 7]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】符号の説明 [Correction target item name description of the sign

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【符号の説明】 1,20,32,35,38………………………セラミック多層配線基板 2,4,6,22,24,26……………………セラミック層3,23…………………………………………メタルプレ [EXPLANATION OF SYMBOLS] 1,20,32,35,38 ........................... ceramic multilayer wiring substrate 2,4,6,22,24,26 ........................ ceramic layer 3, 23 ................................................ Metarupure
ーン層(導体層) 5,9,25………………………………………隙間 7…………………………………………………導体層 10,28,30,34…………………………ビア導体 10,11,30b,30c,34b……………ビア導体 Chromatography emission layer (conductor layer) 5,9,25 ............................................. gap 7 ......................................................... conductor layer 10,28,30,34 .............................. via conductor 10,11,30b, 30c, 34b ............... via conductors
(内部ビア導体) 12,14,14a,30a,34a,36……ビア導体 (The via conductor) 12,14,14a, 30a, 34a, 36 ...... via conductors
(最表面ビア導体) 13,31………………………………………パッド (Outermost surface via conductor) 13, 31 ............................................. pad

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】基板の表面にフリップチップと接続するパッドを有するフリップチップ用セラミック多層配線基板において、 基板の表面に露出するビア導体の上端部の径が該ビア導体の内部の径よりも大きくされ、該ビア導体の上端部にメッキ層からなる上記パッドを形成した、 ことを特徴とするフリップチップ用セラミック多層配線基板。 1. A ceramic multilayer wiring board for flip chip having a pad to be connected to the flip-chip on the surface of the substrate, greater than the diameter of the internal diameter of the via conductor of the upper end of the via conductor exposed on the surface of the substrate is, the formation of the pad of the plating layer to the upper end of the via conductor, the ceramic multi-layer wiring board for flip chip, characterized in that.
  2. 【請求項2】前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成された内部ビア導体とからなり、 上記最表面ビア導体はその上端部から内部ビア導体に向けて縮径するテーパ形状を有する、ことを特徴とする請求項1に記載のフリップチップ用セラミック多層配線基板。 Wherein said via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, and the via conductor formed inside the ceramic layer consists, ceramic multi-layer wiring board for flip chip of claim 1 wherein said outermost surface via conductor having a tapered shape whose diameter decreases toward the inside via conductor from its upper end, it is characterized.
  3. 【請求項3】前記ビア導体は、前記基板の表面を成す最表面のセラミック層内に形成され且つ前記上端部を含む最表面ビア導体と、内部のセラミック層内に形成された内部ビア導体とからなり、 上記最表面ビア導体の径が上記内部ビア導体の径よりも大きい、ことを特徴とする請求項1に記載のフリップチップ用セラミック多層配線基板。 Wherein the via conductor, and the outermost surface via conductor and including the said upper portion is formed on the ceramic layer of the outermost surface which forms the surface of the substrate, and the via conductor formed inside the ceramic layer consists, diameter of the outermost via conductor is larger than the diameter of the inner via conductors, ceramic multilayer wiring board for flip chip according to claim 1, characterized in that.
  4. 【請求項4】前記最表面ビア導体及び内部ビア導体とは、金属物質とセラミック物質との混合物質からなり、 Wherein said the outermost via conductors and the via conductors, made of a mixture material of metal material and a ceramic material,
    且つ上記最表面ビア導体中のセラミック物質の含有量が上記内部ビア導体中のそれよりも多い、ことを特徴とする請求項2又は3に記載のフリップチップ用セラミック多層配線基板。 And the content of the ceramic material in the outermost surface via conductor is larger than that in the inner via conductors, ceramic multilayer wiring board for flip chip according to claim 2 or 3, characterized in that.
JP18000598A 1998-06-26 1998-06-26 Ceramic multilayer wiring substrate for flip chip Expired - Fee Related JP3098992B2 (en)

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