JP6062884B2 - Component-embedded substrate, manufacturing method thereof, and mounting body - Google Patents

Component-embedded substrate, manufacturing method thereof, and mounting body Download PDF

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JP6062884B2
JP6062884B2 JP2014108875A JP2014108875A JP6062884B2 JP 6062884 B2 JP6062884 B2 JP 6062884B2 JP 2014108875 A JP2014108875 A JP 2014108875A JP 2014108875 A JP2014108875 A JP 2014108875A JP 6062884 B2 JP6062884 B2 JP 6062884B2
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substrate
layer
wiring
component
insulating layer
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JP2015225912A (en
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浩次 宗像
浩次 宗像
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Fujikura Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

この発明は、電子部品を内蔵した部品内蔵基板及びその製造方法並びに実装体に関する。   The present invention relates to a component-embedded substrate that incorporates an electronic component, a manufacturing method thereof, and a mounting body.

近年の小型精密電子機器を中心とした更なる小型化や高性能化の要求に対応するため、例えば部品内蔵基板技術によって、半導体デバイス等の電子部品の小型化を進めつつ高集積化に対応する必要性が増している。部品内蔵基板技術を用いたものとして、部品内蔵基板(例えば、下記特許文献1参照。)が知られている。   In order to respond to the demand for further miniaturization and higher performance mainly in small precision electronic equipment in recent years, for example, by using the component-embedded substrate technology, the electronic components such as semiconductor devices are being miniaturized and the higher integration is supported. The need is increasing. 2. Description of the Related Art A component built-in substrate (for example, see Patent Document 1 below) is known as a component using the component built-in substrate technology.

この部品内蔵基板は、複数の単位基板を積層して積層方向に複数の電子部品を内蔵してなるもので、電子部品が開口部に収容された両面基板が積層方向に複数積層され、中間基板が両面基板を含む他の単位基板の間に積層されて構成されている。これにより、電子部品を収容する箇所の厚さを薄くして、部品内蔵基板全体の薄型化を図っている。   This component-embedded substrate is formed by laminating a plurality of unit substrates and incorporating a plurality of electronic components in the laminating direction, and a plurality of double-sided substrates in which electronic components are accommodated in the opening are laminated in the laminating direction. Is laminated between other unit substrates including a double-sided substrate. Thereby, the thickness of the part which accommodates an electronic component is made thin, and thickness reduction of the whole component built-in board | substrate is achieved.

特許第5427305号公報Japanese Patent No. 5427305

一般的に用いられるシリコン半導体からなる電子部品では、例えばTj温度(半導体素子温度)が175℃以上になると、半導体素子自体が熱により破壊されてしまう可能性がある。従って、電子部品の運用上のTj温度は、例えば80℃〜100℃の範囲内に収まるように熱設計が行われている。   In a commonly used electronic component made of a silicon semiconductor, for example, when the Tj temperature (semiconductor element temperature) is 175 ° C. or higher, the semiconductor element itself may be destroyed by heat. Therefore, the thermal design is performed so that the Tj temperature in the operation of the electronic component falls within a range of 80 ° C. to 100 ° C., for example.

しかしながら、上記特許文献1に開示された従来技術の部品内蔵基板においては、内蔵された電子部品の周囲が、熱伝導係数が約0.2W/mk程度のエポキシ樹脂やポリイミド樹脂などの絶縁樹脂材料により覆われた構造を採用している。また、複数の電子部品間にも、絶縁樹脂材料からなる接着層や中間基板などが介在するのみである。   However, in the conventional component-embedded substrate disclosed in Patent Document 1, an insulating resin material such as an epoxy resin or a polyimide resin having a thermal conductivity coefficient of about 0.2 W / mk is provided around the built-in electronic component. The structure covered with is adopted. Further, only an adhesive layer made of an insulating resin material or an intermediate substrate is interposed between the plurality of electronic components.

この絶縁樹脂材料は、熱伝導係数が約370W/mk程度の銅などの金属材料と比べると、約1/1000倍程度の熱伝導係数を示すものである。このため、電子部品の熱が拡散され難く、放熱特性を考慮した構造設計が必要となるという問題がある。   This insulating resin material exhibits a thermal conductivity coefficient of about 1/1000 times that of a metal material such as copper having a thermal conductivity coefficient of about 370 W / mk. For this reason, there is a problem that the heat of the electronic component is not easily diffused, and a structural design in consideration of heat dissipation characteristics is required.

この発明は、上述した問題点に鑑みてなされたもので、部品内蔵基板全体の薄型化を図りつつ内蔵された電子部品の熱を層内において拡散させて放熱することができる部品内蔵基板及びその製造方法並びに実装体を提供することを目的とする。   The present invention has been made in view of the above-described problems, and has a component-embedded board that can dissipate heat by diffusing the heat of the built-in electronic component in the layer while reducing the thickness of the entire component-embedded board. An object is to provide a manufacturing method and a mounting body.

本発明に係る部品内蔵基板は、複数の単位基板を積層し、積層方向に複数の電子部品を内蔵してなる多層構造の部品内蔵基板であって、前記複数の単位基板は、第1絶縁層を有し、第1電子部品が収容された開口部を備えた第1基板と、前記第1基板に隣接し、第2絶縁層の前記第1基板側の面に形成された第1配線層及び前記第2絶縁層の少なくとも前記第1基板側に設けられた第1接着層備えた中間基板とを含み、前記中間基板の前記第1配線層と前記第1電子部品とが前記第1接着層を介して対向するように配置され積層されていることを特徴とする。   The component-embedded substrate according to the present invention is a component-embedded substrate having a multilayer structure in which a plurality of unit substrates are stacked and a plurality of electronic components are embedded in the stacking direction, and the plurality of unit substrates are first insulating layers. A first substrate having an opening in which the first electronic component is accommodated, and a first wiring layer formed adjacent to the first substrate and formed on a surface of the second insulating layer on the first substrate side And an intermediate substrate provided with a first adhesive layer provided at least on the first substrate side of the second insulating layer, wherein the first wiring layer and the first electronic component of the intermediate substrate are bonded to the first adhesive layer. It is characterized by being arranged and laminated so as to face each other through layers.

本発明に係る部品内蔵基板によれば、第1基板に第1接着層を介して隣接する中間基板の第1配線層と第1基板の開口部に収容された第1電子部品とが、第1接着層を介して対向するように配置され積層されている。このため、第1電子部品の熱は第1接着層を通って第1配線層に伝導されるので、第1配線層を通って拡がる状態となり、層内で拡散して放熱することができる。また、第1電子部品は第1基板の開口部に収容されるので、各単位基板間に第1電子部品を収容するための絶縁体スペーサ等を配置する必要がなく、部品内蔵基板全体の薄型化を図ることができる。   According to the component-embedded substrate according to the present invention, the first wiring layer of the intermediate substrate adjacent to the first substrate via the first adhesive layer and the first electronic component housed in the opening of the first substrate are It is arranged and laminated so as to face each other through one adhesive layer. For this reason, since the heat of the first electronic component is conducted to the first wiring layer through the first adhesive layer, the heat spreads through the first wiring layer and can be diffused and dissipated in the layer. Further, since the first electronic component is accommodated in the opening of the first substrate, it is not necessary to arrange an insulator spacer for accommodating the first electronic component between the unit substrates, and the entire component-embedded substrate is thin. Can be achieved.

本発明の一実施形態においては、前記複数の単位基板は、前記中間基板の前記第1基板とは反対側に配置され、第3絶縁層を有し、前記第1電子部品と積層方向に重なる位置に第2電子部品が収容された開口部を備えた第2基板を含み、前記中間基板は、前記第2絶縁層の前記第2基板側の面に形成された第2配線層及び前記第2絶縁層の前記第2基板側に設けられた前記第1接着層を有する。   In one embodiment of the present invention, the plurality of unit substrates are disposed on the opposite side of the intermediate substrate from the first substrate, have a third insulating layer, and overlap the first electronic component in the stacking direction. A second substrate having an opening accommodating a second electronic component at a position, wherein the intermediate substrate includes a second wiring layer formed on a surface of the second insulating layer on the second substrate side, and the second substrate The first adhesive layer is provided on the second substrate side of the two insulating layers.

本発明の他の実施形態においては、前記中間基板は、前記第2配線層と前記第2電子部品とが前記第1接着層を介して対向するように配置され積層されている。   In another embodiment of the present invention, the intermediate substrate is disposed and laminated such that the second wiring layer and the second electronic component face each other with the first adhesive layer interposed therebetween.

本発明の更に他の実施形態においては、前記複数の単位基板は、前記第2基板と前記中間基板との間に配置され、第4絶縁層の一方の面に形成された第3配線層及び前記第4絶縁層を貫通し前記第3配線層と前記第2電子部品とを接続するビアを有し、前記第4絶縁層の他方の面側に設けられた第2接着層を備えた第3基板を含み、前記中間基板は、前記第2配線層と前記第3配線層とが前記第1接着層を介して対向するように配置され積層されている。   In still another embodiment of the present invention, the plurality of unit substrates are disposed between the second substrate and the intermediate substrate, and a third wiring layer formed on one surface of the fourth insulating layer and A second adhesive layer provided on the other surface side of the fourth insulating layer, having a via that penetrates the fourth insulating layer and connects the third wiring layer and the second electronic component; The intermediate substrate is arranged and laminated such that the second wiring layer and the third wiring layer are opposed to each other with the first adhesive layer interposed therebetween.

本発明の更に他の実施形態においては、前記中間基板の前記第1及び第2配線層の少なくとも一方は、前記第3基板の前記第3配線層と積層方向に重ならない領域に形成されている。   In still another embodiment of the present invention, at least one of the first and second wiring layers of the intermediate substrate is formed in a region that does not overlap with the third wiring layer of the third substrate in the stacking direction. .

本発明に係る部品内蔵基板の製造方法は、複数の単位基板を積層し、積層方向に複数の電子部品を内蔵してなる多層構造の部品内蔵基板の製造方法であって、前記単位基板として第1絶縁層に第1電子部品が収容される開口部を形成して第1基板を作製する工程と、前記単位基板として第2絶縁層の前記第1基板側に配置される面に第1配線層を形成すると共に、前記第2絶縁層の少なくとも前記第1基板側に第1接着層を設けて中間基板を作製する工程と、前記第1基板の前記開口部に前記第1電子部品を収容し、前記第1基板に対して前記中間基板を前記第1配線層と前記第1電子部品とが前記第1接着層を介して対向するように隣接配置し、前記単位基板を積層方向に複数積層する工程とを備えたことを特徴とする。   A method for manufacturing a component-embedded substrate according to the present invention is a method for manufacturing a component-embedded substrate having a multilayer structure in which a plurality of unit substrates are stacked and a plurality of electronic components are embedded in the stacking direction. Forming a first substrate by forming an opening for accommodating the first electronic component in one insulating layer, and forming a first wiring on a surface of the second insulating layer disposed on the first substrate side as the unit substrate; Forming an intermediate substrate by forming a layer and forming a first adhesive layer on at least the first substrate side of the second insulating layer; and housing the first electronic component in the opening of the first substrate The intermediate substrate is arranged adjacent to the first substrate so that the first wiring layer and the first electronic component face each other with the first adhesive layer interposed therebetween, and a plurality of unit substrates are arranged in the stacking direction. And a step of laminating.

本発明に係る部品内蔵基板の製造方法によれば、単位基板として作製された第1基板の開口部に第1電子部品を収容し、この第1基板に対して第1配線層が形成された中間基板を第1接着層を介して隣接配置し、第1配線層と第1電子部品とが第1接着層を介して対向するように単位基板を積層方向に複数積層することで部品内蔵基板を製造するので、上記部品内蔵基板の作用効果と同様の作用効果を奏する部品内蔵基板を容易に製造することができる。   According to the component-embedded substrate manufacturing method of the present invention, the first electronic component is accommodated in the opening of the first substrate manufactured as the unit substrate, and the first wiring layer is formed on the first substrate. A component-embedded substrate in which a plurality of unit substrates are stacked in the stacking direction so that the intermediate substrate is disposed adjacently via the first adhesive layer, and the first wiring layer and the first electronic component face each other via the first adhesive layer Therefore, it is possible to easily manufacture a component-embedded substrate that exhibits the same effects as those of the component-embedded substrate.

本発明の一実施形態においては、前記単位基板として第3絶縁層に第2電子部品が前記第1電子部品と積層方向に重なる位置に収容される開口部を形成して第2基板を作製する工程を備え、前記中間基板を作製する工程では、前記第2絶縁層の前記第2基板側に配置される面に第2配線層を形成すると共に、前記第2絶縁層の前記第2基板側に前記第1接着層を設け、前記積層する工程では、前記第2基板を前記中間基板に対して前記第1基板とは反対側に配置して積層する。   In one embodiment of the present invention, the second substrate is manufactured by forming an opening in the third insulating layer as the unit substrate in which the second electronic component is accommodated at a position overlapping the first electronic component in the stacking direction. And the step of producing the intermediate substrate includes forming a second wiring layer on a surface of the second insulating layer disposed on the second substrate side, and forming the second insulating layer on the second substrate side. In the step of laminating and laminating the first adhesive layer, the second substrate is disposed on the opposite side of the intermediate substrate from the intermediate substrate and laminated.

本発明の他の実施形態においては、前記積層する工程では、前記第2基板を前記中間基板を介して前記第2電子部品と前記第2配線層とが前記第1接着層を介して対向するように配置して積層する。   In another embodiment of the present invention, in the step of laminating, the second electronic component and the second wiring layer are opposed to each other with the first adhesive layer interposed between the second substrate and the intermediate substrate. Are arranged and laminated.

本発明の更に他の実施形態においては、前記単位基板として第4絶縁層の一方の面に第3配線層を形成すると共に、前記第4絶縁層を貫通し前記第3配線層と前記第2電子部品とに接続されるビアを形成し、前記第4絶縁層の他方の面側に第2接着層を設けて第3基板を作製する工程を備え、前記積層する工程では、前記第3基板を前記第2基板と前記中間基板との間に、前記第2配線層と前記第3配線層とが前記第1接着層を介して対向するように配置して積層する。   In still another embodiment of the present invention, a third wiring layer is formed on one surface of the fourth insulating layer as the unit substrate, and the third wiring layer and the second wiring penetrate through the fourth insulating layer. Forming a via connected to an electronic component, and providing a second adhesive layer on the other surface side of the fourth insulating layer to produce a third substrate, and in the step of laminating, the third substrate Between the second substrate and the intermediate substrate, the second wiring layer and the third wiring layer are disposed so as to face each other with the first adhesive layer interposed therebetween.

本発明の更に他の実施形態においては、前記中間基板を作製する工程では、前記第1及び第2配線層の少なくとも一方を、前記第3基板の前記第3配線層と積層方向に重ならない領域に形成する。   In still another embodiment of the present invention, in the step of manufacturing the intermediate substrate, at least one of the first and second wiring layers does not overlap with the third wiring layer of the third substrate in the stacking direction. To form.

本発明に係る実装体は、上記部品内蔵基板の表面及び裏面の少なくとも一つの実装面上に他の電子部品を表面実装したものである。   The mounting body according to the present invention is such that another electronic component is surface-mounted on at least one mounting surface of the front and back surfaces of the component-embedded substrate.

本発明によれば、部品内蔵基板全体の薄型化を図りつつ内蔵された電子部品の熱を層内において拡散させて放熱することができる。   According to the present invention, it is possible to dissipate heat by diffusing heat of a built-in electronic component in the layer while reducing the thickness of the entire component-embedded substrate.

本発明の第1の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 1st Embodiment of this invention. 同部品内蔵基板の中間基板を示す上面図である。It is a top view which shows the intermediate board of the same component built-in board. 同部品内蔵基板の製造方法による製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process by the manufacturing method of the same component built-in substrate. 同部品内蔵基板の製造方法による製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process by the manufacturing method of the same component built-in substrate. 同部品内蔵基板の製造方法による製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process by the manufacturing method of the same component built-in substrate. 同部品内蔵基板の製造方法による製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process by the manufacturing method of the same component built-in substrate. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. 本発明の第1の実施形態に係る部品内蔵基板を備えた実装体を示す断面図である。It is sectional drawing which shows the mounting body provided with the component built-in board | substrate which concerns on the 1st Embodiment of this invention. 本発明の第2の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 2nd Embodiment of this invention. 同部品内蔵基板の中間基板を示す上面図である。It is a top view which shows the intermediate board of the same component built-in board. 本発明の第3の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 3rd Embodiment of this invention. 同部品内蔵基板の中間基板を示す上面図である。It is a top view which shows the intermediate board of the same component built-in board. 本発明の第4の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 4th Embodiment of this invention. 本発明の第5の実施形態に係る部品内蔵基板を示す断面図である。It is sectional drawing which shows the component built-in board | substrate which concerns on the 5th Embodiment of this invention.

以下、添付の図面を参照して、この発明の実施の形態に係る部品内蔵基板及びその製造方法並びに実装体を詳細に説明する。   Hereinafter, a component-embedded substrate, a manufacturing method thereof, and a mounting body according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明の第1の実施形態に係る部品内蔵基板を示す断面図である。図2は、部品内蔵基板の中間基板を示す上面図である。なお、図1は図2におけるA−A’線断面を表した図である。図1及び図2に示すように、第1の実施形態に係る部品内蔵基板1は、複数の単位基板を積層して積層方向に複数の電子部品80,90を内蔵してなるものである。   FIG. 1 is a cross-sectional view showing a component-embedded substrate according to the first embodiment of the present invention. FIG. 2 is a top view showing the intermediate board of the component built-in board. FIG. 1 is a view showing a cross section taken along line A-A ′ in FIG. 2. As shown in FIGS. 1 and 2, the component-embedded substrate 1 according to the first embodiment is formed by stacking a plurality of unit substrates and incorporating a plurality of electronic components 80 and 90 in the stacking direction.

部品内蔵基板1は、単位基板としての複数の両面基板10と、中間基板20と、複数の片面基板30とを、例えば熱圧着により一括積層した構造を備えている。この部品内蔵基板1において、中間基板20よりも積層方向の下方側に配置された両面基板10は第1基板として機能する。   The component-embedded substrate 1 has a structure in which a plurality of double-sided substrates 10 as a unit substrate, an intermediate substrate 20, and a plurality of single-sided substrates 30 are collectively laminated by, for example, thermocompression bonding. In the component-embedded substrate 1, the double-sided substrate 10 disposed below the intermediate substrate 20 in the stacking direction functions as a first substrate.

また、中間基板20よりも積層方向の上方側に配置された両面基板10は第2基板として、またこの第2基板である両面基板10と中間基板20との間に配置された片面基板30は第3基板としてそれぞれ機能する。各電子部品80,90は、各両面基板10に形成された開口部19内に、例えば背面81a,91a側を積層方向の上方側に向けると共に電極形成面81b,91b側を積層方向の下方側に向けた状態でそれぞれ収容されている。   Further, the double-sided substrate 10 disposed above the intermediate substrate 20 in the stacking direction is used as a second substrate, and the single-sided substrate 30 disposed between the double-sided substrate 10 and the intermediate substrate 20 as the second substrate is Each functions as a third substrate. Each electronic component 80, 90 has, for example, a back surface 81a, 91a side facing upward in the stacking direction and an electrode forming surface 81b, 91b side facing down in the stacking direction in the opening 19 formed in each double-sided substrate 10. Each of them is housed in the state of facing.

なお、第1基板として機能する両面基板10の開口部19内に収容された電子部品80は第1電子部品として機能し、第2基板として機能する両面基板10の開口部19内に収容された電子部品90は第2電子部品として機能する。部品内蔵基板1において内蔵される電子部品80,90は、上記のように2つに限定されるものではなく、更に多く内蔵されてもよい。   The electronic component 80 accommodated in the opening 19 of the double-sided substrate 10 that functions as the first substrate functions as the first electronic component and is accommodated in the opening 19 of the double-sided substrate 10 that functions as the second substrate. The electronic component 90 functions as a second electronic component. The electronic components 80 and 90 incorporated in the component-embedded substrate 1 are not limited to two as described above, and more electronic components 80 and 90 may be incorporated.

各両面基板10は、それぞれ例えばフィルム状の第1及び第3絶縁層としての樹脂基材11と、この樹脂基材11の両面側にそれぞれ形成された配線12とを備える。また、各両面基板10は、例えば一方の配線12及び樹脂基材11を貫通するビアホール2内にめっき形成されて各配線12を接続するビア13を備える。   Each double-sided substrate 10 includes, for example, a resin base 11 as a film-like first and third insulating layers, and wirings 12 formed on both sides of the resin base 11, respectively. In addition, each double-sided substrate 10 includes vias 13 that are formed by plating in via holes 2 that penetrate one wiring 12 and resin base material 11 and connect the respective wirings 12.

また、各両面基板10は、それぞれ所定箇所において樹脂基材11及び配線12を除去した開口部19を備える。開口部19にはそれぞれ電子部品80,90が収容される。なお、第1及び第2基板を両面基板10で構成しない場合は、樹脂基材11と開口部19により第1及び第2基板を構成すれば足りる。   Moreover, each double-sided board 10 is provided with the opening part 19 which removed the resin base material 11 and the wiring 12 in the predetermined location, respectively. Electronic parts 80 and 90 are accommodated in the openings 19, respectively. In the case where the first and second substrates are not configured by the double-sided substrate 10, it is sufficient to configure the first and second substrates by the resin base material 11 and the opening 19.

中間基板20は、例えば少なくとも一つの両面基板10(図1においては積層方向の下方側の両面基板10)に隣接し、フィルム状の第2絶縁層としての樹脂基材21と、この樹脂基材21の積層方向の下方側の面及び上方側の面にそれぞれ形成された第1及び第2配線層としての配線22とを備える。   The intermediate substrate 20 is adjacent to, for example, at least one double-sided substrate 10 (the double-sided substrate 10 on the lower side in the stacking direction in FIG. 1), and a resin base material 21 as a film-like second insulating layer, and the resin base material 21 and wirings 22 as first and second wiring layers formed on the lower surface and the upper surface in the stacking direction, respectively.

また、中間基板20は、樹脂基材21の少なくとも両面基板10側(図1においては樹脂基材21の両面側)に設けられた第1接着層としての接着層9を備える。更に、中間基板20は、接着層9と共に樹脂基材21を貫通するビアホール3内に充填形成された導電性ペーストからなるビア23を備える。   Further, the intermediate substrate 20 includes an adhesive layer 9 as a first adhesive layer provided on at least the double-sided substrate 10 side of the resin base material 21 (both sides of the resin base material 21 in FIG. 1). Further, the intermediate substrate 20 includes a via 23 made of a conductive paste filled in the via hole 3 penetrating the resin base material 21 together with the adhesive layer 9.

配線22は、図2に示すように、図2中破線で囲んだ電子部品80と積層方向に重なる領域29を含めて、樹脂基材21の両面上のほぼ全面に亘ってベタ状態で形成されている。ビア23は、本実施形態においては、配線22と面方向において非接続の状態で形成されている。   As shown in FIG. 2, the wiring 22 is formed in a solid state over almost the entire surface on both surfaces of the resin base material 21, including the region 29 overlapping with the electronic component 80 surrounded by the broken line in FIG. 2 in the stacking direction. ing. In the present embodiment, the via 23 is formed so as not to be connected to the wiring 22 in the surface direction.

ビア23は、例えば層間信号伝送用の導電ビアとして機能する。ビア23は、中間基板20において、樹脂基材21の面方向の端部よりやや内側の領域に、端部の外周に沿って所定間隔毎に形成されている。樹脂基材21の積層方向の下方側の面に形成された配線(以下、「下方側の配線」と呼ぶ。)22は、接着層9を介して電子部品80の背面81aと対向配置され、樹脂基材21の積層方向の上方側の面に形成された配線(以下、「上方側の配線」と呼ぶ。)22は、樹脂基材21を介して下方側の配線22と対向配置されている。   The via 23 functions as a conductive via for interlayer signal transmission, for example. The vias 23 are formed at predetermined intervals along the outer periphery of the end portion in a region slightly inside the end portion in the surface direction of the resin base material 21 in the intermediate substrate 20. A wiring 22 (hereinafter referred to as “downward wiring”) 22 formed on the lower surface of the resin base material 21 in the stacking direction is disposed opposite to the back surface 81a of the electronic component 80 with the adhesive layer 9 interposed therebetween. A wiring 22 (hereinafter referred to as “upper wiring”) 22 formed on the upper surface of the resin base material 21 in the stacking direction is disposed to face the lower wiring 22 through the resin base material 21. Yes.

このため、電子部品80の熱は、背面81a等から一旦接着層9に伝わり、下方側の配線22に伝わった後、この下方側の配線22に沿って面方向に拡がり拡散して放熱される。また、下方側の配線22に伝わった熱は、更に樹脂基材21を介して上方側の配線22に伝わり、同様に上方側の配線22に沿って面方向に拡がって拡散され放熱される。従って、中間基板20の配線22は、電子部品80の熱を層内で拡散する放熱層として機能する。   For this reason, the heat of the electronic component 80 is once transmitted from the back surface 81a and the like to the adhesive layer 9, and then transmitted to the lower wiring 22, and then spreads and diffuses in the surface direction along the lower wiring 22. . Further, the heat transmitted to the lower wiring 22 is further transmitted to the upper wiring 22 through the resin base material 21, and similarly spreads in the surface direction along the upper wiring 22 to be diffused and dissipated. Accordingly, the wiring 22 of the intermediate substrate 20 functions as a heat dissipation layer that diffuses the heat of the electronic component 80 within the layer.

各片面基板30は、それぞれ例えばフィルム状の樹脂基材31と、この樹脂基材31の一方の面に形成された第3配線層としての配線32とを備える。また、各片面基板30は、樹脂基材31の他方の面側に設けられた第2接着層としての接着層9aと、この接着層9a及び樹脂基材31を貫通するビアホール4内に充填形成された導電性ペーストからなるビア33とを備える。なお、部品内蔵基板1の最表層側にそれぞれ配置される片面基板30の外部に露出した配線32上には、所望により例えば半田からなるバンプ49が形成されている。   Each single-sided substrate 30 includes, for example, a film-like resin base material 31 and wirings 32 as third wiring layers formed on one surface of the resin base material 31. Each single-sided substrate 30 is filled and formed in an adhesive layer 9a as a second adhesive layer provided on the other surface side of the resin base material 31, and via holes 4 penetrating the adhesive layer 9a and the resin base material 31. And a via 33 made of a conductive paste. Note that bumps 49 made of, for example, solder are formed on the wirings 32 exposed to the outside of the single-sided board 30 respectively arranged on the outermost layer side of the component-embedded substrate 1.

なお、詳細は後述するが、両面基板10及び中間基板20は両面CCL(両面銅張積層板)により、また片面基板30は片面CCL(片面銅張積層板)によりそれぞれ構成することができる。各樹脂基材11,21,31は、それぞれ例えば厚さ約12μm〜25μm程度の低誘電材料の樹脂フィルムにより構成されている。樹脂フィルムとしては、例えばポリイミド(PI)、ポリオレフィン(PO)、液晶ポリマー(LCP)などを用いることができる。   Although details will be described later, the double-sided substrate 10 and the intermediate substrate 20 can be constituted by double-sided CCL (double-sided copper-clad laminate), and the single-sided substrate 30 can be constituted by single-sided CCL (single-sided copper-clad laminate). Each resin base material 11, 21, 31 is made of a low dielectric material resin film having a thickness of about 12 μm to 25 μm, for example. As the resin film, for example, polyimide (PI), polyolefin (PO), liquid crystal polymer (LCP), or the like can be used.

配線12,22,32は、例えば樹脂基材11,21,31上にパターン形成された銅箔等の導電材からなる。中間基板20の配線22は、図2に示すように樹脂基材21上にほぼベタ状に形成されている。部品内蔵基板1に内蔵された電子部品80,90は、例えばトランジスタ、集積回路(IC)、ダイオードなどの半導体素子の能動部品や、抵抗器、コンデンサ、リレー、圧電素子などの受動部品からなる。   The wirings 12, 22, and 32 are made of a conductive material such as copper foil patterned on the resin base materials 11, 21, 31, for example. The wiring 22 of the intermediate substrate 20 is formed in a substantially solid shape on the resin base material 21 as shown in FIG. The electronic components 80 and 90 built in the component built-in substrate 1 are composed of active components of semiconductor elements such as transistors, integrated circuits (ICs) and diodes, and passive components such as resistors, capacitors, relays and piezoelectric elements.

図1に示す電子部品80,90は、例えば再配線を施したWLP(Wafer Level Package)を示している。各電子部品80,90の電極形成面81b,91b側には、図示しないパッド上に形成された複数の再配線電極81,91が設けられており、これら再配線電極81,91の周囲には図示しない絶縁層が形成されている。   The electronic components 80 and 90 shown in FIG. 1 are, for example, WLP (Wafer Level Package) subjected to rewiring. A plurality of rewiring electrodes 81 and 91 formed on pads (not shown) are provided on the electrode forming surfaces 81b and 91b side of the electronic components 80 and 90, and around these rewiring electrodes 81 and 91, respectively. An insulating layer (not shown) is formed.

ビア23,33は、ビアホール3,4内にそれぞれ充填された導電性ペーストからなる。導電性ペーストは、例えばニッケル、金、銀、銅、アルミニウム、鉄などから選択される少なくとも1種類の低電気抵抗の金属粒子と、錫、ビスマス、インジウム、鉛などから選択される少なくとも1種類の低融点の金属粒子とを含んでいる。   The vias 23 and 33 are made of conductive paste filled in the via holes 3 and 4, respectively. The conductive paste is, for example, at least one kind of low electrical resistance metal particles selected from nickel, gold, silver, copper, aluminum, iron and the like, and at least one kind selected from tin, bismuth, indium, lead and the like. And low melting point metal particles.

導電性ペーストは、これらの金属粒子にエポキシ、アクリル、ウレタンなどを主成分とするバインダ成分を混合したペーストからなる。このように構成された導電性ペーストは、硬化温度が約150℃〜200℃で、硬化後の融点が約260℃以上となる金属焼結型の特性を備える。   The conductive paste is made of a paste in which a binder component mainly composed of epoxy, acrylic, urethane or the like is mixed with these metal particles. The conductive paste thus configured has a metal sintered type characteristic in which the curing temperature is about 150 ° C. to 200 ° C. and the melting point after curing is about 260 ° C. or more.

また、導電性ペーストは、例えば含有された低融点の金属が200℃以下で溶融し合金を形成することができ、特に銅や銀などとは金属間化合物を形成することができる特性を備えている。従って、各ビア23,33と配線12,32との接続部は、一括積層の熱圧着時に金属間化合物により合金化されることとなる。   In addition, the conductive paste has a characteristic that, for example, the contained low melting point metal can be melted at 200 ° C. or less to form an alloy, and in particular, can form an intermetallic compound with copper or silver. Yes. Therefore, the connection portions between the vias 23 and 33 and the wirings 12 and 32 are alloyed by an intermetallic compound at the time of thermocompression bonding in a batch.

なお、導電性ペーストは、例えば粒子径がナノレベルの金、銀、銅、ニッケルなどのフィラーが、上記のようなバインダ成分に混合されたナノペーストで構成することもできる。導電性ペーストは、その他、上記ニッケルなどの金属粒子が、上記のようなバインダ成分に混合されたペーストで構成することもできる。この場合、導電性ペーストは、金属粒子同士が接触することで電気的接続が行われる特性となる。   The conductive paste can be composed of a nanopaste in which fillers such as gold, silver, copper, and nickel having a nanometer particle size are mixed with the binder component as described above. In addition, the conductive paste can be constituted by a paste in which metal particles such as nickel are mixed with the binder component as described above. In this case, the conductive paste has a characteristic that electrical connection is made when the metal particles come into contact with each other.

また、導電性ペーストのビアホール3,4内への充填方法としては、例えば印刷工法、スピン塗布工法、スプレー塗布工法、ディスペンス工法、ラミネート工法、及びこれらを併用した工法などを用いることができる。ビア13は、上述したように樹脂基材11の両面に形成された配線12を層間接続するために、ビアホール2に施されためっきにより構成されている。   Moreover, as a filling method of the conductive paste into the via holes 3 and 4, for example, a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, and a method using these in combination can be used. As described above, the via 13 is formed by plating applied to the via hole 2 in order to connect the wirings 12 formed on both surfaces of the resin base material 11 to each other.

第1の実施形態に係る部品内蔵基板においては、図1に示すように、中間基板20を含めて中間基板20から積層方向の下方側に向かって、中間基板20、両面基板10及び片面基板30の順に配置され、中間基板20から積層方向の上方側に向かって、片面基板30、両面基板10及び片面基板30の順に配置された6層に積層されている。   In the component-embedded substrate according to the first embodiment, as shown in FIG. 1, the intermediate substrate 20, the double-sided substrate 10, and the single-sided substrate 30 including the intermediate substrate 20 from the intermediate substrate 20 toward the lower side in the stacking direction. The single-sided substrate 30, the double-sided substrate 10, and the single-sided substrate 30 are laminated in six layers from the intermediate substrate 20 toward the upper side in the stacking direction.

中間基板20と下方側の両面基板10及び上方側の片面基板30とは、中間基板20に設けられた接着層9によりそれぞれ接続され、各両面基板10と片面基板30とは、片面基板30に設けられた接着層9aによりそれぞれ接続されている。また、積層方向の最上部に配置された片面基板30を除く各片面基板30は、ビア33の一部が接着層9a側において電子部品80,90の再配線電極81,91と接続されている。   The intermediate substrate 20 is connected to the lower-side double-sided substrate 10 and the upper-side single-sided substrate 30 by an adhesive layer 9 provided on the intermediate substrate 20, and each double-sided substrate 10 and the single-sided substrate 30 are connected to the single-sided substrate 30. They are connected by the provided adhesive layers 9a. In addition, in each single-sided substrate 30 excluding the single-sided substrate 30 arranged at the top in the stacking direction, a part of the via 33 is connected to the rewiring electrodes 81 and 91 of the electronic components 80 and 90 on the adhesive layer 9a side. .

また、各片面基板30は、ビア33のその他が配線12又はビア13と接続されて、配線32が樹脂基材31の電子部品80,90側とは反対側に位置する状態で配置されている。接着層9,9aは、例えばエポキシ系やアクリル系などの、揮発成分が含まれた有機系接着材などからなる。   In addition, each single-sided substrate 30 is arranged in a state where the other of the via 33 is connected to the wiring 12 or the via 13 and the wiring 32 is located on the opposite side of the resin base 31 from the electronic components 80 and 90 side. . The adhesive layers 9 and 9a are made of, for example, an organic adhesive material containing a volatile component such as epoxy or acrylic.

このように構成された部品内蔵基板1においては、上述したように電子部品80が収容された両面基板10に接着層9を介して隣接配置される中間基板20の両面に配線22が形成されている。このため、放熱層として機能する配線22には、接着層9や樹脂基材21を介して電子部品80の熱が伝わるので、例えばこの熱を配線22の面方向に層内で拡散して放熱することが可能となる。   In the component-embedded substrate 1 configured as described above, the wiring 22 is formed on both surfaces of the intermediate substrate 20 that is disposed adjacent to the double-sided substrate 10 in which the electronic component 80 is accommodated via the adhesive layer 9 as described above. Yes. For this reason, since the heat of the electronic component 80 is transmitted to the wiring 22 functioning as a heat dissipation layer through the adhesive layer 9 and the resin base material 21, for example, this heat is diffused in the layer in the surface direction of the wiring 22 to dissipate heat. It becomes possible to do.

また、電子部品80,90は両面基板10の開口部19に収容されて積層方向に内蔵されているので、電子部品80,90を内蔵する箇所の厚さを両面基板10の厚さとほぼ同等の厚さに調整することができ、各単位基板間に電子部品80,90を収容するための絶縁体スペーサ等が不要で、部品内蔵基板全体の厚さを抑えて薄型化を図ることができる。   In addition, since the electronic components 80 and 90 are accommodated in the opening 19 of the double-sided substrate 10 and are built in the stacking direction, the thickness of the place where the electronic components 80 and 90 are built is almost equal to the thickness of the double-sided substrate 10. The thickness can be adjusted, and an insulating spacer or the like for housing the electronic components 80 and 90 is not required between the unit substrates, so that the thickness of the entire component-embedded substrate can be reduced and the thickness can be reduced.

更に、簡単な構造の両面基板10、中間基板20及び片面基板30を作製して電子部品80,90を収容した上で、例えば電子部品80の背面81aと下方側の配線22とをサーマルビアにより接続せずに、熱圧着により一括積層して部品内蔵基板1を製造することができるので、製造工程を簡素化することができる。   Furthermore, after the double-sided board 10, the intermediate board 20 and the single-sided board 30 having a simple structure are manufactured and the electronic components 80 and 90 are accommodated, for example, the back surface 81a of the electronic component 80 and the lower wiring 22 are connected by thermal vias. Since the component-embedded substrate 1 can be manufactured by batch lamination by thermocompression bonding without being connected, the manufacturing process can be simplified.

なお、開口部19に収容された電子部品80,90は、その周囲を接着層9,9aにより囲まれ、積層方向の各電子部品80,90間には中間基板20の樹脂基材21が介在している。このため、電子部品80,90のウェハダイが薄くても開口部19内の体積調整が可能で、積層方向の機械的強度を確保してハンドリング性を高め、電子部品80,90間の絶縁信頼性を高めることもできる。   The electronic components 80 and 90 accommodated in the opening 19 are surrounded by the adhesive layers 9 and 9a, and the resin base material 21 of the intermediate substrate 20 is interposed between the electronic components 80 and 90 in the stacking direction. doing. For this reason, even if the wafer die of the electronic components 80 and 90 is thin, the volume in the opening 19 can be adjusted, the mechanical strength in the stacking direction is ensured, the handling property is improved, and the insulation reliability between the electronic components 80 and 90 is increased. Can also be increased.

次に、第1の実施形態に係る部品内蔵基板1の製造方法について説明する。
図3〜図6は、部品内蔵基板の製造方法による製造工程を示すフローチャートである。また、図7〜図9は、部品内蔵基板を製造工程毎に示す断面図である。まず、図3を参照しながら片面基板30の製造工程について説明する。
Next, a manufacturing method of the component built-in substrate 1 according to the first embodiment will be described.
3 to 6 are flowcharts showing manufacturing steps according to the method for manufacturing the component-embedded substrate. 7 to 9 are cross-sectional views showing the component-embedded substrate for each manufacturing process. First, the manufacturing process of the single-sided substrate 30 will be described with reference to FIG.

図3に示すように、樹脂基材31の一方の面にベタ状態の銅箔などからなる導体層が形成された片面CCLを準備する。そして、この片面CCLの導体上に、例えばフォトリソグラフィによりエッチングレジストを形成した後にエッチングを行い、配線32をパターン形成する(ステップS100)。   As shown in FIG. 3, a single-sided CCL in which a conductor layer made of a solid copper foil or the like is formed on one surface of a resin base material 31 is prepared. Then, an etching resist is formed on the one-sided CCL conductor, for example, by photolithography, and then etching is performed to form a pattern of the wiring 32 (step S100).

配線32の形成に関しては、公知のセミアディティブ法によって、例えば樹脂基材31に蒸着又はスパッタリングなどにより導体薄膜を形成後、フォトリソグラフィなどによりめっきレジストを形成した後に電解めっきを行い、めっきレジストの剥離後にエッチングにより先に形成した導体薄膜を除去する方法で配線32を形成してもよい。   As for the formation of the wiring 32, a conductive thin film is formed on the resin substrate 31 by vapor deposition or sputtering, for example, and then a plating resist is formed by photolithography or the like, followed by electrolytic plating and peeling of the plating resist by a known semi-additive method. The wiring 32 may be formed by a method of removing the conductive thin film previously formed by etching.

このステップS100にて用いられる片面CCLは、例えば厚さ約12μm程度の銅箔からなる導体層に、厚さ約25μm程度の樹脂基材31を貼り合わせた構造からなる。この片面CCLとしては、例えば公知のキャスティング法により、銅箔にポリイミドのワニスを塗布してそのワニスを硬化させて作製されたものを用いることができる。   The single-sided CCL used in step S100 has a structure in which, for example, a resin base 31 having a thickness of about 25 μm is bonded to a conductor layer made of a copper foil having a thickness of about 12 μm. As this single-sided CCL, what was produced by apply | coating a polyimide varnish to copper foil by the well-known casting method, for example, and hardening the varnish can be used.

その他、片面CCLとしては、ポリイミドフィルム上にシード層をスパッタリングにより形成し、めっきにより銅を成長させて導体層を形成したものや、圧延又は電解銅箔とポリイミドフィルムとを接着材により貼り合わせて作製されたものなどを用いることもできる。   In addition, as single-sided CCL, a seed layer is formed on a polyimide film by sputtering, and copper is grown by plating to form a conductor layer, or a rolled or electrolytic copper foil and a polyimide film are bonded together with an adhesive. What was produced can also be used.

なお、樹脂基材31は、必ずしもポリイミドフィルムからなるものである必要はなく、上述したように液晶ポリマーなどのプラスチックフィルムからなるものであってもよい。このことは、樹脂基材11,21についても同様である。また、上記エッチングには塩化第二鉄や塩化第二銅などを主成分とするエッチャントを用いることができる。   The resin base material 31 does not necessarily need to be made of a polyimide film, and may be made of a plastic film such as a liquid crystal polymer as described above. The same applies to the resin base materials 11 and 21. For the etching, an etchant mainly composed of ferric chloride or cupric chloride can be used.

次に、樹脂基材31の配線32側と反対側の他方の面にラミネートなどにより接着材を貼り付けて(ステップS102)、接着層9aを形成する。このステップS102にて貼り付けられる接着材としては、例えば厚さ約25μm程度のエポキシ系熱硬化性フィルムを用いることができる。   Next, an adhesive material is pasted on the other surface of the resin base 31 opposite to the wiring 32 side by lamination or the like (step S102) to form the adhesive layer 9a. For example, an epoxy thermosetting film having a thickness of about 25 μm can be used as the adhesive material to be attached in step S102.

接着材の貼り付けには真空ラミネータを用いて、例えば減圧下の雰囲気中にて接着材が硬化しない温度で0.3MPaの圧力により加熱プレスして貼り合わせることが挙げられる。なお、接着層9,9aに用いられる接着材は、上記エポキシ系の熱硬化性樹脂のみならず、アクリル系の接着材や、熱可塑性ポリイミドなどに代表される熱可塑性接着材などであってもよい。また、接着材は、必ずしもフィルム状である必要はなく、ワニス状の樹脂を塗布したものであってもよい。   For bonding the adhesive, a vacuum laminator may be used, for example, heating and pressing with a pressure of 0.3 MPa at a temperature at which the adhesive does not cure in an atmosphere under reduced pressure. The adhesive used for the adhesive layers 9 and 9a is not limited to the epoxy thermosetting resin, but may be an acrylic adhesive or a thermoplastic adhesive typified by thermoplastic polyimide. Good. Further, the adhesive material does not necessarily have to be in the form of a film, and may be obtained by applying a varnish-like resin.

接着層9aを形成したら、接着層9a側から配線32に向かって、例えばUV−YAGレーザ等のレーザ装置を用いてレーザ光を照射し、接着層9a及び樹脂基材31を貫通するビアホール4を所定箇所に形成する(ステップS104)。形成されたビアホール4内には、例えばプラズマデスミア処理が施される。   After the adhesive layer 9a is formed, the via hole 4 penetrating the adhesive layer 9a and the resin base material 31 is irradiated from the adhesive layer 9a toward the wiring 32 using a laser device such as a UV-YAG laser. It is formed at a predetermined location (step S104). The formed via hole 4 is subjected to, for example, plasma desmear processing.

ビアホール4は、その他、炭酸ガスレーザ(COレーザ)やエキシマレーザなどで形成してもよく、ドリル加工や化学的なエッチングなどにより形成してもよい。また、デスミア処理は、CF及びO(四フッ化メタン+酸素)の混合ガスにより行うことができるが、Ar(アルゴン)などのその他の不活性ガスを用いることもできる。更に、デスミア処理は、いわゆるドライ処理ではなく、薬液を用いたウェットデスミア処理としてもよい。 In addition, the via hole 4 may be formed by a carbon dioxide laser (CO 2 laser), an excimer laser, or the like, or may be formed by drilling or chemical etching. The desmear treatment can be performed with a mixed gas of CF 4 and O 2 (tetrafluoromethane + oxygen), but other inert gases such as Ar (argon) can also be used. Furthermore, the desmear process may be a wet desmear process using a chemical solution instead of a so-called dry process.

ビアホール4を形成したら、例えばスクリーン印刷などの方法により上述したような構成の導電性ペーストをビアホール4内に充填して(ステップS106)、ビア33を形成する。こうして、配線32及びビア33が形成され接着層9aが備えられた樹脂基材31を有する片面基板30を複数製造する。   After the via hole 4 is formed, the conductive paste having the above-described configuration is filled into the via hole 4 by a method such as screen printing (step S106), and the via 33 is formed. In this way, a plurality of single-sided substrates 30 having the resin base material 31 on which the wiring 32 and the vias 33 are formed and provided with the adhesive layer 9a are manufactured.

なお、必要に応じて別途製造した電子部品80,90の再配線電極81,91を、片面基板30の所定のビアに、例えば図示しない電子部品用実装機(マウンタ)を用いて位置合わせする。そして、片面基板30の接着層9a及びビア33の導電性ペーストの硬化温度以下の温度で加熱することによって、電子部品80,90を仮留め接着して搭載する(ステップS108)。このようにして片面基板30及び電子部品80,90が搭載された片面基板30を複数準備しておく。   Note that the rewiring electrodes 81 and 91 of the electronic components 80 and 90 separately manufactured as necessary are aligned with predetermined vias of the single-sided substrate 30 by using, for example, an electronic component mounting machine (mounter) (not shown). Then, the electronic components 80 and 90 are temporarily bonded and mounted by heating at a temperature lower than the curing temperature of the conductive layer 9a of the single-sided substrate 30 and the via 33 (step S108). In this way, a plurality of single-sided substrates 30 on which the single-sided substrate 30 and the electronic components 80 and 90 are mounted are prepared.

次に、図4を参照しながら両面基板10の製造工程について説明する。
まず、図4に示すように、樹脂基材11の両面に導体層が形成された両面CCLを準備し(ステップS200)、所定箇所に上述したようにビアホール2を形成して(ステップS202)、例えばプラズマデスミア処理を行う。
Next, the manufacturing process of the double-sided substrate 10 will be described with reference to FIG.
First, as shown in FIG. 4, a double-sided CCL in which a conductor layer is formed on both sides of the resin base material 11 is prepared (step S200), and the via hole 2 is formed at a predetermined location as described above (step S202). For example, plasma desmear processing is performed.

次に、樹脂基材11の全面にパネルめっき処理を施して(ステップS204)、導体層上及びビアホール2内にめっき層を形成し、配線12及びビア13の原型を形成する。そして、樹脂基材11の両面にエッチングなどを施して、配線12やビア13などをパターン形成する(ステップS206)。   Next, panel plating is performed on the entire surface of the resin base material 11 (step S204), a plating layer is formed on the conductor layer and in the via hole 2, and a prototype of the wiring 12 and the via 13 is formed. Then, etching or the like is performed on both surfaces of the resin base material 11 to pattern the wirings 12 and vias 13 (step S206).

最後に、電子部品80,90が内蔵される部分の樹脂基材11を上述したようなUV−YAGレーザ等のレーザ装置を用いてレーザ光を照射することにより除去し、所定の開口径を有する開口部19を形成して(ステップS208)、電子部品80,90が収容される開口部19を有する両面基板10を複数製造する。   Finally, the resin base material 11 in which the electronic components 80 and 90 are incorporated is removed by irradiating laser light using a laser device such as the UV-YAG laser as described above, and has a predetermined opening diameter. The opening 19 is formed (step S208), and a plurality of the double-sided substrates 10 having the opening 19 in which the electronic components 80 and 90 are accommodated are manufactured.

次に、図5を参照しながら中間基板20の製造工程について説明する。
まず、図7(a)に示すように、例えばポリイミドフィルムからなる樹脂基材21の両面に導体層8が形成された両面CCLを準備する(ステップS300)。そして、図7(b)に示すように、エッチングなどを施して両面に配線22を形成する(ステップS302)。
Next, the manufacturing process of the intermediate substrate 20 will be described with reference to FIG.
First, as shown to Fig.7 (a), the double-sided CCL by which the conductor layer 8 was formed on both surfaces of the resin base material 21 which consists of polyimide films, for example is prepared (step S300). Then, as shown in FIG. 7B, the wiring 22 is formed on both surfaces by performing etching or the like (step S302).

次に、図7(c)に示すように、例えば樹脂基材21の両面側に接着材を貼り付けて(ステップS304)、接着層9を形成する。そして、図7(d)に示すように、各接着層9の表層にマスク材7を貼り付けて(ステップS306)、所定箇所にレーザ光を照射する。   Next, as illustrated in FIG. 7C, for example, an adhesive is pasted on both sides of the resin base material 21 (step S <b> 304) to form the adhesive layer 9. And as shown in FIG.7 (d), the mask material 7 is affixed on the surface layer of each contact bonding layer 9 (step S306), and a laser beam is irradiated to a predetermined location.

これにより、図7(e)に示すように、マスク材7、接着層9及び樹脂基材21を貫通するビアホール3を形成する(ステップS308)。なお、上記ステップS308においては、後にビア23が形成されるビアホール3内に配線22が露出しないようにビアホール3を形成する。   Thereby, as shown in FIG.7 (e), the via hole 3 which penetrates the mask material 7, the contact bonding layer 9, and the resin base material 21 is formed (step S308). In step S308, the via hole 3 is formed so that the wiring 22 is not exposed in the via hole 3 in which the via 23 will be formed later.

そして、図7(f)に示すように、形成したビアホール3内に導電性ペーストを充填して(ステップS310)、最後に、図7(g)に示すように、マスク材7を除去し(ステップS312)、ビア23を形成する。これにより、接着層9及び配線22が両面側に設けられビア23が形成された樹脂基材21を有する中間基板20を製造する。   Then, as shown in FIG. 7F, the formed via hole 3 is filled with a conductive paste (step S310), and finally the mask material 7 is removed as shown in FIG. Step S312), the via 23 is formed. As a result, the intermediate substrate 20 having the resin base material 21 in which the adhesive layer 9 and the wiring 22 are provided on both sides and the vias 23 are formed is manufactured.

このようにして複数の両面基板10、中間基板20及び複数の片面基板30を作製したら、図6及び図8に示すように、各片面基板30に搭載された各電子部品80,90と各両面基板10の開口部19とを位置合わせすると共に、各ビア23,33と各配線12,32とを位置合わせして位置決めし、積層する(ステップS400)。   When the plurality of double-sided substrates 10, the intermediate substrate 20, and the plurality of single-sided substrates 30 are manufactured in this manner, as shown in FIGS. 6 and 8, the electronic components 80 and 90 mounted on the single-sided substrates 30 and the double-sided substrates While aligning with the opening part 19 of the board | substrate 10, each via | veer 23,33 and each wiring 12,32 are aligned and positioned, and are laminated | stacked (step S400).

最後に、例えば熱圧着を行う場合は真空プレス機を用いて1kPa以下の減圧雰囲気中にて加熱加圧することで熱圧着により一括積層し(ステップS402)。図9に示すような部品内蔵基板1を製造する。その後、必要に応じて、最表層の配線32上にバンプ49を形成すれば、図1に示すような部品内蔵基板1を製造することができる。   Finally, for example, when thermocompression bonding is performed, batch lamination is performed by thermocompression bonding by heating and pressurizing in a reduced pressure atmosphere of 1 kPa or less using a vacuum press machine (step S402). The component built-in substrate 1 as shown in FIG. 9 is manufactured. Thereafter, if the bumps 49 are formed on the outermost layer wiring 32 as necessary, the component-embedded substrate 1 as shown in FIG. 1 can be manufactured.

なお、一括積層時には、層間や開口部19内の接着層9,9aの硬化と同時に、ビアホール3,4内に充填された導電性ペーストの硬化及び合金化が行われる。そして、金属間化合物の合金層により、各配線12,32やビア23,33の接続部の機械的強度を高め、接続信頼性を高めることができる。各基板10,20,30の積層処理は、熱圧着による一括積層に限定されるものではない。   At the time of batch stacking, the conductive paste filled in the via holes 3 and 4 is cured and alloyed simultaneously with the curing of the adhesive layers 9 and 9a in the interlayer and the opening 19. And the alloy strength of the intermetallic compound can increase the mechanical strength of the connecting portions of the wirings 12 and 32 and the vias 23 and 33, and can improve the connection reliability. The lamination process of the substrates 10, 20, and 30 is not limited to batch lamination by thermocompression bonding.

図10は、本発明の第1の実施形態に係る部品内蔵基板を備えた実装体を示す断面図である。実装体100は、第1の実施形態に係る部品内蔵基板1の表面及び裏面側に、内蔵された電子部品80,90とは異なる他の電子部品98,99を表面実装したものである。表面実装された各電子部品98,99は、例えば約260℃程度の温度による半田リフロー処理によって形成されたバンプ49を介して、片面基板30の所定箇所の配線32に接続されている。   FIG. 10 is a cross-sectional view showing a mounting body including the component built-in substrate according to the first embodiment of the present invention. The mounting body 100 is obtained by surface-mounting other electronic components 98 and 99 different from the built-in electronic components 80 and 90 on the front and back sides of the component-embedded substrate 1 according to the first embodiment. The surface-mounted electronic components 98 and 99 are connected to the wiring 32 at a predetermined location on the single-sided substrate 30 through bumps 49 formed by solder reflow processing at a temperature of about 260 ° C., for example.

図示の例では、部品内蔵基板1の裏面側に一つの電子部品98が、表面側に二つの電子部品99がそれぞれ表面実装されているが、表面側の二つの電子部品99は、更にモールド樹脂などによる樹脂部材97によって配線32上で封止されている。このように構成された実装体100においても、部品内蔵基板1に内蔵された電子部品80の熱を中間基板20の配線22により層内で拡散して放熱するなど、上述した作用効果と同様の作用効果を奏することができる。   In the example shown in the figure, one electronic component 98 is mounted on the back side of the component-embedded substrate 1 and two electronic components 99 are mounted on the front side, but the two electronic components 99 on the front side are further molded resin. It is sealed on the wiring 32 by a resin member 97 such as. Also in the mounting body 100 configured in this manner, the heat of the electronic component 80 built in the component built-in substrate 1 is diffused in the layer by the wiring 22 of the intermediate substrate 20 to dissipate heat, and the same effects as described above. An effect can be produced.

また、中間基板20が介在するため部品内蔵基板1全体の歪みや変形が抑えられているので、確実に電子部品98,99の表面実装を行うことができる。これと共に、部品内蔵基板1の構成部材に半田を用いていないため、半田リフロー時に基板内部で半田が再溶融することはなく、高い接続信頼性を確保することができる。   Further, since the intermediate substrate 20 is interposed, distortion and deformation of the entire component-embedded substrate 1 are suppressed, so that the surface mounting of the electronic components 98 and 99 can be reliably performed. At the same time, since solder is not used as a constituent member of the component-embedded substrate 1, the solder does not remelt inside the substrate during solder reflow, and high connection reliability can be ensured.

図11は、本発明の第2の実施形態に係る部品内蔵基板を示す断面図である。図12は、部品内蔵基板の中間基板を示す上面図である。なお、図11は図12におけるB−B’線断面を表した図である。また、以降において、既に説明した部分と重複する箇所には同一の符号を附して説明を割愛することがある。   FIG. 11 is a cross-sectional view showing a component-embedded substrate according to the second embodiment of the present invention. FIG. 12 is a top view showing the intermediate board of the component built-in board. FIG. 11 is a view showing a cross section taken along line B-B ′ in FIG. 12. In the following description, the same reference numerals are attached to portions that overlap the already described portions, and the description may be omitted.

図11及び図12に示すように、第2の実施形態に係る部品内蔵基板1Aは、中間基板20の上方側の配線22が、積層方向の上方側の電子部品90と接続された片面基板30の配線32と積層方向に重ならない領域に形成されている点が、第1の実施形態に係る部品内蔵基板1と相違している。   As shown in FIGS. 11 and 12, the component-embedded substrate 1A according to the second embodiment includes a single-sided substrate 30 in which the wiring 22 on the upper side of the intermediate substrate 20 is connected to the electronic component 90 on the upper side in the stacking direction. This is different from the component-embedded substrate 1 according to the first embodiment in that it is formed in a region that does not overlap the wiring 32 in the stacking direction.

すなわち、上方側の配線22は、図12に示すような領域29内において配線32と積層方向に重なる領域29aには形成されないパターンに形成されている。これにより、上記作用効果と同様の作用効果を奏すると共に、中間基板20の上方側の配線22とその直上の片面基板30の電子部品90と接続された配線32とが一括積層時に接触することはなく、電気的接続信頼性をより向上させることができる。   That is, the upper wiring 22 is formed in a pattern that is not formed in the region 29a overlapping the wiring 32 in the stacking direction in the region 29 as shown in FIG. As a result, the same effects as the above-described effects can be obtained, and the wiring 22 on the upper side of the intermediate substrate 20 and the wiring 32 connected to the electronic component 90 of the single-sided substrate 30 immediately above the contact can be contacted at the time of batch lamination. In addition, the electrical connection reliability can be further improved.

図13は、本発明の第3の実施形態に係る部品内蔵基板を示す断面図である。図14は、部品内蔵基板の中間基板を示す上面図である。なお、図13は図14におけるC−C’線断面を表した図である。図13及び図14に示すように、第3の実施形態に係る部品内蔵基板1Bは、中間基板20の上方側及び下方側の配線22が、それぞれ積層方向に対向する片面基板30の配線32及び両面基板10の配線12と積層方向に重ならず、且つ各ビア23により囲まれた領域内において例えば格子状パターンにパターン形成されている点が、第2の実施形態に係る部品内蔵基板1Aと相違している。なお、配線22のパターンは、格子状パターンのみならず、放熱設計に基づき種々のパターンで構成することができる。   FIG. 13 is a cross-sectional view showing a component built-in substrate according to a third embodiment of the present invention. FIG. 14 is a top view showing an intermediate board of the component built-in board. FIG. 13 is a view showing a cross section taken along line C-C ′ in FIG. 14. As shown in FIGS. 13 and 14, the component-embedded substrate 1 </ b> B according to the third embodiment includes the wirings 32 on the single-sided substrate 30 in which the upper and lower wirings 22 of the intermediate substrate 20 face each other in the stacking direction. The point that it is not overlapped with the wiring 12 of the double-sided substrate 10 in the stacking direction and is patterned in, for example, a lattice pattern in the region surrounded by the vias 23 is the same as the component built-in substrate 1A according to the second embodiment. It is different. In addition, the pattern of the wiring 22 can be composed of not only a grid pattern but also various patterns based on a heat radiation design.

図15は、本発明の第4の実施形態に係る部品内蔵基板を示す断面図である。なお、図15においては、バンプ49の図示は省略している。図15に示すように、第4の実施形態に係る部品内蔵基板1Cは、中間基板20の配線22が各ビア23により囲まれた領域内においてほぼベタ状態であり、中間基板20よりも積層方向の上方側における各基板の配置構成が異なる点が、第1の実施形態に係る部品内蔵基板1と相違している。   FIG. 15 is a cross-sectional view showing a component built-in substrate according to a fourth embodiment of the present invention. In FIG. 15, the illustration of the bumps 49 is omitted. As shown in FIG. 15, the component-embedded substrate 1 </ b> C according to the fourth embodiment is substantially solid in a region where the wiring 22 of the intermediate substrate 20 is surrounded by the vias 23, and the stacking direction is higher than that of the intermediate substrate 20. This is different from the component-embedded substrate 1 according to the first embodiment in that the arrangement configuration of each substrate on the upper side of the component is different.

すなわち、部品内蔵基板1Cにおいては、中間基板20よりも積層方向の上方側に向かって、両面基板10及び片面基板30の順に配置されている。また、各両面基板10の開口部に収容された電子部品80,90の背面81a,91a同士が、中間基板20を挟んで積層方向に対向するように積層配置されている。   That is, in the component built-in substrate 1 </ b> C, the double-sided substrate 10 and the single-sided substrate 30 are arranged in this order from the intermediate substrate 20 toward the upper side in the stacking direction. In addition, the back surfaces 81a and 91a of the electronic components 80 and 90 accommodated in the openings of the double-sided substrates 10 are stacked so as to face each other with the intermediate substrate 20 interposed therebetween.

そして、このような構成で部品内蔵基板1の最表層に配置されていた片面基板30が省略されている点が、第1の実施形態に係る部品内蔵基板1とは異なっている。各基板10,20,30の積層配置態様は、積層方向の上方側から下方側又は下方側から上方側に向かって、それぞれ片面基板30、両面基板10、中間基板20、両面基板10及び片面基板30となっている。   And the point which the single-sided board | substrate 30 arrange | positioned in the outermost surface layer of the components built-in board 1 by such a structure is abbreviate | omitted from the components built-in board 1 which concerns on 1st Embodiment. The stacked arrangement of the substrates 10, 20, and 30 is such that the single-sided substrate 30, the double-sided substrate 10, the intermediate substrate 20, the double-sided substrate 10, and the single-sided substrate are respectively arranged from the upper side in the stacking direction to the lower side or from the lower side to the upper side. 30.

なお、電子部品90の熱は、例えば接着層9を介して中間基板20の上方側の配線22に伝わり拡散して放熱される。このように、第4の実施形態に係る部品内蔵基板1Cは、複数の電子部品80,90を内蔵しつつ放熱特性を向上させた5層構造の部品内蔵基板を実現することができる。   The heat of the electronic component 90 is transferred to the wiring 22 on the upper side of the intermediate substrate 20 through the adhesive layer 9 and diffused and radiated. As described above, the component-embedded substrate 1C according to the fourth embodiment can realize a component-embedded substrate having a five-layer structure in which a plurality of electronic components 80 and 90 are incorporated and the heat dissipation characteristics are improved.

図16は、本発明の第5の実施形態に係る部品内蔵基板を示す断面図である。なお、図16においては、バンプ49の図示は省略している。図16に示すように、第5の実施形態に係る部品内蔵基板1Dは、中間基板20の配線22が各ビア23により囲まれた領域内においてほぼベタ状態であり、中間基板20の上方側及び下方側の配線22が、積層方向の上方側及び下方側の電子部品90,80と接続された片面基板30の配線32と積層方向に重ならない領域に形成されており、且つ中間基板20よりも積層方向の下方側における各基板の配置構成が異なる点が、第2の実施形態に係る部品内蔵基板1Aと相違している。   FIG. 16 is a cross-sectional view showing a component built-in substrate according to a fifth embodiment of the present invention. In FIG. 16, the illustration of the bumps 49 is omitted. As shown in FIG. 16, the component built-in substrate 1 </ b> D according to the fifth embodiment is substantially solid in a region where the wirings 22 of the intermediate substrate 20 are surrounded by the vias 23. The lower wiring 22 is formed in a region that does not overlap with the wiring 32 of the single-sided substrate 30 connected to the upper and lower electronic components 90 and 80 in the stacking direction, and more than the intermediate substrate 20. The difference in the arrangement configuration of the substrates on the lower side in the stacking direction is different from the component-embedded substrate 1A according to the second embodiment.

すなわち、部品内蔵基板1Dにおいては、中間基板20よりも積層方向の下方側に向かって、片面基板30、両面基板10及び片面基板30の順に配置されている。また、各両面基板10の開口部に収容された電子部品90,80の電極形成面91b,81b同士が、片面基板30、中間基板20及び片面基板30を挟んで積層方向に対向するように積層配置されている。中間基板20に隣接する各片面基板30における電子部品90,80と接続された配線32同士は、接着層9及び樹脂基材21を挟んで対向配置されている。   That is, in the component built-in substrate 1 </ b> D, the single-sided substrate 30, the double-sided substrate 10, and the single-sided substrate 30 are arranged in this order from the intermediate substrate 20 toward the lower side in the stacking direction. In addition, the electrode forming surfaces 91b and 81b of the electronic components 90 and 80 accommodated in the openings of each double-sided substrate 10 are stacked so that the single-sided substrate 30, the intermediate substrate 20 and the single-sided substrate 30 are opposed to each other in the stacking direction. Has been placed. The wirings 32 connected to the electronic components 90 and 80 in each single-sided substrate 30 adjacent to the intermediate substrate 20 are arranged to face each other with the adhesive layer 9 and the resin base material 21 interposed therebetween.

これにより、上記作用効果と同様の作用効果を奏すると共に、中間基板20の上方側及び下方側の配線22とそれぞれの直近の片面基板30の電子部品90,80と接続された配線32とが一括積層時に接触することはなく、電気的接続信頼性をより向上させることができる。   Accordingly, the same effects as the above-described effects can be obtained, and the upper and lower wirings 22 of the intermediate substrate 20 and the wirings 32 connected to the electronic components 90 and 80 of the respective single-sided substrates 30 can be collectively displayed. There is no contact during lamination, and the electrical connection reliability can be further improved.

これら第2〜第5の実施形態に係る部品内蔵基板1A〜1Dの構成によっても、基板内部に内蔵された電子部品の熱を層内で拡散して放熱し、簡単な製造工程で製造でき部品内蔵基板全体の薄型化を図ることができるという第1の実施形態の作用効果と同様の作用効果を奏することができる。   Even with the configurations of the component-embedded substrates 1A to 1D according to the second to fifth embodiments, the heat of the electronic components incorporated in the substrate is diffused and dissipated in the layers, and the components can be manufactured with a simple manufacturing process. The same effect as the effect of 1st Embodiment that can achieve thickness reduction of the whole built-in board | substrate can be show | played.

1 部品内蔵基板
2,3,4 ビアホール
9,9a 接着層
10 両面基板
11,21,31 樹脂基材
12,22,32 配線
13,23,33 ビア
19 開口部
20 中間基板
30 片面基板
80,90 電子部品
81,91 再配線電極
81a,91a 背面
81b,91b 電極形成面
100 実装体
DESCRIPTION OF SYMBOLS 1 Component-embedded substrate 2, 3, 4 Via hole 9, 9a Adhesive layer 10 Double-sided substrate 11, 21, 31 Resin base material 12, 22, 32 Wiring 13, 23, 33 Via 19 Opening 20 Intermediate substrate 30 Single-sided substrate 80, 90 Electronic component 81, 91 Redistribution electrode 81a, 91a Back surface 81b, 91b Electrode forming surface 100 Mounting body

Claims (2)

複数の単位基板を積層し、積層方向に複数の電子部品を内蔵してなる多層構造の部品内蔵基板であって、
前記複数の単位基板は、
第1絶縁層を有し、第1電子部品が収容された開口部を備えた第1基板と、
前記第1基板に隣接し、第2絶縁層、前記第2絶縁層の前記第1基板側の面に形成された第1配線層、前記第2絶縁層の前記第1基板側の面とは反対側の面に形成された第2配線層、前記第2絶縁層の前記第1基板側及びその反対側に設けられた第1接着層並びに前記第2絶縁層及び第1接着層を貫通すると共に前記第1配線層及び第2配線層と非接続に形成された第1層間導電層とを備えた中間基板と
前記中間基板の前記第1基板とは反対側に配置され、第3絶縁層を有し、前記第1電子部品と積層方向に重なる位置に第2電子部品が収容された開口部を備えた第2基板と、
前記第2基板と前記中間基板との間に配置され、第4絶縁層、この第4絶縁層の一方の面に形成された第3配線層、前記第4絶縁層を貫通し前記第3配線層と前記第2電子部品とを接続するビア、及び前記第4絶縁層の他方の面側に設けられた第2接着層を備えた第3基板とを含み、
前記第1基板、前記中間基板及び前記第3基板は、前記第1配線層と前記第1電子部品とが前記第1接着層を介して対向するように配置されると共に、前記第2配線層と前記第3配線層とが前記第1接着層を介して対向するように配置され積層され
前記中間基板の前記第1及び第2配線層の少なくとも前記第2配線層は、前記第3基板の前記第3配線層と積層方向に重ならない領域に形成されている
ことを特徴とする部品内蔵基板。
A multilayered component-embedded substrate in which a plurality of unit substrates are stacked and a plurality of electronic components are embedded in the stacking direction,
The plurality of unit substrates are:
A first substrate having a first insulating layer and having an opening accommodating a first electronic component;
What is the second insulating layer , the first wiring layer formed on the surface of the second insulating layer on the first substrate side, adjacent to the first substrate, and the surface of the second insulating layer on the first substrate side second wiring layer formed on the opposite side, a first adhesive layer and said second insulating layer and the first adhesive layer prior SL provided on the first substrate side and the opposite side of the second insulating layer through And an intermediate substrate comprising a first interlayer conductive layer formed in a non-connected manner with the first wiring layer and the second wiring layer ,
A second insulating layer disposed on the opposite side of the intermediate substrate from the first substrate, having a third insulating layer, and having an opening that accommodates the second electronic component at a position overlapping the first electronic component in the stacking direction; Two substrates,
A fourth insulating layer disposed between the second substrate and the intermediate substrate, a third wiring layer formed on one surface of the fourth insulating layer, and penetrating through the fourth insulating layer; A third substrate including a via connecting the layer and the second electronic component, and a second adhesive layer provided on the other surface side of the fourth insulating layer ,
The first substrate, the intermediate substrate and the third substrate, the first wiring layer and the first electronic component is disposed so as to face each other through the first adhesive layer Rutotomoni, the second wiring layer And the third wiring layer are arranged and laminated so as to face each other with the first adhesive layer interposed therebetween ,
Built-in component characterized in that at least the second wiring layer of the first and second wiring layers of the intermediate substrate is formed in a region not overlapping with the third wiring layer of the third substrate in the stacking direction. substrate.
複数の単位基板を積層し、積層方向に複数の電子部品を内蔵してなる多層構造の部品内蔵基板の製造方法であって、
前記単位基板として第1絶縁層に第1電子部品が収容される開口部を形成して第1基板を作製する工程と、
前記単位基板として第2絶縁層の前記第1基板側に配置される面に第1配線層を形成し、前記第2絶縁層の前記第1基板側とは反対側に配置される面に第2配線層を形成し、前記第2絶縁層の前記第1基板側及びその反対側に第1接着層を設けると共に、前記第2絶縁層及び第1接着層を貫通し前記第1配線層及び第2配線層と非接続な第1層間導電層を形成して中間基板を作製する工程と、
前記単位基板として第3絶縁層に第2電子部品が前記第1電子部品と積層方向に重なる位置に収容される開口部を形成して第2基板を作製する工程と、
前記単位基板として第4絶縁層の一方の面に第3配線層を形成すると共に、前記第4絶縁層を貫通し前記第3配線層と前記第2電子部品とに接続されるビアを形成し、前記第4絶縁層の他方の面側に第2接着層を設けて第3基板を作製する工程と、
前記第1基板の前記開口部に前記第1電子部品を収容し、前記第1基板に対して前記中間基板を前記第1配線層と前記第1電子部品とが前記第1接着層を介して対向するように隣接配置すると共に、前記第2基板を前記中間基板に対して前記第1基板とは反対側に配置し、前記単位基板を積層方向に複数積層する工程と
を備え、
前記中間基板を作製する工程では、前記第1及び第2配線層の少なくとも前記第2配線層を、前記第3基板の前記第3配線層と積層方向に重ならない領域に形成し、
前記積層する工程では、前記第3基板を前記第2基板と前記中間基板との間に、前記第2配線層と前記第3配線層とが前記第1接着層を介して対向するように配置して積層する
ことを特徴とする部品内蔵基板の製造方法。
A method for manufacturing a component-embedded substrate having a multilayer structure in which a plurality of unit substrates are stacked and a plurality of electronic components are embedded in a stacking direction,
Forming a first substrate by forming an opening for accommodating the first electronic component in the first insulating layer as the unit substrate; and
A first wiring layer is formed on a surface of the second insulating layer that is disposed on the first substrate side as the unit substrate, and the second insulating layer is disposed on a surface that is disposed on the opposite side of the first substrate side. forming a second wiring layer, wherein the two first substrate side before Symbol of the insulating layer and the opposite side provided with a first adhesive layer, through said second insulating layer and the first adhesive layer the first wiring layer And forming an intermediate substrate by forming a first interlayer conductive layer that is not connected to the second wiring layer ;
Forming a second substrate by forming an opening in the third insulating layer as the unit substrate in a position where the second electronic component overlaps the first electronic component in the stacking direction;
A third wiring layer is formed on one surface of the fourth insulating layer as the unit substrate, and a via passing through the fourth insulating layer and connected to the third wiring layer and the second electronic component is formed. Providing a second adhesive layer on the other surface side of the fourth insulating layer to produce a third substrate;
The first electronic component is accommodated in the opening of the first substrate, and the intermediate substrate is placed on the first substrate with the first wiring layer and the first electronic component interposed through the first adhesive layer. Arranging the second substrate on the side opposite to the first substrate with respect to the intermediate substrate, and laminating a plurality of the unit substrates in the laminating direction ;
With
In the step of manufacturing the intermediate substrate, at least the second wiring layer of the first and second wiring layers is formed in a region that does not overlap with the third wiring layer of the third substrate in the stacking direction;
In the step of laminating, the third substrate is disposed between the second substrate and the intermediate substrate so that the second wiring layer and the third wiring layer are opposed to each other with the first adhesive layer interposed therebetween. And manufacturing the component-embedded substrate.
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