JPH0278253A - Multilayer plastic chip carrier - Google Patents
Multilayer plastic chip carrierInfo
- Publication number
- JPH0278253A JPH0278253A JP63230613A JP23061388A JPH0278253A JP H0278253 A JPH0278253 A JP H0278253A JP 63230613 A JP63230613 A JP 63230613A JP 23061388 A JP23061388 A JP 23061388A JP H0278253 A JPH0278253 A JP H0278253A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- circuits
- layer
- insulating layer
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000010030 laminating Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 36
- 239000012790 adhesive layer Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 abstract description 4
- 239000011888 foil Substances 0.000 abstract description 4
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- VLENVEGZSVNZDD-UHFFFAOYSA-N NC(=O)OCC.[S] Chemical compound NC(=O)OCC.[S] VLENVEGZSVNZDD-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本発明は、電子部品をパッケージするために用いられる
多層プラスチックチップキャリアに関す゛るものである
。The present invention relates to multilayer plastic chip carriers used for packaging electronic components.
ＩＣチップなど電子部品をパッケージするために用いら
れるプラスチックピングリッドアレイ（ＰＰＧＡ）やプ
ラスチックリードレスナツプキャリア（ＰＬＣＣ）など
のチップキャリアとして、積層板などで形成した基板を
多層に積層した多層プラスチックチップキャリアがある
。
この多層プラスチ・２クナツプキヤリアＡは、第５図（
ａ）や第５図（ｂ）に示すように、中央部にキャビティ
凹所１０を凹設した基板１と中央部にキャビティ凹所１
０よりも大きな開口部１１を設けた基板１（１枚乃至複
数枚）を接着層３によって積層接着して形成されるしの
であり、各基板１の上下面には銅箔のエツチング加工な
どによって回路２が形成しである。基板１に形成される
回路２のうち上下の基板１．１間に挟まれるものは多層
プラスチックチップキャリアＡの内層に存在することに
なるために内層回路２ａとなり、多層プラスチックチツ
ブキャリアＡの上下面に露出するものは外層回路２ｂと
なる。そして基板１のうちキャビティ凹所１０を設けた
最も下の基板１ａの内層回路２ａはキャビティ凹所１０
を中心とする放射状に多数本形成してあり、キャビティ
凹所１０側の端部はインナーリード部１２として他の基
板１ｂの開口部１１内に突出させである。そしてこのよ
うに形成される多層プラスチックチップキャリアＡにあ
って、キャビティ凹所１０にＩＣチップなどの電子部品
１３を実装し、基板１ａの内層回路２ａのインナーリー
ド部１２と電子部品１３との開にワイヤーボンデング１
４等を施すことによって、電子部品１３と内層回路２ａ
とを電気的に接続するものである。この内層回路２ａは
外部への接続部となる端子ピンなどと接続されており、
マザーボードなどに多層プラスチックチップキャリアＡ
を搭載する際に内層回路２ａを介して電子部品１３をマ
ザーボードに電気的に接続することができる。A multilayer plastic chip made by laminating multiple layers of substrates made of laminates, etc. as chip carriers such as plastic pin grid arrays (PPGAs) and plastic leadless nap carriers (PLCCs) used to package electronic components such as IC chips. I have a career. This multilayer plastic carrier A is shown in Figure 5 (
As shown in a) and FIG. 5(b), a substrate 1 with a cavity recess 10 in the center and a cavity recess 1 in the center are shown.
It is formed by laminating and bonding substrates 1 (one or more) each having an opening 11 larger than 0 with an adhesive layer 3, and the upper and lower surfaces of each substrate 1 are etched with copper foil. Circuit 2 is formed. Of the circuits 2 formed on the substrate 1, those sandwiched between the upper and lower substrates 1.1 are present in the inner layer of the multilayer plastic chip carrier A, and thus become inner layer circuits 2a, and are placed on the upper and lower layers of the multilayer plastic chip carrier A. What is exposed on the bottom surface becomes the outer layer circuit 2b. The inner layer circuit 2a of the lowest substrate 1a provided with the cavity recess 10 of the substrate 1 has the cavity recess 10.
A large number of leads are formed radially around the center, and the end on the cavity recess 10 side serves as an inner lead part 12 and projects into the opening 11 of the other substrate 1b. In the multilayer plastic chip carrier A formed in this manner, an electronic component 13 such as an IC chip is mounted in the cavity recess 10, and the inner lead portion 12 of the inner layer circuit 2a of the substrate 1a and the electronic component 13 are opened. wire bonding 1
4 etc., the electronic component 13 and the inner layer circuit 2a
It electrically connects the This inner layer circuit 2a is connected to terminal pins etc. that serve as connections to the outside.
Multilayer plastic chip carrier A for motherboards, etc.
When mounting the electronic component 13 on the motherboard, the electronic component 13 can be electrically connected to the motherboard via the inner layer circuit 2a.
そしてこの多層プラスチックチップキャリアＡにおいで
問題となるのは、上下の基板１間の密着性が悪いという
ことである。すなわち、上下の基板１はボンディング用
プリプレグなど接着層３をはさんで加熱加圧成形するこ
とによって、接着層３を介して第６図（、）のように積
層接着されているが、基板１（基板１ａ）に設けた回路
２（内層回路２ａ）が存在するために第６図（ｂ）のよ
うに接着層３と基板１との間に隙間２０が生じ、この隙
間２０に不純物や異物などが入り込んで電子部品１３の
性能が低下したり信頼性が低下したりするおそれがある
。特に、隣合う回路２間の間隔ｒが大きいと接着層３で
回路２開のギャップを埋めることができないために隙間
２０の発生が多くなるものである。
そこで、隙間２０の発生を防ぐために、接着層３の厚み
を厚（設定することがなされているが、このように接着
層３の厚みを厚くすると接着層３の接着樹脂が第７図の
ようにはみ出して回路２のインナーリード部１２が覆わ
れ、電子部品１３との間でワイヤーボンデング１４を施
すことが不可能になるおそれがある。
本発明は上記の点に鑑みて為されたものであり、接着層
３を厚く設定する必要なく、接着１３と基板１との」に
隙間が生じるようなおそれなく基板１を上下に積層して
形成することができる多層プラスチックチップキャリア
を提供することを目的とするものである。A problem with this multilayer plastic chip carrier A is that the adhesion between the upper and lower substrates 1 is poor. That is, the upper and lower substrates 1 are laminated and bonded through the adhesive layer 3 by heat and pressure molding with the adhesive layer 3 such as prepreg for bonding in between, as shown in FIG. Due to the presence of the circuit 2 (inner layer circuit 2a) provided on the (substrate 1a), a gap 20 is created between the adhesive layer 3 and the substrate 1 as shown in FIG. There is a possibility that the performance or reliability of the electronic component 13 may deteriorate due to the intrusion of foreign substances. In particular, if the distance r between adjacent circuits 2 is large, the gaps 20 between the circuits 2 cannot be filled with the adhesive layer 3, which increases the occurrence of gaps 20. Therefore, in order to prevent the occurrence of the gap 20, the thickness of the adhesive layer 3 is set to a certain value, but when the thickness of the adhesive layer 3 is increased in this way, the adhesive resin of the adhesive layer 3 becomes thicker as shown in Figure 7. There is a risk that the wire may protrude and cover the inner lead portion 12 of the circuit 2, making it impossible to perform wire bonding 14 with the electronic component 13.The present invention has been made in view of the above points. To provide a multilayer plastic chip carrier which can be formed by stacking substrates 1 one above the other without the need to make the adhesive layer 3 thick and without fear of creating a gap between the adhesive 13 and the substrate 1. The purpose is to
【課・題を解決するための手段１
本発明は、上下複数枚の各基板１，１・・・に多数本の
回路２，２．・・・を設けると共に各基板１を接着ｆｆ
１３で積層接着することによって形成される多層プラス
チックチップキャリア八において、上下の基板１間に位
置する回路２の幅寸法を隣合う回路２の間隔の幅寸法よ
りも大きく形成して回路２の間隔を小さくし、この回路
２を覆うように基板１の表面に塗布した絶縁層４を介し
て接着層３によって各基板１を積層接着して成ることを
特徴とするものである。
【作 用］
本発明にあっては、回路２を覆うように基板１の表面に
絶縁層４を塗布することによって隣合う回路２間のギャ
ップを埋めることができ、待に回路２の幅寸法を隣合う
回路２の間隔の幅・寸法よりも大きく形成することで回
路２の間隔を小さくして、回路２間のギャップを絶縁層
４で確実に埋めることがでさ、基板１の表面を平滑な状
態にして接着／１３で基板１を積層接着することによっ
て密着性良く各基板１を積層することができる。
【実施例】
以下本発明を１図乃至第４図に示す実施例によって詳述
する。
基板１は銅張りエポキシ積層板など金属箔を張った樹脂
積層板等で形成されるものであり、金属箔をエツチング
加工などすることによって各基板１には多数本の回路２
が形成しである。ここで、基板１のうち多層プラスチッ
クチップキャリアＡの下層に位置する基板１ａの上面の
中央部にはキャビティ凹所１０が凹設してあって、この
基板１ａの上面に形成した内層用の回路２ａはキャビテ
ィ凹所１０を中心とする放射状のパターンで設けられて
いるものであり、第３図に示すように一方の端部はイン
ナーリード部１２としてキャビティ凹所１０に近接し、
他方の端部はスルーホール部１５を設けたランド１６と
して基板１ａの端部に近接している（第３図においては
回路２ａを基板１ａの一部においてのみ図示し、他の部
分は図示を省略している）。
そしてまず、この基板１ａの上面に絶縁層４を形成させ
る。絶縁層４はツルグーレノストなどを用いて形成する
ことがでさるものであり、液状のツルグーレノストを基
板１ａの上面に塗布して必要に応じて加熱して硬化させ
ることによって絶縁／１４を形成することができる。こ
のように絶縁層４を塗布して形成することによって、ｆ
ＩＳｉ図に示すように基板１ａの上面に形成した内層回
路２ａの隣合うものの間のギャップを絶縁層４で埋める
ことができ、基板１ａの上面を平滑にすることができる
。ここで、回路２ａ間の間隔が狭い程、回路２ａ間のギ
ャップは小さくなるため、絶縁層４によってギャップを
確実に埋めることができるものであり、回路２ａ開の開
隔ｌは２ｍｍ以下に設定するのがよい。銅箔などの金属
箔をエツチング加工等することによって基板１に回路２
を形成する場合、通常は信号線として必要な幅を残して
他の部分をエツチングすることによって回路２の形成を
おこなうが、本発明では回路２の幅を信号線として必要
な幅以上に広い幅で残してエツチングすることによって
、第４図に示すように回路２の幅を隣合う回路２間の間
隔よりも広く設定し、この結果隣合う回路２開の間隔を
２ｍｍ以下の狭い寸法に設定で慇るようにしである。間
隔を２ｍ＋ａ以下の狭い幅に設定するのは基板１に形成
する回路２の総てであってもよいが、少なくとも基板１
間に挟まれることになる内層回路２ａにおいてはこのよ
うに設定される。またできるだけ基板１の全面において
回路２の幅寸法を回路２の間隔寸法よりも広く設定する
ことが望ましく、インナーリード部１２に近い部分では
必ずこのことが必要であるが、もちろん基板１の全面に
おいてこのように要求されるものではなく、例えばスル
ーホールを形成した部分などでは回路２の幅寸法は回路
２間の間隔の幅寸法よりも小さく設定されることが多く
、基板１の８０％程度の面積において回路２の幅寸法を
回路２の間隔寸法よりも広く設定すればよい。
上記のように基板１ａの上面に絶ａ屑４を塗布して形成
したのち、この基板１ａの上に接着層３を介して開口１
１ＦＩｓＩＩを設けた基板１ｂを積層接着する。接着層
３は例えばポンディング用のプリプレグ（樹脂含浸乾燥
基材）によって形成することができ、プリプレグを上下
の基板１闇に挟み込んで加熱加圧成形することによって
、上下複数枚の基板１を接着層３で積層接着して第２図
に示すような多層プラスチックチップキャリアＡを得る
ことができるものである。基板１の表面は絶縁層４の塗
布で平滑になっているために、接着Ｍ３と基板１の表面
との間には隙間が生じるおそれはない。
またこのように接着層３と基板１との間に隙間が生じる
ことを防止できるために！１着層３として厚みの厚いも
のを用いる必要がなく、基板１ｂの開口ｇｉｉ内に突出
する内層回路２ａのインナーリード部１２が接着層３の
はみ出しで覆われてしまうようなおそれもない、尚、上
記第１図〜第４図の実施例では開口部１１を設けた基板
１ｂには内層回路２ａを形成していないが、第５図（ａ
）（ｂ）のように基板１ｂに内層回路２ａを形成した場
合にも本発明が適用されるのはいうまでもなく、このと
きは基板１ｂ側にも絶縁層４を塗布形成しておくもので
ある。[Means for solving problems 1] The present invention provides a plurality of circuits 2, 2, . ... and bond each substrate 1ff
In the multilayer plastic chip carrier 8 formed by laminating and bonding in step 13, the width of the circuit 2 located between the upper and lower substrates 1 is formed to be larger than the width of the interval between adjacent circuits 2 to increase the interval between the circuits 2. The circuit board 1 is characterized in that each board 1 is laminated and bonded by an adhesive layer 3 via an insulating layer 4 coated on the surface of the board 1 so as to cover the circuit 2. [Function] In the present invention, by applying the insulating layer 4 to the surface of the substrate 1 so as to cover the circuit 2, the gap between adjacent circuits 2 can be filled. It is possible to reduce the gap between the circuits 2 by making the width and size larger than the width and dimension of the gap between the adjacent circuits 2, and to reliably fill the gap between the circuits 2 with the insulating layer 4. By laminating and bonding the substrates 1 in a smooth state using adhesive/13, the substrates 1 can be laminated with good adhesion. EXAMPLES The present invention will be described in detail below with reference to examples shown in FIGS. 1 to 4. The board 1 is formed of a resin laminate covered with metal foil, such as a copper-clad epoxy laminate, and a large number of circuits 2 are formed on each board 1 by etching the metal foil.
is formed. Here, a cavity recess 10 is provided in the center of the upper surface of the substrate 1a located in the lower layer of the multilayer plastic chip carrier A in the substrate 1, and a cavity 10 is formed in the center of the upper surface of the substrate 1a, and a circuit for an inner layer formed on the upper surface of the substrate 1a. 2a is provided in a radial pattern centered on the cavity recess 10, and as shown in FIG. 3, one end is close to the cavity recess 10 as an inner lead part 12,
The other end is close to the end of the board 1a as a land 16 provided with a through-hole portion 15 (in FIG. 3, the circuit 2a is shown only in a part of the board 1a, and other parts are not shown). (omitted). First, an insulating layer 4 is formed on the upper surface of this substrate 1a. The insulating layer 4 can be formed using sulfur urethane or the like, and the insulation layer 14 can be formed by applying liquid sulfur urenost onto the upper surface of the substrate 1a and heating and curing it if necessary. can. By coating and forming the insulating layer 4 in this way, f
As shown in the ISi diagram, the gap between adjacent inner layer circuits 2a formed on the upper surface of the substrate 1a can be filled with the insulating layer 4, and the upper surface of the substrate 1a can be made smooth. Here, the narrower the interval between the circuits 2a, the smaller the gap between the circuits 2a, so the gap can be reliably filled with the insulating layer 4, and the gap l between the circuits 2a is set to 2 mm or less. It is better to do so. The circuit 2 is formed on the board 1 by etching a metal foil such as copper foil.
When forming the circuit 2, normally the width necessary for the signal line is left and the other parts are etched to form the circuit 2, but in the present invention, the width of the circuit 2 is made wider than the width necessary for the signal line. As shown in Figure 4, the width of the circuit 2 is set wider than the interval between adjacent circuits 2 by etching, and as a result, the interval between adjacent circuits 2 is set to a narrow dimension of 2 mm or less. It makes me feel comfortable. The interval may be set to a narrow width of 2m+a or less for all the circuits 2 formed on the substrate 1, but at least the circuit 2 formed on the substrate 1
The inner layer circuit 2a that will be sandwiched between them is set in this way. Furthermore, it is desirable to set the width of the circuit 2 to be wider than the interval between the circuits 2 over the entire surface of the board 1 as much as possible, and this is always necessary in the area close to the inner lead part 12, but of course, over the entire surface of the board 1 This is not required; for example, in areas where through-holes are formed, the width of the circuits 2 is often set smaller than the width of the interval between the circuits 2, and approximately 80% of the board 1 is The width dimension of the circuit 2 may be set wider than the interval dimension of the circuit 2 in terms of area. After coating the top surface of the substrate 1a with the abrasive material 4 as described above, an opening 1 is formed on the substrate 1a via the adhesive layer 3.
The substrates 1b provided with 1FIsII are laminated and bonded. The adhesive layer 3 can be formed, for example, from prepreg (resin-impregnated dry base material) for bonding, and by sandwiching the prepreg between the upper and lower substrates 1 and molding them under heat and pressure, the plurality of upper and lower substrates 1 are bonded together. By laminating and bonding layer 3, a multilayer plastic chip carrier A as shown in FIG. 2 can be obtained. Since the surface of the substrate 1 is smoothed by applying the insulating layer 4, there is no possibility that a gap will be formed between the adhesive M3 and the surface of the substrate 1. Also, it is possible to prevent a gap from forming between the adhesive layer 3 and the substrate 1 in this way! There is no need to use a thick one as the first layer 3, and there is no fear that the inner lead portion 12 of the inner layer circuit 2a protruding into the opening gii of the substrate 1b will be covered by the protruding adhesive layer 3. In the embodiments shown in FIGS. 1 to 4, the inner layer circuit 2a is not formed on the substrate 1b provided with the opening 11, but in the embodiment shown in FIG.
) It goes without saying that the present invention is also applied to the case where the inner layer circuit 2a is formed on the substrate 1b as in (b), and in this case, the insulating layer 4 is also applied and formed on the substrate 1b side. It is.
上述のように本発明にあっては、回路を覆うように基板
の表面に塗布した絶縁層を介して接着層によって各基板
を積層接着するようにしたので、回路を覆うように基板
の表面に絶縁層を塗布することによって隣合う回路間の
ギャップを埋めることができ、特に回路の幅寸法を隣合
う回路の間隔の幅寸法よりも大きく形成することで回路
の間隔を小さくしたので、回路間のギャップを絶縁層で
確実に埋めることができ、基板の表面を絶縁層で平滑な
状態にして接着層で基板を積／ｌ接着することができる
ものであり、接着層と基板との間に隙問が生じることな
く′ｆｉ着性良く各基板をＭｔｗＪすることがでさるも
のである。As described above, in the present invention, each board is laminated and bonded using an adhesive layer through an insulating layer applied to the surface of the board so as to cover the circuit. By applying an insulating layer, the gap between adjacent circuits can be filled.In particular, by forming the width of the circuit to be larger than the width of the gap between adjacent circuits, the gap between the circuits can be reduced. The gap between the adhesive layer and the substrate can be reliably filled with the insulating layer, the surface of the substrate can be smoothed with the insulating layer, and the substrate can be laminated/bonded with the adhesive layer. This makes it possible to MtwJ each substrate with good 'fi adhesion without creating any gaps.
第１図は第２図のイーイ線部分の拡大断面図、第２図は
本発明の一実施例の断面図、第３図は同上の基板の平面
図、第４図は基板の回路の一部の拡大図、ｔｐＪＳ図（
ａ）（ｂ）は多層プラスチックチップキャリアの断面図
、第６図（ａ）は従来例の一部の拡大断面図、第６図（
ｂ）は１６図（ａ）のローロ線部分の断面図、第７図は
他の従来例の一部の拡大断面図である。
１は基板、２は回路、３は接着層、４は絶縁層である。FIG. 1 is an enlarged sectional view of the E-II line in FIG. 2, FIG. 2 is a sectional view of an embodiment of the present invention, FIG. 3 is a plan view of the same board, and FIG. Enlarged view of section, tpJS diagram (
a) and (b) are cross-sectional views of a multilayer plastic chip carrier, FIG. 6(a) is an enlarged cross-sectional view of a part of the conventional example, and FIG.
b) is a cross-sectional view of the Rollo line portion of FIG. 16(a), and FIG. 7 is an enlarged cross-sectional view of a part of another conventional example. 1 is a substrate, 2 is a circuit, 3 is an adhesive layer, and 4 is an insulating layer.
Claims (2)
に各基板を接着層で積層接着することによって形成され
る多層プラスチックチップキャリアにおいて、上下の基
板問に位置する回路の幅寸法を隣合う回路の間隔の幅寸
法よりも大きく形成して回路の間隔を小さくし、この回
路を覆うように基板の表面に塗布した絶縁層を介して接
着層によって各基板を積層接着して成ることを特徴とす
る多層プラスチックチップキャリア。(1) In a multilayer plastic chip carrier formed by providing multiple circuits on each of upper and lower boards and laminating and bonding each board with an adhesive layer, the width dimension of the circuit located between the upper and lower boards is The spacing between the circuits is formed to be larger than the width of the spacing between the matching circuits, and the spacing between the circuits is reduced, and each substrate is laminated and bonded using an adhesive layer through an insulating layer coated on the surface of the substrate to cover the circuit. Features a multilayer plastic chip carrier.
ることを特徴とする請求項１記載の多層プラスチックチ
ップキャリア。(2) The multilayer plastic chip carrier according to claim 1, characterized in that the distance between adjacent circuits is formed to be 2 mm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230613A JPH0278253A (en) | 1988-09-14 | 1988-09-14 | Multilayer plastic chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230613A JPH0278253A (en) | 1988-09-14 | 1988-09-14 | Multilayer plastic chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0278253A true JPH0278253A (en) | 1990-03-19 |
| JPH0587181B2 JPH0587181B2 (en) | 1993-12-15 |
Family
ID=16910508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63230613A Granted JPH0278253A (en) | 1988-09-14 | 1988-09-14 | Multilayer plastic chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0278253A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072144A (en) * | 1989-07-15 | 1991-12-10 | Matsushita Electric Works, Ltd. | Moving-coil linear motor |
| US5477085A (en) * | 1993-11-26 | 1995-12-19 | Nec Corporation | Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits |
| US5531637A (en) * | 1993-05-14 | 1996-07-02 | Kabushiki Kaisha Nagao Kogyo | Automatic centrifugal fluidizing barrel processing apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5228547A (en) * | 1975-08-29 | 1977-03-03 | Kazuo Hara | Method for the coagulation of sodium alginate |
| JPS60107894A (en) * | 1983-11-17 | 1985-06-13 | 沖電気工業株式会社 | Method of producing multilayer printed circuit board |
| JPS61258457A (en) * | 1985-05-13 | 1986-11-15 | Nec Corp | Resin sealed type semiconductor device |
| JPS62192664U (en) * | 1986-01-18 | 1987-12-08 | ||
| JPS6338878A (en) * | 1986-07-31 | 1988-02-19 | 株式会社 ウロコ製作所 | Drier |
-
1988
- 1988-09-14 JP JP63230613A patent/JPH0278253A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5228547A (en) * | 1975-08-29 | 1977-03-03 | Kazuo Hara | Method for the coagulation of sodium alginate |
| JPS60107894A (en) * | 1983-11-17 | 1985-06-13 | 沖電気工業株式会社 | Method of producing multilayer printed circuit board |
| JPS61258457A (en) * | 1985-05-13 | 1986-11-15 | Nec Corp | Resin sealed type semiconductor device |
| JPS62192664U (en) * | 1986-01-18 | 1987-12-08 | ||
| JPS6338878A (en) * | 1986-07-31 | 1988-02-19 | 株式会社 ウロコ製作所 | Drier |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072144A (en) * | 1989-07-15 | 1991-12-10 | Matsushita Electric Works, Ltd. | Moving-coil linear motor |
| US5531637A (en) * | 1993-05-14 | 1996-07-02 | Kabushiki Kaisha Nagao Kogyo | Automatic centrifugal fluidizing barrel processing apparatus |
| US5477085A (en) * | 1993-11-26 | 1995-12-19 | Nec Corporation | Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0587181B2 (en) | 1993-12-15 |
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