JPS60107894A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS60107894A
JPS60107894A JP21509783A JP21509783A JPS60107894A JP S60107894 A JPS60107894 A JP S60107894A JP 21509783 A JP21509783 A JP 21509783A JP 21509783 A JP21509783 A JP 21509783A JP S60107894 A JPS60107894 A JP S60107894A
Authority
JP
Japan
Prior art keywords
multilayer printed
printed wiring
copper foil
copper
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21509783A
Other languages
Japanese (ja)
Inventor
下戸 敬二郎
和雄 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP21509783A priority Critical patent/JPS60107894A/en
Publication of JPS60107894A publication Critical patent/JPS60107894A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (技術分野) 本発明は内層・ぐターンを有する多層印刷配線板の製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a multilayer printed wiring board having inner layers and patterns.

(従来技術) 現在印刷配線基板に高密度実装が要求されるようになる
にしたがい、配線の密度を上げると同萌に内層の級を増
加することで、その要求に対応している。なお多層印刷
配線板の層数は現在8〜12層板が量産化されている状
態であるが今後、さらにその層数の増加が要求されるも
のと推定される。
(Prior Art) At present, as printed circuit boards are required to have high-density packaging, this demand is met by increasing the number of inner layers at the same time as increasing the wiring density. Although 8 to 12 layers of multilayer printed wiring boards are currently being mass-produced, it is estimated that an increase in the number of layers will be required in the future.

従来の多層印刷配線板の製造方法は第1図に示すように
複数の/IPターンを有する銅張積層板1と外層用銅箔
2をそれぞれ多層印刷配線板用接着基材(以下ゾリゾレ
グという)3を介し熱圧着し製造しているのが通常であ
る。これに用いられる材料の厚さは内層パターンの銅張
積層板lの絶縁層が0.1 mn以上、銅箔が0.03
5〜0.07tranであり、外層用銅箔2が0.00
9〜0.035調、ノリグレグ3は006〜0.2 t
tmを使用し、グレルグ3は1〜3枚を一緒に使用して
いる。
As shown in Fig. 1, the conventional method for producing a multilayer printed wiring board is to use a copper-clad laminate 1 having a plurality of /IP turns and a copper foil 2 for the outer layer as adhesive base materials for multilayer printed wiring boards (hereinafter referred to as ZOLIZOLEG). It is usually manufactured by thermocompression bonding through 3. The thickness of the materials used for this is 0.1 mm or more for the insulating layer of the copper-clad laminate l of the inner layer pattern, and 0.03 mm for the copper foil.
5 to 0.07 tran, and the outer layer copper foil 2 is 0.00
9~0.035 tone, Norigreg 3 is 006~0.2t
tm is used, and 1 to 3 of Grerug 3 are used together.

このように熱圧着してできる多層板は8〜12層板では
板厚が2.4miが平均的であシ、14層以上では約3
m+程度になる。さらに暦数が増えるに従って板厚はよ
シ厚くなる。このように板厚が厚くなるのは銅張積層板
1の増加分に対しては止むを得ないが、問題はゾレルグ
3の増加である。
The average thickness of multilayer boards made by thermocompression bonding is 2.4mm for 8 to 12 layers, and about 3mm for 14 or more layers.
It will be about m+. Furthermore, as the number of calendars increases, the thickness of the plate becomes thicker. This increase in thickness is unavoidable due to the increase in the number of copper-clad laminates 1, but the problem is the increase in the number of ZOLLEGs 3.

即チソレゾレグ3は被接着面のパターンの形状で異なり
、銅箔が厚く、パターンに々って残る銅の面積が少ない
程グレゾレグ3を薄く、枚数を増す必要がある。これは
グリシレグ3に含まれる樹脂分子 d’ ターン以外の
エツチングされた部分を埋めるだめである。このように
プレプレグ3の厚みは接する面の銅箔の状態で決まるだ
め自由寿厚みを選択することが不可能となり、止むを得
ず厚さが増加することである。そのことは多層印刷配線
板の中層とスルーホールめっきとの接続性やスルーポー
ルのめっきの信頼性は板厚によるところが大きく、板厚
が厚くなるに従って絶縁材料とスルホール銅めっきの膨
張係数の差による伸縮の絶対値が大きくなるため信頼性
が劣るという欠点がある。
That is, the Chisolesleg 3 differs depending on the shape of the pattern on the surface to be adhered, and the thicker the copper foil and the smaller the area of copper remaining along the pattern, the thinner the Gresoleg 3 and the need to increase the number of sheets. This is to fill in the etched portions other than the d' turns of the resin molecules contained in Glycyleg 3. In this way, the thickness of the prepreg 3 is determined by the state of the copper foil on the contacting surface, so it is impossible to select the free life thickness, and the thickness is unavoidably increased. This means that the connectivity between the middle layer of a multilayer printed wiring board and through-hole plating and the reliability of through-hole plating largely depend on the board thickness, and as the board thickness increases, the difference in expansion coefficient between the insulating material and the through-hole copper plating increases. There is a drawback that reliability is poor because the absolute value of expansion and contraction becomes large.

(発明の目的) 本発明は上記欠点を解決したもので、多層印刷配線板の
板厚を薄く作ることにより信頼性が従来法より優れ/こ
新規な加工方法を提供するものである。
(Objective of the Invention) The present invention solves the above-mentioned drawbacks and provides a novel processing method that is superior in reliability to conventional methods by making a multilayer printed wiring board thinner.

(発明の構成) このl]的のだめ本発明はパターンを形成した以外の部
分に絶縁性樹脂を塗布してパターンの銅箔の凹凸を少な
りシ、グリシレグによる樹脂分で四部を殆んど埋める必
要をなくして、予めシリプレグを任意の厚さに選べるよ
うにしたものである。
(Structure of the Invention) The present invention applies insulating resin to the parts other than where the pattern is formed to slightly reduce the unevenness of the copper foil of the pattern, and fills most of the four parts with the resin from Grishireg. This eliminates the need for silipregs and allows you to select any desired thickness of silicone preg in advance.

(実施例) 次に、本発明の実施例を図面により詳細に説明する。第
2図(a)〜(Q)は本発明製造方法の各工程を示す説
明図で、図に示すようにはじめに、絶縁層1bの表裏に
銅箔1aを設けた銅張積層板1に導体・クターンのみを
フォトレジスト11で被覆しく(a)図)、銅箔エツチ
ング液、例えば塩化第2鉄水溶液(比重40°Be)の
40℃でスプレーエツチングして・やターン以外の銅箔
1cを除去するC (b)図)。次に7オトレジスト1
1を前1114洗浄する((C)図)。次に絶縁性樹脂
12、例えばツルグーレジストインキをカーテンコータ
ーのような塗布装置を用いてできるかぎシ・クターン以
外の凹部に塗布し、乾燥機で約130℃、時間30分処
理する((d)図)。以上のようにしてできた中層板を
(e)図の様にシリプレグ3を介して必要枚数(約1枚
)重ね、1だ最外層に銅箔2を重ね、熱圧着する。
(Example) Next, an example of the present invention will be described in detail with reference to the drawings. FIGS. 2(a) to (Q) are explanatory diagrams showing each step of the manufacturing method of the present invention. As shown in the figures, first, a conductor is placed on a copper-clad laminate 1 in which copper foil 1a is provided on the front and back sides of an insulating layer 1b.・Coat only the pattern with photoresist 11 (Figure (a)), and spray-etch it at 40°C with a copper foil etching solution, such as a ferric chloride aqueous solution (specific gravity 40°Be). Remove C (Figure b)). Next 7 otoresist 1
1 before washing 1114 ((C) figure). Next, the insulating resin 12, for example, Tsurugo resist ink, is applied to the recesses other than the key marks using a coating device such as a curtain coater, and then treated in a dryer at approximately 130°C for 30 minutes ((d) )figure). As shown in Fig. 3(e), the required number of middle layer plates (approximately 1 plate) are stacked with silicon preg 3 interposed between them, and the copper foil 2 is stacked on the outermost layer, followed by thermocompression bonding.

このようにして本発明による多層印刷配線板が得られる
In this way, a multilayer printed wiring board according to the invention is obtained.

(発明の効果) このように本発明によれば、前述した従来例と対比して
、グリシレグの枚数を従来2枚以上使用1−でいたもの
が1枚でも可能となり、最終的に仕」二る多層印刷配線
板の板厚が薄く作ることができる。特に10層以上の多
層印刷配線板に効果が−大きく、印刷配線板に要求され
る強度的な点を満足する最少の板厚で多層印刷配線板を
作ることができる。従って中層銅箔との接続性が良くな
ると同時に、従来より軽いものができる等の効果がある
(Effects of the Invention) According to the present invention, in contrast to the conventional example described above, it is now possible to reduce the number of grid legs to one instead of the conventional method of using two or more. Multilayer printed wiring boards can be made thinner. The effect is particularly great for multilayer printed wiring boards with 10 or more layers, and multilayer printed wiring boards can be made with the minimum thickness that satisfies the strength requirements of printed wiring boards. Therefore, the connectivity with the middle layer copper foil is improved, and at the same time, it is possible to manufacture a product that is lighter than before.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多層印刷配線板の製造方法を示す説明図
、第2図(a)〜(e)は本発明多層印刷配線板の製造
方法の一実施例を示す説明図である。 ノ・・・銅張積層板、1a・・りぐターン部の銅箔、1
1〕・・・絶縁層、2・・・最外層の銅箔、3・・プリ
プレグ、1ノ・・フォトレジスト、12・・・絶縁性樹
脂。 第2図 ″−2
FIG. 1 is an explanatory diagram showing a conventional method for manufacturing a multilayer printed wiring board, and FIGS. 2(a) to (e) are explanatory diagrams showing an embodiment of the method for manufacturing a multilayer printed wiring board of the present invention. No...Copper-clad laminate, 1a...Copper foil on the rig turn part, 1
1]... Insulating layer, 2... Outermost copper foil, 3... Prepreg, 1... Photoresist, 12... Insulating resin. Figure 2''-2

Claims (1)

【特許請求の範囲】[Claims] 銅張積層板の銅箔に所望のパターンをエツチングで形成
し、これらに多層印刷配線板用接着基材を介し、かつ最
外層に銅箔を重ね合せ熱圧着して多層印刷配線板を成形
する工程において、所望のパターンを形成した銅張積層
板のエツチングで除かれた部分並びにエツチングされな
い銅箔部に絶縁性材料を塗布する工程を設けたことを特
徴とする多層印刷配線板の製造方法。
A desired pattern is formed on the copper foil of the copper-clad laminate by etching, and the copper foil is superimposed on the outermost layer via an adhesive base material for multilayer printed wiring boards and bonded under heat to form a multilayer printed wiring board. A method for manufacturing a multilayer printed wiring board, comprising the step of applying an insulating material to the etched portions of the copper-clad laminate having a desired pattern formed thereon, as well as to the copper foil portions that are not etched.
JP21509783A 1983-11-17 1983-11-17 Method of producing multilayer printed circuit board Pending JPS60107894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21509783A JPS60107894A (en) 1983-11-17 1983-11-17 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21509783A JPS60107894A (en) 1983-11-17 1983-11-17 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS60107894A true JPS60107894A (en) 1985-06-13

Family

ID=16666699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21509783A Pending JPS60107894A (en) 1983-11-17 1983-11-17 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60107894A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62285498A (en) * 1986-06-03 1987-12-11 松下電工株式会社 Multilayer printed interconnection board
JPS6324695A (en) * 1986-07-17 1988-02-02 東芝ケミカル株式会社 Manufacture of multilayer interconnection board
JPH0278253A (en) * 1988-09-14 1990-03-19 Matsushita Electric Works Ltd Multilayer plastic chip carrier

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62285498A (en) * 1986-06-03 1987-12-11 松下電工株式会社 Multilayer printed interconnection board
JPS6324695A (en) * 1986-07-17 1988-02-02 東芝ケミカル株式会社 Manufacture of multilayer interconnection board
JPH0278253A (en) * 1988-09-14 1990-03-19 Matsushita Electric Works Ltd Multilayer plastic chip carrier
JPH0587181B2 (en) * 1988-09-14 1993-12-15 Matsushita Electric Works Ltd

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