JPH10126058A - Manufacture of multilayered printed interconnection board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the surface smoothness of a multilayered printed interconnection board by increasing the adhesion of a circuit pattern on the surface of the wiring board by thermocompression bonding one-sided copper-plated insulating layers to both surfaces of a laminated intermediate body and forming via holes through the insulating layers, and then, plating the upper surface of copper foil and internal surfaces of the via holes with copper and forming outermost-layer circuit patterns on the plated copper layers. SOLUTION: After insulating layers 14 and 14 are again formed on both surfaces of the core material 10 of a laminated intermediate body and via holes 16 and 16 are formed through the layers 14 and 14, via holes 20 are formed by forming plated copper layers 18 and 18 on the surfaces of the insulating layers 14 and 14 and circuit patterns 24 are formed on the layers 18 and 18. By repeating the above-mentioned operations, a laminated intermediate body 72 composed of five layers is obtained. Copper-plated laminated boards 76 carrying copper soil 74 stuck to one surface are thermocompression bonded to both surfaces of the intermediate body 72 and outermost layers with an adhesive and circuit patterns 80 and via holes 82 are formed on the boards 72 after forming via holes 78. Since the laminated board 76 are pressed against the intermediate body 72 and heated by holding the boards 76 between the heating boards of a press machine at the time of thermocompression bonding the boards 76 to the intermediate body 72, the surface smoothness of a multilayered printed interconnection board can be improved by increasing the adhesion of the circuit pattern on the surface of the board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board by a build-up method.

[0002]

2. Description of the Related Art A build-up method is conventionally known. This build-up method is a method in which an insulating layer and a conductor layer are alternately stacked on an inner core material on which a circuit pattern is formed, and when a circuit pattern is formed on each layer of the conductor layer, To form a via hole that establishes conduction.

[0003] The build-up method includes a resin coating method in which an insulating layer is formed by an insulating resin coat and a laminating method in which a copper foil-clad insulating plate is laminated. Both of these methods will be described with reference to FIGS. 2 and 3, respectively.

FIG. 2 is a process explanatory view showing a resin coating method. The step (A) in FIG. 2 is a step of preparing the inner layer core material 10, and circuit patterns 12, 12 are formed on both surfaces of the core material 10. On the core material 10, a sheet (prepreg) obtained by impregnating a resin such as paper or glass with a base material, for example, is laminated, and a copper-clad laminate is formed by applying a copper foil to an insulating plate made by applying pressure and heat. Used. A circuit pattern is formed on the copper foil of the copper-clad laminate by known photoetching.

[0005] Both surfaces of the core material 10 are coated with an insulating resin by a method such as curtain coating or printing. With this coating, the insulating layers 14 can be formed (step (B) in FIG. 2).

The insulating layers 14 and 14 have via hole holes 1
6 and 16 are processed (step (C) in FIG. 2). For this processing, various methods such as a photo method, a laser method, a drill method, and a honing method can be used. In the photo method, a photosensitive ink is used as an insulating resin used to form the insulating layer 14 in the step (B), and a pattern including the positions of the via holes is exposed to cure the ink other than the via hole holes 16. . Thereafter, the via-hole 16 is formed by washing and removing the uncured resin at the position corresponding to the via-hole.

In the laser method, a laser beam is applied to the position of the via hole 16 to make a hole. When the laser beam reaches the lower circuit pattern 12, it does not enter any more. Therefore, the via hole 16 having a depth reaching the circuit pattern 12 can be formed accurately.

[0008] The drilling method uses a drill that rotates at a high speed and the insulating layer 1
4 is to machine the via hole 16 directly.
In the honing method, a protective sheet having small holes at the positions of the via holes 16 is attached to the surface of the insulating layer 14, and a liquid or air containing an abrasive is blown from above to form the via holes 16.

After forming the via hole 16, the surface of the insulating layer 14 is plated with copper. (Step (D) in FIG. 2). A part of the copper plating layers 18 is formed on the inner surface of the via hole 16 to form the via hole 20. In order to form the copper plating layer 18, electroless plating is performed on the surface of the insulating layer 14 to impart conductivity to the surface, and then electrolytic copper plating is performed.

A circuit pattern 24 is formed on the copper plating layer 18 using a photosensitive resist 22 (see steps (D) and (E) in FIG. 2). That is, a dry film made of a photosensitive resin sheet is thermocompression-bonded on the copper plating layer 18, a pattern having the same shape as the circuit pattern 24 is baked by ultraviolet exposure, and developed to leave the resist 22 in the same pattern as the circuit pattern 24. Then, unnecessary portions of the copper plating layer 18 are removed by etching the surface, and a circuit pattern 24 is formed. As a result, the circuit pattern 12 on the lower layer and the circuit pattern 24 on the surface layer are electrically connected by the via hole 20.

By repeating the processing in the same step as steps (B) to (E) twice on the laminate 26 formed in step (E), a seven-layer multilayer print shown in FIG. The wiring board 28 is completed.

Next, the lamination method will be described with reference to FIG. FIG.
FIG. 2 is a process explanatory view of this method. The step (A) is a step of preparing the inner layer core material 10 on which the circuit pattern 12 is formed, and is the same as the step (A) in FIG. This core material 1
A single-sided copper-clad laminate 50 is laminated on the surface of No. 0.
Step (B)).

The laminate 50 is formed by pressing a prepreg obtained by impregnating paper or glass with a resin in the same manner as the core material 10.
An insulating plate cured by heating is prepared, and a copper foil 52 is provided on one side thereof. Via holes 54 are formed in the laminate 50 (step (C) in FIG. 3).

As a method of forming the via hole hole 54, a method can be used in which a hole is formed in the copper foil 52 by etching, and a hole is formed in the insulating plate below the hole by a laser beam. Further, a drilling method of mechanically processing with a drill, a chemical milling method of making a hole in the copper foil 52 with a drill, and making a hole in an insulating plate thereunder by etching with a chemical solvent, and the like can be used.

After the formation of the via hole 54, copper plating is applied to the surface and the inner surface of the via hole 54 (step (D) in FIG. 3). This copper plating layer 56 can be formed by performing electroless copper plating after electroless copper plating as in the step (D) in FIG.

A circuit pattern 60 is formed on the copper plating layer 56 using a photosensitive resist 58 (see steps (D, E) in FIG. 3).

That is, as described in the steps (D, E) in FIG. 2, the dry film is thermocompression-bonded, and a pattern having the same shape as the circuit pattern 60 is baked by ultraviolet exposure.
The development is performed to leave the resist 58 in the same shape as the circuit pattern 60, and to remove unnecessary portions between the copper plating layer 56 and the copper foil 52.

As a result, the circuit pattern 60 in the upper layer is connected to the circuit pattern 12 in the lower layer by a via hole 62. By repeating steps (B) to (E) on this, a laminate 64 is completed (step (F) in FIG. 3).

[0019]

2. Problem of the Prior Art The resin coating method shown in FIG. 2 has the advantage that the manufacturing is easy and inexpensive because each insulating layer 14 is formed of a resin coating layer. However, this resin coating layer has a weak adhesion to the circuit patterns 12 and 24 made of a copper plating layer, and is at most 1 kg /
Only about cm ² can be obtained.

For this reason, the insulating layer 14 is
24, especially the outermost circuit pattern 24A
When the soldering operation is repeated (see FIG. 2 (F)), the circuit pattern 24A may be peeled off, resulting in a fatal defect. Therefore, there is a problem that parts cannot be replaced (repairability is poor).

In addition to the large number of via holes 20 formed on the surface, the insulating layer 14 on the inner via hole 20 is slightly depressed at the portion of the via hole 20 therebelow, so that the surface smoothness (coplanarity) is reduced. ) Gets worse. For this reason, for example, there is a problem that the reliability when mounting an LSI or HIC (hybrid IC) having a connection terminal of a BGA (ball grid array) is reduced.

On the other hand, in the lamination method shown in FIG. 3, the insulating layer is formed of a resin plate of the copper-clad laminate 50, and the circuit pattern 60A on the surface (see step (F) in FIG. 3) is a prepreg and the lower insulating layer. Is bonded to the insulating layer and the circuit pattern 60A.
Adhesion with the substrate becomes sufficiently large. Therefore, the circuit pattern 60A does not come off even if soldering is repeated. Further, when the copper-clad laminate 50 is laminated, the whole is heated and pressed, so that the surface smoothness is improved.

However, this laminating method has a problem that it takes a long time to perform hot pressing a plurality of times. That is, it takes about 1.5 hours even if only one heat press is performed. Therefore, if this heat press is repeated a plurality of times, the productivity becomes extremely poor.

[0024]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a multilayer printed wiring board which can solve both the problems of the resin coating method and the lamination method. I do. That is, a multilayer printed wiring board that can improve the repairability by increasing the adhesion of the circuit pattern on the surface, improve the smoothness of the surface, improve the soldering reliability at the time of component mounting, and further improve the productivity. It is an object of the present invention to provide a method for producing the same.

[0025]

According to the present invention, there is provided a method for manufacturing a multilayer printed wiring board by a build-up method.
(A) Prepare an inner layer core material on which a circuit pattern is formed,
(B) forming an insulating layer with an insulating resin coat on the inner core material; (c) forming a via hole in the insulating layer;
(D) a plating layer is formed on the surface of the insulating layer and the inner surface of the via hole; (e) a circuit pattern is formed on the plating layer; and (f) the steps (b) to (e) are repeated to form a laminated intermediate. (G) A single-sided copper-foiled insulating plate is thermocompression-bonded on the laminated intermediate, (h) A via hole is formed in the copper-foiled insulating plate, and (i) Copper plating is applied to the upper surface of the copper foil and the inner surface of the via hole. And (j) forming an outermost circuit pattern on the copper plating layer.

[0026]

FIG. 1 is a process diagram of one embodiment of the present invention. In FIG. 1, steps (A) to (E) show the resin coating method, and correspond to steps (A) to (E) in FIG. Therefore, in steps (A) to (E) of FIG. 1, the same portions as those of FIG. 2 are denoted by the same reference numerals, and description thereof will not be repeated.

In the step (E), the three-layered intermediate body 70 obtained in the preceding step (D) is again subjected to the steps (B) to
By repeating the step of (D), a five-layered laminated body 72 is obtained. The outermost layers are laminated on both surfaces of the laminated intermediate 72 by the lamination method shown in FIG.

That is, the outermost layer is formed by thermocompression bonding a copper-clad laminate 76 having a copper foil 74 on one side to a laminate intermediate 72 with a prepreg or an adhesive (step (F) in FIG. 1), drilling or laser processing. Via hole processing, etc.
8 (step (G) in FIG. 1), and a circuit pattern 80 and a via hole 82 are formed (step (H) in FIG. 1). Steps (F) to (H) correspond to steps (B) to (E) shown in FIG. 3, and therefore, detailed description thereof will not be repeated.

According to this embodiment, when the laminated plate 76 is thermocompression-bonded in the step (F), the laminated plate 76 is sandwiched between hot plates of a press machine and pressurized and heated. Therefore, the smoothness of the laminate 84 as a product is good, and the parallelism of both surfaces is good. Further, since the heating press step by this press machine is performed only once in the last laminating step (F), the time required for the production is slightly increased as compared with the conventional resin coating method. It can be greatly reduced compared to the lamination method.

In the embodiment shown in FIG.
Although a plurality of insulating layers 14 and one laminated plate 76 are laminated on both surfaces of the present invention, the present invention can also be applied to a laminate laminated on only one surface, and includes this. As the outermost copper-clad laminate 76, a laminate having an adhesive ability, for example, a no-flow prepreg with a copper foil (a prepreg having no fluidity on one side of a copper foil and further coated with an adhesive) is used. Alternatively, a copper foil with resin (a copper foil coated with a resin on one side) may be used. In short, any structure may be used as long as it is laminated by pressing with a hot press.

[0031]

According to the first aspect of the present invention, as described above, the outermost layer is formed by the laminating method on the laminated intermediate produced by the resin coating method, so that the adhesion of the circuit pattern of the outermost layer is improved. This makes it possible to replace components by soldering (to improve repairability), improve the smoothness of the surface, improve the reliability of component mounting, and increase productivity.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of the present invention.

FIG. 2 is a process explanatory view of a conventional method.

FIG. 3 is a process explanatory view of a conventional method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 core material 12 circuit pattern 14 insulating layer 16 via hole hole 20 via hole 24, 24 circuit pattern 72 laminated intermediate 74 copper foil 76 laminated plate 78 via hole hole 80 circuit pattern 82 via hole

Claims (1)

[Claims] In a method for manufacturing a multilayer printed wiring board by a build-up method, (a) an inner core material having a circuit pattern is prepared, and (b) an insulating layer is formed on the inner core material by an insulating resin coat. (C) forming a via hole in the insulating layer; (d) applying a plating layer to the surface of the insulating layer and the inner surface of the via hole; (e) forming a circuit pattern in the plating layer; )-(E) are repeated to form a laminated intermediate, (g) a single-sided copper-foiled insulating plate is thermocompression-bonded on the laminated intermediate, and (h) via holes are formed in the copper-foiled insulating plate. And (i) applying copper plating to the upper surface of the copper foil and the inner surface of the via hole, and (j) forming an outermost layer circuit pattern on the copper plating layer.