JP3645780B2 - Build-up multilayer printed wiring board and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer printed wiring board and a manufacturing method thereof, and more particularly to a build-up multilayer printed wiring board with improved wiring efficiency formed by building up an insulating resin and a conductive layer on the surface of a core substrate and a manufacturing method thereof. It is.
[0002]
[Prior art]
A multilayer printed wiring board formed by alternately stacking insulating resin layers and wiring layers on a core substrate is a so-called build-up multilayer printed wiring board that has been put to practical use as a high-density mounting substrate because a fine wiring pattern can be formed. Use is expanding.
[0003]
A method for manufacturing a build-up multilayer printed wiring board is disclosed in Japanese Patent Application Laid-Open No. 10-341077 (referred to as the first prior art). In this technique, after panel plating is performed on a double-sided copper-clad laminate with through holes, the through holes are filled with an insulating resin layer, and then patterned to form first via holes and wiring patterns with lands that pass therethrough. A core substrate is manufactured. After forming the build-up insulating layer on the core substrate, a hole penetrating the land of the first via hole is formed in the insulating layer, and the entire surface is plated. Next, a second via hole connected to the upper wiring pattern and the land of the first via hole is formed by etching. The build-up insulating layers and the wiring patterns (including via holes) are alternately formed to manufacture a multilayer printed wiring board having a predetermined number of layers.
[0004]
[Problems to be solved by the invention]
However, the first conventional technique has the following problems.
(1) Since an insulating resin layer is formed on the inner surface of the through via hole (first via hole) of the core substrate, a micro via hole (second via hole) cannot be formed directly on the inner surface. Therefore, a micro via hole (second via hole) for connecting to the upper wiring pattern is connected to the land of the first via hole. Therefore, the area required for wiring increases and wiring efficiency deteriorates.
(2) A process of filling the first via hole of the core substrate with the insulating resin layer is necessary, and the manufacturing cost increases.
[0005]
Methods for solving the above-mentioned problems of the prior art are disclosed in JP-A-11-40949, (referred to as the second prior art), JP-A-274730 (referred to as the third prior art), and the like. .
[0006]
In the second prior art described above, after filling the through via hole of the core substrate with a conductive material and planarizing the surface, the micro via hole connected to the through via hole is formed on the build-up insulating layer immediately above the through via hole. Form.
[0007]
In the third prior art, the insulating resin layer is filled in the through via hole of the core substrate and the surface thereof is flattened, and then the insulating resin layer on the surface of the through via hole is etched away to a predetermined depth. Next, after filling the recess from which the insulating resin layer has been removed by etching with a conductive paste and planarizing it, a micro via hole connected to the through via hole is formed in the build-up insulating layer immediately above the through via hole.
[0008]
In these conventional technologies, a conductive material such as a conductive paste that is conducted to the land of the through via hole is formed on the surface of the through via hole of the core substrate, and a micro via hole that is connected to the through via hole of the core substrate is formed immediately above the through via hole. Although there is an effect of improving the wiring efficiency, there is a problem that the connection reliability between the micro via hole and the conductive material such as the conductive paste is lowered in a high temperature atmosphere such as soldering. The same man-hours for filling the conductive material into the through via hole as in the prior art are necessary, and there is a problem of an increase in manufacturing cost.
[0009]
Accordingly, an object of the present invention is to provide a build-up multilayer printed wiring and a method for manufacturing the same, which solve the above-mentioned problems of the prior art.
[0010]
[Means for Solving the Problems]
The build-up multilayer printed wiring board having the first configuration according to the present invention is laminated via a first insulating layer, and the outer layer side of the through hole filled with the first insulating layer is blocked with a pad. and the two core substrate at least having a blind via hole formed in the electrically connecting layers of the core substrate laminated two core substrate was through, the second insulation therein a base through hole in which a layer is filled, a third insulating layer formed on the laminated surface of the two core substrate, provided on the third insulating layer directly above the blind via the The opening of the blind via hole reaching the pad includes a micro via hole formed by plating.
[0011]
In the first configuration, one or more conductive layers may be further interposed between the two core substrates.
[0012]
Further, the build-up multilayer printed wiring board having the first configuration described above may have a configuration in which one or more fourth insulating layers and conductive layers are alternately formed on at least one surface thereof.
[0013]
The manufacturing method of the buildup multilayer printed wiring board of the 2nd structure of this invention WHEREIN: The process of forming a 1st plating layer in the whole surface of the drilled double-sided copper clad laminated board, The said 1st one side of the said laminated board Patterning the plating layer to form first and second core substrates having first through holes, and the first and second cores via a first insulating resin having adhesiveness When the surface of the substrate and the patterned inwardly to form an inner layer substrate was thermally bonded and filling together said first through hole in said first of said first and second core substrate by an insulating resin, wherein Forming a hole penetrating the inner layer substrate, and forming a second plating layer on the entire surface of the inner layer substrate including the hole, and then patterning the second plating layer to form a surface of the first through hole The second plating Forming a base through hole with said second plated layer and the brightest emission de via hole having occluded pad into the hole, a step of filling the base through hole in the second insulating layer, the inner layer on the substrate Forming a third insulating layer, and forming a third plating layer on the surface of the third insulating layer including the opening after forming an opening reaching the pad in the third insulating layer. And patterning the third plating layer to form a micro via hole electrically connected to the pad in the opening.
[0014]
In the second configuration, the third insulating tree layer is formed of a thermosetting resin or a light / thermosetting resin, and when a thermosetting resin is used for the third insulating resin layer, A catalyst for electroless plating can also be dispersed in the resin. The micro via hole can be formed on the blind via hole by an additive method by dispersing the electroless plating catalyst in the third insulating resin layer.
[0015]
In the second configuration, when the inner layer substrate is formed by thermally bonding the first and second core substrates with the patterned surfaces inside through the first insulating resin having adhesiveness, A third core substrate having one or more conductive layers is further disposed between the first and second core substrates, and the first, third, and second core substrates are interposed via the first insulating resin. Can be thermally bonded to form an inner layer substrate. In addition, one or more conductive layers made of the fourth insulating layer and the fourth plating layer may be alternately formed on the third insulating layer including the patterned third plating layer.
[0016]
In the present invention, the blind via hole of the inner layer substrate is closed with the pad formed by plating, and the micro via hole can be directly formed thereon, so that a build-up multilayer printed wiring board with improved wiring accommodation can be provided.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a build-up multilayer printed wiring board according to the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 1 is a cross-sectional view of an essential part of a substrate for explaining a first embodiment of a build-up multilayer printed wiring board according to the present invention. Referring to FIG. 1, the build-up multilayer printed wiring board includes two core substrates 21 and 22 each having at least a blind via hole laminated with an insulating layer 23 and closed on one side by a pad 2a, The buildup insulating layer 25 formed on the surface of 22 and the stacked core substrates 21 and 22 are penetrated, the layers between the core substrates 21 and 22 are electrically connected, and the buildup insulating layer 25 is filled therein. The base through via hole 3 is formed, and the build-up insulating layer 25 immediately above the blind via hole 2 includes the micro via hole 1 formed by plating in the opening reaching the pad 2a of the blind via hole 2.
[0019]
As the insulating layer 23, a thermosetting epoxy resin, a polyimide resin, or the like can be used. A glass epoxy resin substrate or a glass polyimide resin substrate can be used as the base material of the core substrate. The insulating layer 23 is formed by placing the core substrates 21 and 22 on both sides of a resin sheet made of a semi-cured thermosetting epoxy resin, polyimide resin, or the like called a prepreg and laminating them by hot pressing. The interior of the blind via hole 2 is also filled with the insulating layer that has melted and flowed in in this lamination process. An epoxy resin can be used as the build-up insulating layer.
[0020]
Next, a manufacturing method of the build-up multilayer printed wiring board according to the first embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view of the main part of the substrate for explaining the process sequence of the method for manufacturing the build-up multilayer printed wiring board of FIG. FIG. 3 is a cross-sectional view of the main part of the substrate for explaining the process sequence subsequent to FIG.
[0021]
First, a copper-clad laminate (reinforced with glass fiber) such as epoxy insulating resin is drilled, and a plating operation such as panel electrolytic copper plating or pattern electrolytic copper plating is performed. 12, 13, and 14 are formed. A through hole 10 is formed in the hole.
[0022]
Thereafter, a conductive pattern is formed on the laminated surface (surface on the inner layer side) of the copper-clad laminate by exposure, development, and etching operations to manufacture core substrates 21 and 22.
[0023]
Next, a semi-cured prepreg made of an epoxy resin or the like is sandwiched between two similarly manufactured core substrates 21 and 22, and the core substrates 21 and 22 are laminated by a laminating press (FIG. 2B). The prepreg is melted and filled into the through holes 10 of the core substrates 21 and 22. Reference numeral 23 denotes an insulating layer formed by melting and curing the prepreg. The insulating layer blown over the through holes 10 of the core substrates 21 and 22 is removed by polishing and flattened.
[0024]
Next, after the hole 5 penetrating the laminated core substrates 21 and 22 is opened, a plating operation of copper or the like is performed to form the second plating layers 15 and 16. At this time, the surface on the outer layer surface side of the through hole 10 is closed with the second plating layers 15 and 16. By this plating operation, the second plating layer is also formed on the wall of the hole 5.
[0025]
Next, the second plating layers 15 and 16 on the outer layer surface side of the core substrates 21 and 22 are patterned by a photolithography technique to form a conductive pattern. In this step, the base via hole 3 is formed to connect the blind via hole 2 having a structure in which the surface of the through hole is blocked with the pad 2a and the layer between the core substrates 21 and 22 (FIG. 2C).
[0026]
Next, a thermosetting liquid resin made of an epoxy resin as an undercoat material is applied to the surfaces of the core substrates 21 and 22 by screen printing or the like to fill the pattern gaps on the surfaces of the core substrates 21 and 22 and at the same time, the base through via hole 3 Is filled with a thermosetting liquid resin and thermoset. Thereafter, the surface of the core substrates 21 and 22 is coated with a thermosetting resin made of an epoxy resin on the copper foil 24 and a resin-coated copper foil in a semi-cured state is thermocompression-bonded with a laminating press or a roll laminator, and the whole is thermoset. (FIG. 3A). The code | symbol 25 of Fig.3 (a) shows the buildup insulating layer which has thermosetting resin of the copper foil with resin as a main component.
[0027]
Next, after removing the copper foil 24 in a portion where the micro via hole 1 is to be formed by exposure, development, and etching, a hole reaching the pad 2a is formed by laser processing. Thereafter, a plating operation is performed to form third plating layers 17 and 18. In addition, a panel plating method or a pattern plating method can be used for the plating operation.
[0028]
Thereafter, an outer layer conductive pattern is formed by performing exposure, development, and etching operations. In this step, the micro via hole 1 directly connected to the pad 2a of the blind via hole 2 is formed (FIG. 3B).
[0029]
In the step of FIG. 3 (a), the base through via hole 3 is filled with a thermosetting liquid resin and thermally cured, and then the resin-coated copper foil is heated on the surfaces of the core substrates 21 and 22 with a laminating press or a roll laminator. However, the build-up insulating layer 25 may be formed of a light or thermosetting resin such as a liquid or film epoxy resin or a thermosetting resin instead of the copper foil with resin.
[0030]
When a photo / thermosetting resin is used, an opening reaching the pad 2a can be formed in the buildup insulating layer 25 by laser drilling or photolithography.
[0031]
When a thermosetting resin is used, an opening reaching the pad 2a can be formed in the buildup insulating layer 25 by laser drilling. Moreover, when using a thermosetting resin, the electroless-plating catalyst can be disperse | distributed in resin, and an outer-layer conductive pattern (a micro via hole containing) can be formed by a full additive method.
[0032]
Next, a second embodiment of the build-up multilayer printed wiring board according to the present invention will be described in detail with reference to the drawings.
[0033]
FIG. 4 is a cross-sectional view of a principal part of a substrate showing a second embodiment of the build-up multilayer printed wiring board according to the present invention. In this embodiment, in the first embodiment described above, one build-up insulating layer and a conductive pattern are further formed on the outer layer. The build-up multilayer printed wiring board of the present embodiment is obtained by further applying an undercoat material to both surfaces of the wiring board manufactured in the first embodiment, and then crimping a resin-coated copper foil to obtain the first The conductive pattern having the micro via hole 1a is formed on the outer layer by the same operation as that of the embodiment. In FIG. 4, reference numeral 25a denotes a second buildup insulating layer. If the micro via hole 1 of the build-up layer adjacent to the core substrate is provided on the almost axial line of the blind via hole 2, the same effect can be obtained even if the build-up layer has two or more layers.
[0034]
Next, a third embodiment of the build-up multilayer printed wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 5 is a cross-sectional view of a principal part of a substrate showing a second embodiment of the build-up multilayer printed wiring board according to the present invention. Referring to FIG. 5, in the present embodiment, another core substrate 26 is inserted between the two core substrates in the second embodiment.
In FIG. 5, the core substrate is composed of three core substrates 21, 22, and 26, but if the core substrate is provided with the blind via hole 2 in the outermost two core substrates 21 and 22, The core substrate may be a single-sided printed wiring board or a multilayer printed wiring board having two or more sides. In addition, the code | symbol 3a of FIG. 5 shows the base through-via hole which connects the layers of three core substrates.
[0035]
The build-up multilayer printed wiring board according to the third embodiment can be manufactured by a method similar to the method described in the first embodiment.
[0036]
In the description of the first to third embodiments, the subtractive method is used as the method for manufacturing each core substrate. However, the core substrate may be manufactured by an additive method.
[0037]
【The invention's effect】
As described above, the present invention provides the following effects.
(1) Since a blind via hole is formed by simultaneously filling the through hole of the core substrate in the core substrate laminating process, a special process for filling the blind via hole is not required, and the manufacturing process can be simplified. .
(2) Since the surface of the blind via hole of the core substrate is blocked with a pad and a micro via hole for connecting an upper layer can be directly formed thereon, the wiring capacity of the build-up multilayer printed wiring board can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a substrate for explaining a build-up multilayer printed wiring board according to a first embodiment of the present invention.
2 is a cross-sectional view of the main part of the substrate for explaining the process sequence of the manufacturing method of the build-up multilayer printed wiring board of FIG. 1. FIG.
FIG. 3 is a cross-sectional view of a substantial part of a substrate for explaining a process sequence subsequent to FIG. 2 (c).
FIG. 4 is a cross-sectional view of a principal part of a substrate for explaining a build-up multilayer printed wiring board according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view of a principal part of a substrate for explaining a build-up multilayer printed wiring board according to a third embodiment of the present invention.
[Explanation of symbols]
1, 1a Micro via hole 2 Blind via hole 3, 3a Base through via hole 11, 12, 13, 14 First plating layer 15, 16 Second plating layer 17, 18 Third plating layer 21, 22 Core substrate 23 Insulating layers 25, 25a Build-up insulation layer

Claims (9)

Two core substrates each having at least a blind via hole formed by closing the outer layer side of a through-hole filled with the first insulating layer with a pad, which is laminated through the first insulating layer; , Through the two stacked core substrates, electrically connecting the layers of these core substrates, a base through via hole filled with a second insulating layer therein, and the stacked two substrates A third insulating layer formed on the surface of the core substrate, and a micro via hole formed by plating in an opening reaching the pad of the blind via hole provided in the third insulating layer directly above the blind via hole A build-up multilayer printed wiring board, comprising: 2. The build-up multilayer printed wiring board according to claim 1, further comprising one or more conductive layers between the two core substrates. 3. A build-up multilayer printed wiring board, wherein one or more fourth insulating layers and conductive layers are alternately formed on at least one surface of the build-up multilayer printed wiring board according to claim 1 or 2. Forming a first plating layer on the entire surface of the perforated double-sided copper-clad laminate, and patterning the first plating layer on one side of the laminate to form first and second holes having first through holes. forming a two core substrate, forming a first insulating said first and second core substrate via a resin with the patterned surface on the inside with heat-bonding the inner layer substrate having adhesiveness Both the step of filling the first through holes of the first and second core substrates with the first insulating resin, the step of forming a hole penetrating the inner layer substrate, and the inner layer substrate including the hole hole after forming the second plating layer on the entire surface, and the second plating layer is patterned, Bligh down de via hole having the first pad of closing the surface of the through hole in the second plating the Said second A step of forming a base through via hole having a plating layer; a step of filling the base through via hole with a second insulating layer; a step of forming a third insulating layer on the inner layer substrate; Forming an opening reaching the pad in the insulating layer, and then forming a third plating layer on the surface of the third insulating layer including the opening; and patterning the third plating layer to form the opening in the opening Forming a micro via hole electrically connected to the pad. A method for manufacturing a build-up multilayer printed wiring board, comprising: 5. The method for manufacturing a build-up multilayer printed wiring board according to claim 4, wherein the third insulating resin layer is formed of a thermosetting resin or a photo / thermosetting resin. The manufacturing method of the buildup multilayer printed wiring board of Claim 4 which used the thermosetting resin in which the catalyst for electroless plating was disperse | distributed to said 3rd insulating resin. 5. The method according to claim 4, wherein the first and second core substrates are thermally bonded with the patterned surfaces inside to form an inner layer substrate through an adhesive first insulating resin. A third core substrate having one or more conductive layers is further disposed between the second core substrate and the second core substrate, and the first, third, and second core substrates are heated via the first insulating resin. A method for producing a build-up multilayer printed wiring board, comprising bonding to form an inner layer substrate. 8. The conductive layer made up of a fourth insulating layer and a fourth plating layer alternately on the third insulating layer including the patterned third plating layer according to claim 4. A method for producing a build-up multilayer printed wiring board characterized by forming. 5. The method for manufacturing a build-up multilayer printed wiring board according to claim 4, wherein a laser processing or a photolithography technique is used as the method for forming the opening.

Images