JPH02114697A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH02114697A
JPH02114697A JP63268455A JP26845588A JPH02114697A JP H02114697 A JPH02114697 A JP H02114697A JP 63268455 A JP63268455 A JP 63268455A JP 26845588 A JP26845588 A JP 26845588A JP H02114697 A JPH02114697 A JP H02114697A
Authority
JP
Japan
Prior art keywords
film
insulating resin
substrates
circuit
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63268455A
Other languages
Japanese (ja)
Inventor
Kazuo Oishi
一夫 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63268455A priority Critical patent/JPH02114697A/en
Publication of JPH02114697A publication Critical patent/JPH02114697A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards

Landscapes

  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To improve a hybrid integrated circuit device of this design in the degree of integration by a method wherein the circuit device is provided with such a structure that two circuit substrates are laminated through the intermediary of insulating resin, a film like element is arranged on the joining faces of the substrates with insulating resin respectively, and components are mounted on the surfaces of the substrates opposite to those on which the film like elements are arranged. CONSTITUTION:Two circuit substrates 1 and 2 are bonded together into one piece with an insulating resin layer 4. The insulating resin layer 4 is formed in such manner that thermosetting epoxy resin or the like is applied onto either the first circuit substrate 1 or the second circuit substrate 2 through a screen printing and then heat- bonded with pressure and set. Or, film molding resin of 5-stage may be heat bonded with pressure being sandwiched between the substrates 1 and 2. A film resistor, element 5 and a film condenser element C are formed on the joining faces of the first circuit substrate 1 and the second circuit substrate 3 with the insulating resin layer 4 respectively. And, the faces of the substrates 1 and 2 opposite to those joined to the insulating resin layer 4 are made to serve as component mounting faces, and the component mounting faces and the film-like elements forming faces are electrically connected through through-holes 7.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、混成集積回路装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a hybrid integrated circuit device.

従来の技術 近年、電子機器の小型軽量化や薄形化の進展に伴い、能
動部品であるIl:j、)ランジヌタ等と、受動部品で
ある抵抗、コンデンサ、コイル等を同一パッケージ内に
収納した混成集積回路装置が幅広く利用されており、電
子回路の高密度実装に大いに貢献している。
Conventional technology In recent years, as electronic devices have become smaller, lighter, and thinner, active components such as Il:j, ) lunge nut, and passive components such as resistors, capacitors, and coils have been housed in the same package. Hybrid integrated circuit devices are widely used and contribute greatly to the high-density packaging of electronic circuits.

以下、図面を参照しながら、従来の混成集積回路装置に
ついて説明する。第2図は、従来の混成集積回路装置の
一例における断面図を示したものである。第2図におい
て、13は絶縁基板であシ、一般に96%アルミナ等の
セラミック基板が用いられる。14は導体で、ヌクリー
ン印刷等で形成される厚膜導体、あるいは、蒸着ヌパリ
タリング等で着膜する薄膜導体が使用される。16は前
記絶縁基板表面の導体間に形成された膜抵抗素子であり
、この膜抵抗素子16については、導体14の種類、製
法に対応して、厚膜法、薄膜法のいずれかで形成される
。例えばムg−Pd電極を導体として用いる場合、Ru
O2抵抗体を使用する。16は膜コンデンサ素子であり
、この膜コンデンサ素子16は、絶縁基板13の表面の
下部導体とその上部に形成した誘電体層と更にその上部
に形成した上部導体とから成る3層構造が一般的であり
、抵抗体と同様、厚膜法、薄膜法いずれかにより形成さ
れる。17は前記絶縁基板13の表面導体と裏面導体を
電気的に接続するヌル−ホールである。
A conventional hybrid integrated circuit device will be described below with reference to the drawings. FIG. 2 shows a cross-sectional view of an example of a conventional hybrid integrated circuit device. In FIG. 2, 13 is an insulating substrate, and generally a ceramic substrate such as 96% alumina is used. Reference numeral 14 denotes a conductor, which may be a thick film conductor formed by Nuclean printing or the like, or a thin film conductor deposited by vapor deposition Nuparitaring or the like. 16 is a film resistance element formed between the conductors on the surface of the insulating substrate, and this film resistance element 16 is formed by either a thick film method or a thin film method, depending on the type and manufacturing method of the conductor 14. Ru. For example, when using a Mug-Pd electrode as a conductor, Ru
Use an O2 resistor. 16 is a membrane capacitor element, and this membrane capacitor element 16 generally has a three-layer structure consisting of a lower conductor on the surface of the insulating substrate 13, a dielectric layer formed on top of the lower conductor, and an upper conductor further formed on top of the lower conductor. Like the resistor, it is formed by either the thick film method or the thin film method. Reference numeral 17 denotes a null hole that electrically connects the front conductor and back conductor of the insulating substrate 13.

以上の構成から成る厚膜回路基板あるいは薄膜回路基板
の表面または裏面に、チップ部品18.ミニモールドト
ランジヌタ19 、SO形IOパ、、tケージ2o等を
半田接続し、かつ外部摩り出し端子としてクリップ状リ
ード端子を絶縁基板13の周辺部にはさみこみ、半田2
2により、導体14と接続した構造となっている。以上
のように回路基板の両面に部品を実装するとともに、膜
抵抗素子。
Chip components 18. A mini-mold transistor 19, an SO type IO pad, a t-cage 2o, etc. are connected by soldering, and a clip-shaped lead terminal is inserted into the periphery of the insulating board 13 as an external extrusion terminal, and the solder 2
2, the structure is connected to the conductor 14. In addition to mounting components on both sides of the circuit board as described above, film resistance elements are also mounted on both sides of the circuit board.

膜コンデンサ素子、膜インダクタンヌ素子等ヲ同じく回
路基板の両面に配置することにより、高密度実装を実現
している。またICについては、ワイヤボンディング法
、またはフリ・Iブチリプ法等によりベアチップを直接
基板上に実装する場合もある。
High-density packaging is achieved by arranging membrane capacitor elements, membrane inductor elements, etc. on both sides of the circuit board. Regarding ICs, bare chips may be directly mounted on a substrate by a wire bonding method, a free/I-button lip method, or the like.

発明が解決しようとする課題 しかしながら、従来の混成集積回路装置は、基板両面に
部品及び膜抵抗素子、膜コンデンサ素子を配置している
ため、集積度の向上の面で限界に達しつつある。フォト
リングラフィ等を使った導体配線のファインライン化ま
たは多層化等によって配線面積を縮小することも可能で
あるが、コヌトが大幅に高くなるという問題点を有して
いた。
Problems to be Solved by the Invention However, since conventional hybrid integrated circuit devices have components, film resistance elements, and film capacitor elements arranged on both sides of the substrate, they are reaching a limit in terms of improving the degree of integration. Although it is possible to reduce the wiring area by creating fine lines or multilayering the conductor wiring using photolithography or the like, there is a problem in that the wiring becomes significantly high.

一方、回路基板を重ねた高密度実装技術では、回路基板
の間の隙間に、半田付は時のフラ・ソクスが残っていた
り、あるいは使用時の吸湿により、絶縁性が下が9、端
子間のショートにつながる恐れがある。
On the other hand, with high-density mounting technology in which circuit boards are stacked, insulation from soldering may remain in the gaps between circuit boards, or insulation may deteriorate due to moisture absorption during use. This may lead to a short circuit.

本発明はかかる点に鑑みなされたもので、大幅なコヌト
アソブを招くことなく、簡素な製造工程を用いて、従来
の両面実装形混成集積回路装置の集積度を大幅に上回る
高密度混成集積回路装置を提供することを目的としてい
る。
The present invention has been devised in view of the above points, and uses a simple manufacturing process without causing a large amount of complexity, and has a high-density hybrid integrated circuit device that significantly exceeds the degree of integration of conventional double-sided mount type hybrid integrated circuit devices. is intended to provide.

課題を解決するための手段 本発明は、上記問題点を解決するため、2枚の回路基板
が絶縁樹脂を介して積層された構造を有し、前記2枚の
回路基板の絶縁樹脂との接合面に、それぞれ膜状素子を
配置し、かつ前記2枚の回路基板の膜状素子形成面に対
して反対面に部品を搭載したものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a structure in which two circuit boards are laminated with an insulating resin interposed therebetween, and the bonding of the two circuit boards with the insulating resin is provided. A film element is arranged on each surface, and components are mounted on the opposite surface of the two circuit boards to the surface on which the film element is formed.

作用 本発明は、従来の混成集積回路装置において膜状素子を
回路基板の表面あるいは裏面に配置する代わりに、積層
した2枚の回路基板の接合面にそれぞれ配置することに
より、投影面積において基板面積の2層分の面積を基板
接合部のみで有効に利用できることとなる。更に膜状素
子が接合而に収納された結果として、一体接合化された
基板の表面および裏面の全面積をチップ部品、IC等の
部品実装に利用できることとなる。以上のように、2枚
の回路基板を用いて、絶縁樹脂によって接合される内層
膜状素子形成面2層分と、チップ部品及び実装面となる
表面、裏面の2層分とを有する、計4層構成の混成集積
回路装置を提供することとなる。
Function The present invention reduces the board area in terms of projected area by arranging film elements on the bonding surfaces of two laminated circuit boards, instead of arranging them on the front or back surfaces of the circuit boards in conventional hybrid integrated circuit devices. This means that the area for two layers can be effectively used only in the substrate bonding portion. Furthermore, as a result of the film elements being housed in a bonded structure, the entire area of the front and back surfaces of the integrally bonded substrate can be used for mounting components such as chip components and ICs. As described above, two circuit boards are used to create a circuit board that has two layers on the inner layer film element forming surface bonded by insulating resin, and two layers on the front and back surfaces that serve as chip components and mounting surfaces. A hybrid integrated circuit device having a four-layer configuration is provided.

さらに、2枚の回路基板の間の隙間を絶縁樹脂で完全に
埋めているので、フラツクスが隙間に入り込んだり、水
分が入り込んだりして、絶縁性が下がり、ショートが起
きるという現象も避けることができる。
Furthermore, since the gap between the two circuit boards is completely filled with insulating resin, it is possible to prevent flux from entering the gap or moisture from entering the gap, reducing insulation properties and causing short circuits. can.

実施例 以下、本発明の一実施例について図面を参照しながら詳
細に説明する。第1図は、本発明の一実強例における混
成集積回路装置の断面図である。
EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of a hybrid integrated circuit device in one practical example of the present invention.

第1の回路基板1と第2の回路基板2はそれぞれ焼結済
みのセラミック等の無機系絶縁基板であり、今回は96
%アルミナを使用している。その表面には、所定の配線
パターンの導体3が形成されており、これら2枚の回路
基板1,2は絶縁樹脂層4により接合一体化されている
。絶縁樹脂層4は、熱硬化型のエポキシ系樹脂等をヌク
リーン印Iす法により第1の回路基板1.第2の回路基
板2のいずれか一方に、加熱圧着することにより接合硬
化して得られる。あるいは、Bステージ状態のフィルム
成形樹脂を2枚の回路基板1.2間にはさんで、加熱圧
着してもよい。またポリイミドフィルムにエポキシ等の
接着剤を両面塗布した接着剤付きポリイミドフィルムを
用いてもよい。前記第1の回路基板1.第2の回路基板
2の絶縁樹脂層4との接合而には、それぞれ膜抵抗素子
6と膜コンデンサ素子6が形成されている。また、絶縁
樹脂層4との接合面に対して各回路基板1.2の反対面
は、部品搭載面として使用しており、部品搭載面と膜状
素子形成面とはヌル−ホール7によって電気的導通を行
っている。第1の回路基板1の部品搭載面には、チップ
コンデンサ、チップコイル等のチップ部品8とミニモー
ルドトランジヌタ9が半田付けにより実装されている。
The first circuit board 1 and the second circuit board 2 are each an inorganic insulating board made of sintered ceramic or the like.
% alumina is used. A conductor 3 having a predetermined wiring pattern is formed on the surface thereof, and these two circuit boards 1 and 2 are joined together by an insulating resin layer 4. The insulating resin layer 4 is formed on the first circuit board 1 by using a thermosetting epoxy resin or the like using a Nuclean printing method. It is obtained by bonding and curing by heat-pressing bonding to either one of the second circuit boards 2. Alternatively, the film-molded resin in the B stage state may be sandwiched between two circuit boards 1.2 and bonded under heat and pressure. Alternatively, an adhesive-coated polyimide film obtained by coating both sides of a polyimide film with an adhesive such as epoxy may be used. Said first circuit board 1. A membrane resistive element 6 and a membrane capacitor element 6 are formed at the junctions of the second circuit board 2 and the insulating resin layer 4, respectively. In addition, the opposite surface of each circuit board 1.2 to the bonding surface with the insulating resin layer 4 is used as a component mounting surface, and the component mounting surface and the membrane element forming surface are connected to each other by the null hole 7. We are communicating with each other. On the component mounting surface of the first circuit board 1, chip components 8 such as a chip capacitor and a chip coil, and a mini mold transistor 9 are mounted by soldering.

また第2の回路基板2の部品搭載面にはチップ部品8と
IC10が同じく半田付けにより実装されている。以上
の搭載部品は、2枚の回路基板1.2を接合−体化する
前に、個々の回路基板1.2の状態においてリフロー法
、あるいは半田浸漬法等によって実装される。11はク
リップ状リード端子であり、接合一体化された第1の回
路基板1.第2の回路基板2をはさみ込むように挿入さ
れ、半田12によって、各回路基板1.2の部品搭載面
の端子ランドと接続されている。尚、クリ1.プ状リー
ド端子11は、半田接続後に所定の切断工程、フォーミ
ング工程を経て成形される。また耐湿性の向上や自動実
装性の向上を目的として外装樹脂モールド成形やコーテ
ィングを施こす場合がある。
Furthermore, a chip component 8 and an IC 10 are similarly mounted on the component mounting surface of the second circuit board 2 by soldering. The above-described mounting components are mounted on each circuit board 1.2 by a reflow method, a solder dipping method, or the like before the two circuit boards 1.2 are joined together. Reference numeral 11 denotes a clip-shaped lead terminal, which is connected to the first circuit board 1. It is inserted so as to sandwich the second circuit board 2, and is connected by solder 12 to a terminal land on the component mounting surface of each circuit board 1.2. Furthermore, chestnut 1. The pull-shaped lead terminal 11 is formed through a predetermined cutting process and forming process after soldering. In addition, exterior resin molding or coating may be applied to improve moisture resistance and automatic mounting performance.

以上の構成による本実施例を用いて、具体的な混成集積
回路装置を試作し、従来例と比較した結果を以下に述べ
る。表1は、民生用機器の小信号回路を本実施例と従来
例を用いて試作した結果を示す表である。内蔵部品総数
74点で構成される回路を従来の両面実装基板で作成し
た場合、20jlff X 30 I’llの基板面積
を必要とし、集積密度で12.3点/lriとなった。
Using this embodiment with the above configuration, a concrete hybrid integrated circuit device was prototyped, and the results of comparison with the conventional example will be described below. Table 1 is a table showing the results of trial manufacturing of a small signal circuit for consumer equipment using this embodiment and a conventional example. When a circuit consisting of a total of 74 built-in components was created using a conventional double-sided mounting board, a board area of 20 lff x 30 I'll was required, resulting in an integration density of 12.3 points/lri.

使用した基板は配線幅200μm 、配線間隔200μ
mの設計ルールを用い、銅厚膜セラミック基板の両面実
装基板を使用している。従来例に対して、本実施例では
、膜抵抗素子38点と膜コンデンサ素子20点を、絶縁
樹脂層との接合面に配置することにより、基板面積を2
0mX16m[縮小でき、集積密度を23.1点/dに
することができる。なお、使用した設計ルール及び基板
材質は従来例と全く同じ仕様で試作した。
The board used has a wiring width of 200μm and a wiring spacing of 200μm.
A double-sided mounting board made of a copper thick film ceramic board is used. In contrast to the conventional example, in this example, 38 film resistance elements and 20 film capacitor elements are arranged on the bonding surface with the insulating resin layer, thereby reducing the substrate area by 2.
It can be reduced to 0m x 16m, and the integration density can be reduced to 23.1 points/d. The design rules and substrate material used were the same as the conventional example.

以上のように、本実砲例による混成集積回路装置は、使
用回路基板を2枚構成とし、膜抵抗素子及び膜コンデン
サ素子を絶縁樹脂層との接合面に配置することにより、
約2倍の実装密度を実現することができる。
As described above, the hybrid integrated circuit device according to this example uses two circuit boards, and by arranging the membrane resistor element and the membrane capacitor element on the joint surface with the insulating resin layer,
Approximately twice the packaging density can be achieved.

(以 下 余 白) さらに、2枚の回路基板を絶縁樹脂層を介して接合し、
完全に一体化しているので、回路基板の間の隙間に、フ
ラソクヌが残ったり、また吸湿が起こったりすることが
なく、端子間シヲートもなくなる。
(Left below) Furthermore, two circuit boards are bonded via an insulating resin layer,
Since it is completely integrated, there is no residual moisture left in the gaps between the circuit boards, no moisture absorption, and no seats between terminals.

なお、本実施例においては、部品実装を回路基板の接合
工程以前に行っているが、製造工程の都合により、基板
接合一体止の後に行ってもよい。
In this embodiment, component mounting is performed before the circuit board bonding process, but depending on the manufacturing process, it may be performed after the board bonding process.

また、個々の第1の回路基板1.第2の回路基板2は単
層導体によるセラミック基板を使用したが、印刷方式あ
るいはグリーンシート方式による多層基板を使用しても
、同じ効果が得られることは言うまでもない。
Further, each first circuit board 1. Although the second circuit board 2 uses a ceramic board with a single layer conductor, it goes without saying that the same effect can be obtained even if a multilayer board with a printing method or a green sheet method is used.

発明の詳細 な説明したように、本発明によれば、2枚の回路基板を
絶縁樹脂層を介して接合し、その接合面に抵抗、コンデ
ンサ、インダクタンス等の膜状素子を配置することで、
4層構造の一体化回路装置ができ、実装密度が大幅に向
上する。さらに絶縁樹脂層を介しているため、2枚の回
路基板間へのフラlクヌや水の侵入が原因である端子間
ショートもなくなる。
As described in detail, according to the present invention, two circuit boards are bonded via an insulating resin layer, and film elements such as resistors, capacitors, and inductances are arranged on the bonded surface.
An integrated circuit device with a four-layer structure can be created, greatly improving packaging density. Furthermore, since the insulating resin layer is interposed, short circuits between terminals caused by leakage or water intrusion between two circuit boards are also eliminated.

以上のように本発明は、簡単な製造工程で大幅なコヌト
アノプを招くことなく、高密度な混成集積回路装置を提
供できるため、その実用的効果は犬なるものがある。
As described above, the present invention can provide a high-density hybrid integrated circuit device through a simple manufacturing process without causing a large amount of noise, and therefore has significant practical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における混成集積回路装置の
断面図、第2図は従来の混成集積回路装置の一例におけ
る断面図である。 1・・・・・・第1の回路基板、2・・・・・・第2の
回路基板、3・・・・・・導体、4・・・・・・絶縁樹
脂層、6・・・・・・膜抵抗素子、6・・・・・・膜コ
ンデンサ素子、7・・・・・・ヌル−ホール、8・・・
・・・チップ部品、9・・・・・・ミニモールドトラン
ジヌタ、10・・・・・・工C111・・・・・・クリ
 ノブ状リード端子、12・・・・・・半田。
FIG. 1 is a sectional view of a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional hybrid integrated circuit device. DESCRIPTION OF SYMBOLS 1...First circuit board, 2...Second circuit board, 3...Conductor, 4...Insulating resin layer, 6... ...Membrane resistor element, 6...Membrane capacitor element, 7...Null-hole, 8...
...Chip parts, 9...Mini mold transistor, 10...C111...Clean knob-shaped lead terminal, 12...Solder.

Claims (1)

【特許請求の範囲】[Claims] 2枚の回路基板が絶縁樹脂を介して積層された構造を有
し、前記2枚の回路基板の絶縁樹脂との接合面に、それ
ぞれ膜状素子を配置し、かつ前記2枚の回路基板の膜状
素子形成面に対して反対面に部品を搭載した混成集積回
路装置。
It has a structure in which two circuit boards are laminated with an insulating resin interposed therebetween, and a film-like element is arranged on the bonding surface of the two circuit boards with the insulating resin, and A hybrid integrated circuit device in which components are mounted on the opposite side to the surface on which film elements are formed.
JP63268455A 1988-10-25 1988-10-25 Hybrid integrated circuit device Pending JPH02114697A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63268455A JPH02114697A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63268455A JPH02114697A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH02114697A true JPH02114697A (en) 1990-04-26

Family

ID=17458744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63268455A Pending JPH02114697A (en) 1988-10-25 1988-10-25 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH02114697A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0470772U (en) * 1990-10-31 1992-06-23
US5428885A (en) * 1989-01-14 1995-07-04 Tdk Corporation Method of making a multilayer hybrid circuit
WO1997008737A2 (en) * 1995-08-24 1997-03-06 Siemens Aktiengesellschaft Circuit arrangement including a hybrid circuit
US7635046B2 (en) 2006-03-06 2009-12-22 Mitsubishi Electric Corp. Electric power steering apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428885A (en) * 1989-01-14 1995-07-04 Tdk Corporation Method of making a multilayer hybrid circuit
JPH0470772U (en) * 1990-10-31 1992-06-23
WO1997008737A2 (en) * 1995-08-24 1997-03-06 Siemens Aktiengesellschaft Circuit arrangement including a hybrid circuit
WO1997008737A3 (en) * 1995-08-24 1997-04-10 Siemens Ag Circuit arrangement including a hybrid circuit
US7635046B2 (en) 2006-03-06 2009-12-22 Mitsubishi Electric Corp. Electric power steering apparatus

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