KR0152576B1 - Stack chip package having center pad - Google Patents

Stack chip package having center pad

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Publication number
KR0152576B1
KR0152576B1 KR1019950033124A KR19950033124A KR0152576B1 KR 0152576 B1 KR0152576 B1 KR 0152576B1 KR 1019950033124 A KR1019950033124 A KR 1019950033124A KR 19950033124 A KR19950033124 A KR 19950033124A KR 0152576 B1 KR0152576 B1 KR 0152576B1
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KR
South Korea
Prior art keywords
chip package
substrate
chip
package
bonding pads
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Application number
KR1019950033124A
Other languages
Korean (ko)
Other versions
KR970018456A (en
Inventor
권영도
송영희
Original Assignee
김광호
삼성전자주식회사
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Priority to KR1019950033124A priority Critical patent/KR0152576B1/en
Publication of KR970018456A publication Critical patent/KR970018456A/en
Application granted granted Critical
Publication of KR0152576B1 publication Critical patent/KR0152576B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

본 발명은 센터 본딩패드들 갖는 적층 칩 패키지에 관한 것으로, 동일칩을 적층하더라도 핀명의 자유도가 원활하게 할 수 있도록, 적어도 2개 이상의 칩이 양면 실장된 적어도 2개 이상의 윈도우와; 그 윈도우를 가로질러 형성된 금속 패턴닝을 갖는 기판과; 상기 칩상에 형성된 본딩패드들에 대응된 리드들이 기판의 접속안자들이 관통공에 의해 전기적 연결된 것을 특징으로 한다.The present invention relates to a stacked chip package having center bonding pads, comprising: at least two or more windows on which at least two chips are double-sided mounted so that the degree of freedom of pin names can be smoothed even when the same chips are stacked; A substrate having metal patterning formed across the window; Leads corresponding to bonding pads formed on the chip may be electrically connected by connection holes of substrates.

Description

센터 패드를 갖는 적층 칩 패키지Stacked Chip Packages with Center Pad

제1도는 종래 기술의 실시예에 의한 대칭칩을 적용한 적층 칩 패키지를 나타내는 단면도.1 is a cross-sectional view showing a laminated chip package to which a symmetric chip according to an embodiment of the prior art is applied.

제2도는 종래 기술의 다른 실시예에 의한 센터 패드를 갖는 대칭칩을 적용한 적층 칩 패키지의 단면도.2 is a cross-sectional view of a laminated chip package to which a symmetric chip having a center pad according to another embodiment of the prior art is applied.

제3도 내지 제5도는 본 발명의 실시예에 의한 와이어 본딩법에 의한 센터 패드를 갖는 적층 칩 패키지를 나타내는 단면도.3 to 5 are cross-sectional views showing a laminated chip package having a center pad by a wire bonding method according to an embodiment of the present invention.

제6도는 본 발명의 다른 실시예에 의한 범프를 적용한 센터 패드를 갖는 적층 칩 패키지를 나타내는 단면도.6 is a cross-sectional view showing a laminated chip package having a center pad to which bumps are applied according to another embodiment of the present invention.

제7도는 본 발명에 의한 상호 접속 기술이 상이한 적층 칩 패키지를 나타내는 단면도.7 is a cross-sectional view showing a laminated chip package having a different interconnection technology according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10,10A : 칩 20,30,40 : 기판10,10A: chip 20,30,40: substrate

50,55 : 반성형 윈도우부 70 : 성형수지50,55: semi-molded window part 70: molding resin

80 : 리드 85 : 비전도성 접착제80: lead 85: non-conductive adhesive

300,310,320,330,340 : 적층 칩 패키지300,310,320,330,340: stacked chip packages

본 발명은 적층 칩 패키지에 관한 것으로, 더욱 상세하게는 적층 칩 패키지를 구성 시에 대칭칩(mirror chip)이 필요 없도록 와이어 본딩에 의한 상호 접속을 하여 패키지 불량확인시 재작업이 가능하도록 한 것이며, 또한 폴리아미드 계열의 내열성 기판을 적용한 센터 패드를 갖는 적층 칩 패키지에 관한 것이다.The present invention relates to a laminated chip package, and more particularly, to rework when a package defect is confirmed by interconnecting by wire bonding so that a mirror chip is not required when constructing a laminated chip package. The present invention also relates to a laminated chip package having a center pad to which a polyamide-based heat resistant substrate is applied.

최근 고집적 메모리 패키징 기술이 개발되어 적용 또는 검토중이며, 대부분은 상호접속 기술이라 할 수 있으나, 이에 따른 양산기술에 대한 확보가 필요한데, 그렇지 못한 경우 시제품 제작에만 그치고 마는 경우가 대부분이다.Recently, high-density memory packaging technology has been developed and is being applied or reviewed, and most of them can be referred to as interconnect technologies, but it is necessary to secure mass production technology accordingly.

단위 패키지에 칩의 실장 밀도를 높이기 위한 일반적인 방법중의 하나가 적층 칩 패키지이다.One common method for increasing chip mounting density in a unit package is a stacked chip package.

전술한 적층 칩 패키지의 실시예로써 미국 특허 제4,862,322호(등록일:1989.8.29. 발명의 명칭:double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projection outwardly from theirbetween.)에 개시되어 있다. 제1도를 참조하면, 종래기술에 따른 상호 대칭구조를 갖는 적층칩의 제1실시예로써, 상부칩(10) 및 하부칩(10A)이 서로 마주보며 적층되어 있고, 그 본딩패드들에 대응되는 좌우 연결단자(22),(24)와 범프(3)에 의해 전기적 연결되어 있으며, 그 연결단자들(22),(24)은 그들에 공통 연결되는 리드(11)가 들어가 전기적 연결되어 있으며, 상기 구조는 성형수지(70)에 의해 봉지된 구조를 갖는다.As an embodiment of the above-mentioned stacked chip package, disclosed in US Patent No. 4,862,322 (registered date: Aug. 29, 1989, double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projection outwardly from theirbetween.) have. Referring to FIG. 1, as a first embodiment of a stacked chip having a mutually symmetrical structure according to the related art, the upper chip 10 and the lower chip 10A are stacked to face each other, and correspond to the bonding pads. The left and right connecting terminals 22 and 24 are electrically connected to each other by the bumps 3, and the connecting terminals 22 and 24 are electrically connected by the leads 11 commonly connected to them. , The structure has a structure encapsulated by the molding resin (70).

또 다른 적층 칩 패키지의 실시예로써 미국 특허 제4,763,188호(등록일:1988.8.9. 발명의 명칭:packaging system for multiple semiconductor devices)에 개시되어 있다. 제2도를 참조하면, 상부칩(10)의 센터 본딩패드들은 그들에 대응되는 연결단자들(21)과 범프(3)에 의해 전기적 연결되어 있으며, 같은 방법으로 하부칩(10A)의 센터 본딩패드들이 그들에 대응되는 연결단자들(23)과 범프(3)에 의해 전기적 연결되어 있으며, 상기 각기 연결단자들(21),(23)은 공통 리드(11)와 전기적 연결되어 있으며, 상기 구조는 성형수지(70)에 의해 봉지된 구조를 갖는다.Another embodiment of a stacked chip package is disclosed in US Pat. No. 4,763,188 (registered date: 1988.8.9. Packaging invention for multiple semiconductor devices). Referring to FIG. 2, the center bonding pads of the upper chip 10 are electrically connected by connecting terminals 21 and bumps 3 corresponding thereto, and in the same manner, the center bonding pads of the lower chip 10A are connected. The pads are electrically connected by connecting terminals 23 and bumps 3 corresponding to the pads, and the connecting terminals 21 and 23 are electrically connected to the common lead 11, respectively. Has a structure encapsulated by the molding resin (70).

따라서 본 발명의 목적은 상호접속을 보다 용이하게 하는 동시에 고집적 박형 패키지를 실제 생산성 있도록 하는 센터 패드를 갖는 적층 칩 패키지를 제공하는데 있다.It is therefore an object of the present invention to provide a stacked chip package having a center pad which makes the interconnect easier and at the same time makes the highly integrated thin package practically productive.

상기 목적을 달성하기 위하여, 복수개의 칩이 실장되는 적층 칩 패키지에 있어서, 적어도 2개 이상의 칩이 양면 실장된 적어도 2개 이상의 윈도우와; 그 윈도우를 가로질러 형성된 금속 패턴닝을 갖는 기판과; 상기 칩상에 형성된 본딩패드들에 대응된 리드들이 기판의 접속단자들이 관통공에 의해 전기적 연결된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지를 제공한다.In order to achieve the above object, a laminated chip package in which a plurality of chips are mounted, comprising: at least two windows at least two chips mounted on both sides; A substrate having metal patterning formed across the window; Provided is a multilayer chip package having a center pad, wherein leads corresponding to bonding pads formed on the chip are electrically connected to connection terminals of a substrate by a through hole.

이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

제3도 내지 제5도는 본 발명의 실시예에 의한 센터 패드를 갖는 적층 칩 패키지를 나타내는 단면도이다.3 to 5 are cross-sectional views showing a stacked chip package having a center pad according to an embodiment of the present invention.

제3도를 참조하면, 본 발명에 의한 적층 칩 패키지(300)는 상부칩(10)의 센터 본딩패드들은 하부칩(10A)과 비전도성 접착제(85)에 의해 공통 접착된 중앙기판(20)의 회로패턴들에 대응하여 와이어(60)에 의해 전기적 연결되어 있으며, 그 다른 본딩패드들은 상기 상부칩의 에지면이 접착된 에지기판(30)의 기판의 접속패드들에 대응하여 각기 와이어(60)에 의해 전기적 연결되어 있으며, 같은 방법으로 하부칩(10A)은 그의 상부면상에 형성된 센터 본딩패드들이 상기 상부칩(10)과 공통으로 일부면이 접착된 공통기판(20)에 각기 와이어(60)에 의해 전기적 연결되어 있으며, 또한 그 다른 본딩패드들은 상기 하부칩(10A)의 에지면이 접착된 에지기판(40)의 기판의 접속패드들에 대응하여 와이어(60)에 의해 전기적 연결되어 있는 구조를 갖으며, 상기 와이어 본딩된 부분은 반성형(half molding) 윈도우부들(50),(55)이 되어 있어 그 부분이 외부로부터 보호되어 있으며, 상기 각 에지기판들은(30),(40)은 리드들(80)과 각기 전도성 물질에 의해 전기적 연결되어 있으며, 상기의 내부구조는 성형수지(70)에 의해 보호되어 있는 구조를 갖는다.Referring to FIG. 3, in the stacked chip package 300 according to the present invention, the center bonding pads of the upper chip 10 are commonly bonded by the lower chip 10A and the non-conductive adhesive 85. The other bonding pads are electrically connected by wires 60 corresponding to the circuit patterns of the wires 60, and the other bonding pads respectively correspond to the connection pads of the substrate of the edge substrate 30 to which the edge of the upper chip is bonded. In the same way, the lower chip 10A is wired to the common substrate 20 to which the center bonding pads formed on the upper surface of the lower chip 10A are bonded to the upper chip 10, respectively. The other bonding pads are electrically connected by wires 60 corresponding to the connection pads of the substrate of the edge substrate 40 to which the edge surface of the lower chip 10A is bonded. Structure, the wire bonded portion is The half molding window portions 50 and 55 are protected from the outside, and the edge substrates 30 and 40 are formed on the leads 80 and the conductive material, respectively. By the electrical connection, the internal structure has a structure that is protected by the molding resin (70).

제4도를 참조하면, 제3도에 있어서의 기판으로의 와이어 본딩을 한쪽으로만 한 구조를 갖으며, 제5도는 제3도의 기판들과의 전기적 연결은 와이어 본딩으로 하고 칩과 기판의 접착은 비전도서우 접착제(85)로 접착한 것을 특징으로 한다.Referring to FIG. 4, it has a structure in which wire bonding to the substrate in FIG. 3 is made on one side only, and FIG. 5 is wire bonding as the electrical connection with the substrates in FIG. The non-coated adhesive is characterized in that the adhesive 85.

제6도는 본 발명의 다른 실시예에 의한 범프를 적용한 센터 패드를 갖는 적층 칩 패키지를 나타내는 단면도이다. 제6도를 참조하면, 적층 칩 패키지(33)는 상부칩(10)과 하부칩(10A)이 서로 마주보고 적층되어 있으며, 그들의 사이에 공통기판(30)이 삽입되어 각기 비전도성 접착제(85)에 의해 공통으로 접착되어 있으며, 상기 칩들(10),(10A)의 센터 본딩패드들은 그들에 대응되는 공통기판(30)의 기판의 접속패드들에 각기 범프(3)에 의해 전기적 연결되어 있으며, 상기 공통기판(30)의 에지부에서는 그들에 대응되는 리드들(80)에 전도성 물질에 의해 전기적 연결된 구조를 갖는다.6 is a cross-sectional view illustrating a multilayer chip package having a center pad to which bumps are applied according to another embodiment of the present invention. Referring to FIG. 6, in the stacked chip package 33, the upper chip 10 and the lower chip 10A are stacked to face each other, and a common substrate 30 is inserted therebetween to each of the non-conductive adhesives 85. Are bonded to each other, and the center bonding pads of the chips 10 and 10A are electrically connected to the connection pads of the substrate of the common substrate 30 corresponding thereto by bumps 3, respectively. In addition, the edge portion of the common substrate 30 has a structure electrically connected to the leads 80 corresponding to them by a conductive material.

제7도는 본 발명에 의한 상호 접속 기술이 상이한 적층 칩 패키지를 나타내는 단면도이다. 제7도를 참조하면, 적층 칩 패키지(340)는 에지 본딩패드들을 갖는 상부칩(10)은 공통기판(30)과 비전도성 접착제(85)에 의해 접착되어 있으며, 그 본딩패드들은 그들에 대응되는 리드들(80)에 각기 와이어(60)에 의해 전기적 연결되어 있으며, 그 이외의 구조는 제6도의 패키지와 동일한 구조를 갖는다.7 is a cross-sectional view showing a stacked chip package having different interconnection technologies according to the present invention. Referring to FIG. 7, the stacked chip package 340 has an upper chip 10 having edge bonding pads bonded by a common substrate 30 and a non-conductive adhesive 85, and the bonding pads correspond to them. The leads 80 are electrically connected to each other by wires 60, and the other structures have the same structure as that of the package of FIG.

이때 각 칩의 입력/출력 리드들과 연결되는 본딩패드가 기판의 상하면에 위치하고 적어도 한면에는 리드프레임의 내부리드와 연결될 수 있도록 한 단자가 있도록 하며, 본딩패드와 기판의 접속패드가 와이어 패턴에 의해 서로 연결된다.At this time, the bonding pads connected to the input / output leads of each chip are located on the upper and lower surfaces of the board, and at least one side thereof has a terminal to be connected to the inner lead of the lead frame, and the bonding pads and the connection pads of the board are connected by a wire pattern. Are connected to each other.

종래의 기술과 같이 입력/출력 리드와 본딩패드의 연결은 범프로 상호접속시키는 방법 대신에 와이어 본딩방법을 적용하여 1개 또는 2개 정도의 본딩 작업 불량시 재작업이 2-3차례 가능하도록 함으로써 칩 2개중에 본딩 에러에 의한 생산성 저하를 재작업이 가능토록 함으로써 종래 기술을 극복하였다.As in the prior art, the connection between the input / output leads and the bonding pads is made by applying a wire bonding method instead of interconnecting the bumps so that rework can be performed 2-3 times in case of one or two defects. Overcoming the prior art has been overcome by allowing rework to reduce productivity due to bonding errors in two chips.

또한 박형 패키지의 추세에 따라 폴리이미드 계열의 내열성을 갖는 기판을 적용하였으며 내열성외에 매우 얇게 할 수 있는 재료이므로 박형 패키지에 적용함이 가능하다.In addition, in accordance with the trend of thin package, a substrate having a polyimide-based heat resistance is applied. Since the material can be made very thin besides heat resistance, it can be applied to a thin package.

또한 관통홀을 이용한 기판 양면에 단자가 형성된 양면기판을 적용하였다. 이 기판의 단자 및 본딩패드는 구리에 니켈 및 금을 프레팅함으로써, 와이어 본딩시에 본딩성을 향상시켰으며, 기판 두께에 있어서, 테이프(P.I)는 1mil, 단자는 1.03mil이 가능하므로 최소한 3.06mil이 가능하다.In addition, a double-sided board having terminals formed on both sides of the board using through holes was applied. The board and bonding pads of this board improve the bonding properties during wire bonding by pre-coating nickel and gold on copper, and at least 3.06 since the tape thickness is 1 mil and the terminal is 1.03 mil. mil is possible.

이렇게 만들어진 기판을 외부 회로와 연결될 수 있도록 기판내의 접속패드와 리드프레임의 내부리드를 접촉하며 기판의 접속패드와 내부리드상의 전도성 물질에 따라 그 응용범위를 높일 수 있다.The contact pad in the substrate and the inner lead of the lead frame may be contacted with each other so that the substrate may be connected to an external circuit, and the application range may be increased according to the contact pad of the substrate and the conductive material on the inner lead.

일반적인 열압착 방식에 의한 상호접속 기술로 기판의 접속패드와 내부리드의 접합은 재료의 종류에 따라 동종 이종 금속간 접합을 할 수 있는데 주로 금(패드들)대 금(내부리드), 금(패드)대 주석(내부리드), 금(패드)대 은(내부리드)등 여러 가지가 있을 수 있으나 높은 온도에 또는 높은 압력에 의해 기판에 품질적인 문제가 발생되지 않아야 한다. 또한 기판(P.I)에 구리의 단자를 연결할 때는 접착제를 이용하는 방법과 그렇지 않고 스파트 또는 플라즈마 등으로 또는 압착으로 연결하는 비접착제 유형의 기판이 있는데 이는 접착제보다 경(硬)하여 열압착 방식에 적당하다. 따라서, TSOP(thin small outline package)와 같은 박형의 패키지 적용이 가능하게 되었다.In general, the thermal bonding technology is used to connect the board's connection pad and the inner lead, which can be made between different types of metals, depending on the type of material, mainly gold (pads) versus gold (inner lead) Tin (inner lead), gold (pad) versus silver (inner lead) can be used, but the quality problem should not occur in the substrate due to high temperature or high pressure. In addition, there is a method of using an adhesive to connect the copper terminal to the substrate (PI), and there is a non-adhesive type of substrate that is connected by a spat, plasma, or compression, which is harder than an adhesive, and thus suitable for thermocompression bonding. . Therefore, a thin package such as a thin small outline package (TSOP) can be applied.

Claims (9)

복수개의 칩이 실장되는 적층 칩 패키지에 있어서, 적어도 2개 이상의 칩이 양면 실장된 적어도 2개 이상의 윈도우와; 그 윈도우를 가로질러 형성된 금속 패턴닝을 갖는 기판과; 상기 칩상에 형성된 본딩패드들에 대응된 리드들이 기판의 접속단자들이 관통공에 의해 전기적 연결된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.A stacked chip package in which a plurality of chips are mounted, the stacked chip package comprising: at least two windows at least two chips mounted on both sides; A substrate having metal patterning formed across the window; Leads corresponding to the bonding pads formed on the chip is a laminated chip package having a center pad, characterized in that the connection terminals of the substrate are electrically connected by a through hole. 제1항에 있어서, 상기 기판의 일면상의 외부리드와 접속될 수 있도록 한 단자가 형성된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.The multilayer chip package of claim 1, wherein a terminal is formed to be connected to an external lead on one surface of the substrate. 제1항에 있어서, 상기 실장될 칩의 본딩패드와 접속할 수 있는 단자가 기판의 양면에 형성된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.The multilayer chip package of claim 1, wherein terminals connected to the bonding pads of the chip to be mounted are formed on both sides of the substrate. 제1항에 있어서, 상기 실장될 칩의 안정화를 위하여 폴리이미드 계열의 필름에 열경화성 및 열가소성 접착제중의 어느 하나를 테이프 형태 및 쉬트(sheet) 형태의 어느 한 형태로 부착 형성된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.The center pad of claim 1, wherein any one of thermosetting and thermoplastic adhesives is attached to a polyimide-based film in the form of a tape or a sheet in order to stabilize the chip to be mounted. Laminated chip package having a. 제4항에 있어서, 상기 필름이 없이 열경화성 및 열가소성 접착제 중의 어느 하나를 테이프 형태 및 쉬트(sheet) 형태의 어느 한 형태로 부착 형성된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.5. The laminated chip package of claim 4, wherein any one of the thermosetting and thermoplastic adhesives is formed in the form of a tape or a sheet without the film. 제1항에 있어서, 상기 기판이 실장될 칩의 에티브 영역이 상기 패턴닝된 면에 접착되는 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.The laminated chip package of claim 1, wherein an active region of a chip on which the substrate is to be mounted is adhered to the patterned surface. 제1항에 있어서, 상기 기판상이 전기적 연결부분이 적어도 한 면은 코팅된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.2. The laminated chip package of claim 1, wherein at least one side of the substrate is coated with an electrical connection portion on the substrate. 제7항에 있어서, 상기 다른 한면은 범프를 이용한 플립칩을 적용한 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.8. The multilayer chip package of claim 7, wherein the other surface is a flip chip using bumps. 제1항에 있어서, 상기 기판을 중심으로 양면 실장된 칩들의 패키지 단위 면적당 집적도를 높이기 위하여 상기 각 칩들의 한 부분이 겹치도록 된 것을 특징으로 하는 센터 패드를 갖는 적층 칩 패키지.The multilayer chip package of claim 1, wherein a portion of each chip is overlapped to increase the degree of integration per package unit area of the chips mounted on both sides of the substrate.
KR1019950033124A 1995-09-29 1995-09-29 Stack chip package having center pad KR0152576B1 (en)

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