TW437019B - Improved wiring substrate with thermal insert - Google Patents

Abstract

A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In a specific embodiment, the wiring substrate is a laminated printed wiring board with the thermal expansion reduction insert in a layer next to an outer layer to which the integrated circuit is joined (mounted). In a further embodiment the thermal stress reduction insert is a CIC insert or a copper-molybdenum insert. In an alternative embodiment, the wiring substrate is a thin film substrate or a VLSI substrate.

Description

Γ Λ〇7 Q 1 9 -1 No. 88114105_Year Month Η Amendment V. Description of the Invention (1) The patent application for this application is from August 19, 1998, and was applied for by Sundar Kamath and David Chazan (US agent file No. 01 9 9 0 5-〇〇1 9 0 0), whose title is "Insulating flip chip or ball grid array to reduce interconnect stress due to thermal mismatch", incorporated herein by reference D This application is in line with U.S. Practical Application No. 6 0 1 0 9 7 0 6 6 and the title is 11 Insulating Chip or Ball Grid Array for Reducing Interconnection Stress Due to Thermal Mismatch, ', by Sundar Kamath, David Chazan: FTI Huomen Bailin (US agent file number 0 1 9 0 5-0 0 1 9 1 0) apply at the same time, incorporated herein by reference. Background of the invention

Manufacturers of circuit substrates such as printed circuit boards (" printed circuit boards s π), wafer carriers (and VLS I substrates, etc.) face a major problem in controlling the materials between the substrates (in the case of laminated substrates) and Thermal expansion stress between the base material and the components mounted on the base. Thermal stress can occur in at least two cases. One is when a thermal gradient is present. Higher temperatures in an area of the base, such as a heat source The following can cause thermal expansion (cold area relative to the substrate), and even the base system is caused by a single material. The impact of this situation can often be mitigated by slowly changing the temperature, so the thermal gradient is reduced. The second case is: when used with Materials with different coefficients of thermal expansion ("coefficient of thermal expansion"). Therefore, when high temperature changes, a material expands and contracts at a different rate than other materials (typically expressed at the temperature of the speed, without unit coefficients such as mm / mm). The coefficient of thermal expansion can cause various problems, regardless of the rate at which the material is heated or cooled. Together or attached together in other situations, heat will be generated when the temperature changes

O: \ 60 \ 600l8.ptc Page 6 Γ 4370 1 9 _Case No. 88114105_year month day__ 5. Description of the invention (2) Stress. To reduce the stress, this stress can cause the material to deform (warp) or even crack. For example, printed circuit boards are typically formed by laminating several layers of different materials together. A conductive layer, for example, a patterned copper layer formed according to the required circuit outline is separated and laminated to it by a dielectric layer, which provides electrical insulation between the conductive layers. Dielectric layers are typically polymeric resins, such as epoxy resins, including fiber-reinforced resins. Dielectric layers often have a coefficient of thermal expansion of about 50 to 70 ppm / ° C and metals used in conductive layers have a coefficient of thermal expansion of about 16 to 17 p p m / ° C. Therefore, a heat source placed on a printed circuit board or similar circuit substrate can create thermal stress. The increased complexity of contemporaneous integrated circuits affects self-heating stresses in many ways :; problems that occur. First, a very large integrated circuit (" V L S I u) high component count wafer (often referred to as a single wafer) can generate more heat than a wafer with a lower component count. The shrink size of components on a wafer means that heat is often concentrated in smaller areas. Some 1Cs produce more than 10 w / cm2. Shrinking size also means that * the traces on the wafer are finer and the contact pads on the wafer also have finer pitches, which is not mentioned: the number of contact pads has substantially increased. Finally, in many cases, the overall size of V L S I wafers has increased. Increasing the size results in a larger total expansion or contraction, which can result in higher thermal stress. Various industrial technologies have been developed to address the finer contact pitch and increase the number of contacts. The implementation includes a ball grid array (π ball grid arrays "), which is a raised block with a row, typically Packaging wafers with solder spots on one surface of the package. The package may include a wafer carrier or lead frame

Q: \ 60 \ 60018.ptc Page 7 437 0 1 9 _Case No. 88114105_Year Month __ V. Description of the invention (3). The chip is connected to the carrier and the IC contact point has an IC chip to the ball Grid array of balls. Another example is called "M flip-chip", which is similar to ball grid array packaging because: the bumps are typically solder, eutectic (eutectic) or conductive adhesive formed on the contact pads on the IC wafer. This wafer is then flip-chiped onto the circuit substrate and joined. M flip-chip is usually retained to describe the type of direct wafer attachment, even though it is very similar to the packaged ball grid array method. Unfortunately, the insulation coating of the IC may be caused by a material, such as plastic, ceramic, or semiconductor, which has a different coefficient of thermal expansion than any material in the circuit substrate. To complicate things, the finer pitch of the contact array typically means that a thinner circuit pattern must be used on the circuit substrate. Thinner wires are less robust than thicker wires and are therefore more likely to break when subjected to stress. Similarly, if the shear stress develops between IC and the substrate, the smaller solder ball will have a very small strength that does not resist the stress (including work hardening) and may fail at the joint or may crack. A particularly non-negligible view of this type of failure is that electrical contact can be established at one temperature and not at other temperatures. Cracks or ruptures of electrical paths due to thermal expansion and contraction " half pieces " combined and separated15 One technique used to improve the reliability of ball grid arrays attached to printed circuit boards is underfill ball grids Array. Underfilling typically involves applying liquid to the (each) edge of the ball grid array, and the liquid is wicked under the ball grid array by capillary action. The liquid is then cured, or cured, such as by a polymerization process, for example, " glue " an array of ball grids onto the surface of a printed circuit board. The thermal expansion coefficient of the underfill material is typically selected to match the thermal expansion coefficient of the typical foot solder of the material that causes the ball grid array ball. Matching these thermal expansion coefficients to reduce the underfill material ball grid array bursting the circuit substrate surface,

O: \ 60 \ 60013.ptc Page 8 · '4 37 0 1 9 _Case No. 88114105_Year Month Day__ V. Description of the invention ¢ 4). The opportunity to damage solder joints or rupture solder balls. Unfortunately, the thermal expansion coefficient of the underlying material may not be a good match for the thermal expansion coefficient of the integrated circuit or the thermal expansion coefficient of the printed circuit board. Another technique used to reduce the difference in thermal expansion coefficient between the integrated circuit and the circuit substrate is to incorporate a thermal expansion coefficient matching layer in the laminated structure of the printed circuit board. The thermal expansion coefficient matching layer usually provides a thermal expansion coefficient that is closer to the thermal expansion coefficient of the integrated circuit. It typically includes a silicon wafer. The thermal expansion coefficient matching layer is typically a sheet of low thermal expansion coefficient material, such as 64% Fe / 3 6% Ni (— Generally known as invariable steel (nINVAR " TM)) or molybdenum, clad with copper plating. The laminated layer is typically provided as a foil. This foil is patterned according to the required circuit pattern or is mostly unformed for use as a ground plane. Copper-invariant steel-copper foil is generally referred to as "CIC 11" Foil. These foils usually extend across the entire laminate. What's shocking is that low thermal expansion materials such as CIC or copper / molybdenum are quite expensive compared to standard copper foils. Therefore, there is a need to reduce thermal stress on circuit substrates. Neutralizes the failures caused by the combination of integrated circuits and circuit substrates. It is more intended to reduce failures without causing other unwanted results. SUMMARY OF THE INVENTION The present invention provides circuit substrates with reduced thermal expansion. Circuit substrates For example, laminated printed circuit boards, thin film circuits, lead frames or wafer carriers accept integrated circuits such as die, flip chip, or ball grid array packaging. The circuit substrate has thermal expansion to reduce the thermal expansion of the insert near the integrated circuit In the stress area, in a specific embodiment, the thermal expansion reducing insert extends a selected distance from the edge (s) of the integrated circuit attachment area , And in another specific embodiment, it stops for a period from the edge of each circuit attachment area

0: \ 60 \ 60018.ptc Page 9 1 '43701 9 _Case No. 88114105_Year Month Day__ V. Description of the invention (5). The selected distance. In a further specific embodiment, the thermal expansion area is substantially equal to the integrated circuit attachment area, the thermal expansion reducing insert reduces the thermal expansion of the circuit substrate in the area connected to the integrated circuit, thereby reducing the circuit substrate / Thermal stress between groups of integrated circuit assemblies. In a specific embodiment A, the circuit substrate is a laminated printed circuit board having a thermal expansion reducing insert in a layer close to the outer layer (connecting (mounting) the integrated circuit thereto). In another embodiment, the thermal expansion reducing insert is a C IC insert or a copper / molybdenum insert. In alternate embodiments, the circuit substrate is a thin film substrate or a VLSI substrate. These and other specific embodiments of the present invention, as well as their advantages and features, are described in more detail with the following text and accompanying drawings. Brief Description of the Drawings Figure 1 A is a simplified cross-sectional view of a conventional single-layer printed wiring board substrate; Figure 1 B is a simplified cross-sectional view of a conventional 4-layer printed circuit board substrate with an attached IC; Figure 2 A is a low thermal expansion coefficient A simplified cross-sectional view of a foil; Figure 2B is a simplified cross-sectional view of a low thermal expansion coefficient insert in a metal foil according to the present invention; Figure 3 is a specific embodiment of the present invention having a printed circuit board mounted in accordance with the present invention. Multilayer printed circuit board with low thermal expansion coefficient insert below the IC; Figure 4 A is a simplified top view of a printed circuit board with a mounted IC, for example: thermal expansion stress area; Figure 4 B is a specific embodiment according to the present invention , A simplified top view of a laminate having a patterned low thermal expansion coefficient conductive insert; and

O: \ 60 \ 6OO13.ptc Page 10 437 Ό 1 9 Correction_ cable number 88114105 V. Description of the invention (6) Figure 5 is a multi-chip module mounted on a printed circuit board according to another embodiment of the present invention Simplified face map. Description of Specific Embodiments The present invention provides an article having improved thermal stress characteristics for use in a circuit substrate and a method for making the same. By way of example only, manufactured substrates include a printed-electrode carrier 'VLSI substrate, a thin-film substrate, a 1C such as a ball grid circuit board array or a microsphere grid array package or the like and a substrate with C-attached equipment. IC components may be chip-on-chip, packaged ball grid arrays are only microsphere grids, and column elements' have wire bonding pads; [c, etc. and can be connected to the substrate through any of various die attachment methods, such as Those skilled in the art 'include solder die attachment, flip chip and ball grid array solder die attachment such as controlled shrink wafer bonding (" C 4'_). FIG. 1A is a simplified cross-sectional view of a conventional high-density printed circuit board partial laminate. The local laminate is formed of a single layer of insulating material, such as epoxy resin, and sold under the name of National Electrical Manufacturers Association (NEMA) aFR4TM or FR5TM. ^ Sold each of copper sheets 1 4 and 16 to the insulating sheet. The upper surface J 8 and the lower surface * of the board "transfer the required conductor pattern 2 2 to the copper sheet, for example, via photolithographic etching method" are well known in the art. The laminate may have a conductor on only one side, or all sides, and a pattern formed on both sides, and other features such as through-hole separation. The two-layer laminate is typically laminated together to form a multilayer printed circuit. J Figure 1B is a simplified cross-sectional view of a four-layer printed body 30 according to a specific embodiment of the present invention (the number of each layer refers to the number of metal layers and the number of non-local laminate sheets). Three dielectric sheets 32 are laminated, such as FR4TM sheet to form a laminated printed circuit board.

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Page 11; 43701 9 _Case No. 88114105_Year Month Date__ V. Description of the invention (7) The surface 38 has a patterned metal layer, which includes (wire) 40 and contact pads 42. Connect the IC device 4 to the contact pad. In this example, the IC device is a simplified representation of a ball grid array or a micro ball grid array, but it can replace other types of components, such as flip-chips or dies attached on the opposite side. As described above, the second patterned metal layer 46 is formed between the first and second dielectric layers 32 and 34. The patterned metal layer includes a first portion 48, such as a copper conductive layer and a second portion 50 of the intermediate thermal expansion material. The intermediate thermal expansion layer is a layer of material that has a thermal expansion coefficient that is closer to the thermal expansion coefficient of I C 4 4 than the thermal expansion coefficient of printed circuit boards. For example, if IC is a VLSI silicon wafer made of plastic, the silicon wafer has a thermal expansion coefficient of about 3 ppm / ° C. Packaging plastics typically have a much higher coefficient of thermal expansion, but because they are plastic, they can deform in response to thermal stress. The thermal expansion coefficient of the dielectric layer of a printed circuit board is typically between about 50 to 70 ppm / ° C and the typical copper layer The thermal expansion coefficient is about 16.6 ppm / ° C. For example, the key has a thermal expansion coefficient of about 5 ppm / ° C, which is between the thermal expansion coefficient of the IC and the thermal expansion coefficient of the printed circuit board, so it can be The operation is an intermediate thermal expansion layer, like other metals such as tungsten or various stainless steels. Therefore, blending molybdenum into the second part of the second patterned metal layer can reduce the thermal expansion of the printed circuit board in the second area and reduce the The thermal expansion between the IC and the printed circuit board in the adhesion area 5 2 is not coordinated. It should be understood that "the metal layer formed by the pattern" does not have to form a pattern, especially in the region under the "IC 11". Although the middle The thermal expansion material may have a coefficient of thermal expansion between the IC and the printed circuit board, but it may also have a coefficient of thermal expansion smaller than that of the IC, for example, INVA RTM has approximately Coefficient of thermal expansion of 1 p p m / ° C. Not used

O: \ 60 \ 60018.ptc Page 12 437 0 1 9 _ Case No. 88I14I05_Year Month Day__ V. Description of the invention (8) ^ Transformed steel or similar materials in the second area can compensate for the thermal expansion in other areas And balance thermal stress. A technique has been tested, that is: # 合 铜-恒 钢-铜 (" C I C ") foil as the intermediate conductive layer throughout the entire conductive layer. However, the use of a low thermal expansion layer throughout the conductive layer of the printed circuit board can cause undesirable results. First, reducing the thermal expansion characteristics of one layer does not necessarily match the thermal expansion characteristics of each layer or mounting component. Referring to FIG. 1B, it can be seen that matching the thermal expansion coefficient of I C 4 4 to the combined attachment area 5 2 is required. For example, if the entire layer of the printed circuit board laminate is constant steel or C I C, the thermal expansion of I C may be higher than the thermal expansion of the printed circuit board. Therefore, thermal expansion can occur because the thermal expansion coefficient of one layer of the printed circuit board is too low rather than too high. An entire layer with a low coefficient of thermal expansion in the second laminate can cause other problems, such as warping or cracking. In fact, the printed circuit board has a composite thermal expansion coefficient, which is the approximate sum of the thermal expansion coefficients of the laminate and each layer, which is adjusted by the rigidity and strength of each layer. For example, if a thin CIC layer is sandwiched between two thick FR 4TM layers, it is possible that the CIC layer is stretched or otherwise compensates for the difference in coefficient of thermal expansion > This phenomenon can cause warping of the laminated assembly < Cracking and / or cracking of the dielectric or metal layer, especially if the metal layer is a relatively brittle material (such as copper). Finally, compared to copper, alloys such as molybdenum and constant steel are quite expensive, and therefore need to be reduced. These materials are used and they are usually not good conductors of electricity or heat like copper. The present invention avoids these problems by providing an intermediate thermal expansion stress relief insert in the area of the IC or other component installed. Therefore, the thermal expansion coefficient of IC may at least partially match the underlying printed circuit board, or the intermediate thermal expansion layer may compensate for the thermal expansion of the layer in areas far from IC. For example, if not

O: \ 60 \ 600l8.ptc Page 13! '43701 9 _ Case No. 88114105_year month day_ί ± ^ ._ V. Description of the invention (9). ^ Variable steel, CIC or other low thermal expansion materials exist in Below the IC, but not throughout the internal dielectric layer, the low coefficient of thermal expansion material can at least partially compensate for the remaining higher coefficient of thermal expansion (than IC) portion of the layer. Therefore, even if the material with low thermal expansion coefficient is not thermally expanded like IC, the relatively high thermal expansion material in the same layer at least partially compensates for the difference in thermal expansion coefficient, resulting in the thermal expansion stress region more closely matching the thermal expansion coefficient of IC. Figure 2A shows a simplified cross-sectional view of an intermediate thermal expansion material 60, such as a constant steel or molybdenum, coated or plated with one of the copper layers 62, 64. If the second part of the second metal layer is patterned, especially if the second part will carry a telecommunications signal, one or both surfaces of the intermediate thermal expansion material need to be plated or coated with copper. The total thickness of the material is between about 6 to 16 mils (mi) and the copper layer is large; about 1.25 mils thick, but these thicknesses are provided by way of example only. In some instances, it may be necessary to select a relatively thick intermediate thermal expansion material, i.e., 16 mils or more to provide sufficient stiffness in the thermal expansion region. In these examples, the conductive layer incorporating the intermediate thermal expansion material should preferably be a ground plane, a power plane, or other conductive plane (which uses thicker gold shavings). Figure 2B is a simplified cross-sectional view of a metal layer 65 for use in a printed circuit board laminate according to the present invention. The plating or cladding 67 includes a copper portion 69 and an intermediate thermal expansion portion 71. A layer of copper 73 is plated or coated on the lower layers. Therefore, the entire metal layer can be manufactured according to the conventional photolithography / etching technique, and if necessary, it is suitable for touching an intermediate thermal expansion material. In this way, good conductivity is maintained between the first and second parts of the conductor layer. FIG. 3 is a simplified cross-sectional view of a printed circuit board 80 according to another embodiment of the present invention. Patterned or unformed metal layers are not shown). Embedding thermal expansion stress compensation insert 8 2 in printing

O: \ 60 \ 60018.ptc Page 14 ^ '4370 1 9 _ Case No. 88114105_ 生 _ ^ _ Θ_ CORRECTION_ V. Description of the invention (10). ^ The dielectric layer 8 of the circuit board laminate. Although the insert is shown on the inner layer, based on the electrical contact to 1C44 or other considerations through the outer layer, the insert can be placed in the outer layer 86. For example, the insert is constant steel, molybdenum, stainless steel Or other metal, when used in conjunction with an epoxy-containing dielectric laminate, this metal has a coefficient of thermal expansion that is less than that of the dielectric material in the printed circuit board layer, preferably less than about 9 ppm / ° C. The dielectric layer 84 is split and formed into a pocket to receive the inserts 82 in the two halves 83, 85 of the dielectric layer, which are then laminated together. In this specific embodiment, the insert does not form a patterned conductive layer, and does not even need to be a conductor. The insert may be achieved by other materials, such as silicon, including polycrystalline silicon, fused silica, boron carbide, and carbonization. Silicon, aluminum-containing ceramics, etc. Fig. 4A is a simplified top view of I C 4 4 mounted on a printed circuit board substrate 30. I C is a rectangle with long sides 4 5 and short sides 4 7. The dotted line 51 represents the thermal expansion compensation area, but it should be understood that this area may lead to the perimeter of IC 4 or even within the perimeter of IC. Usually the thermal stress compensation area does not extend more than about 8 mm from the edge of the installed IC, but the size is selected according to several standards, including the relative thermal expansion coefficient of the thermal expansion material of the IC, printed circuit board, and the rigidity of each layer And elastic. Fig. 4B is a simplified diagram of a metal layer 46 having a pattern formed by a part of the intermediate thermal expansion region 50 and the copper region 48. The metal layer is a metal layer or foil according to the above-mentioned FIG. 2B, and is formed into a pattern to create a trace 8 8 in the thermal expansion compensation area, indicated by a dotted line 51. These traces usually extend into the thermal expansion compensation area along the long axis of IC shown in FIG. 4A, providing excellent thermal compensation effects. In addition to thermal expansion compensation, traces can remain long or divergent, as shown. FIG. 5 shows the second IC 92 mounted on the printed circuit board 94.

O: \ 60 \ 60018.ptc Page 15 43701 9 _ Case No. 88114105_ Year Month Day __ '' V. Description of the invention (11) '_ A simplified sectional view of the first I C 9 0. The second IC has a thermal expansion reduction insert 9 6, and the printed circuit board also has a thermal expansion reduction insert 9 8. The thermal expansion implant 9 6 in the second IC 9 2 may be a heat-matching material such as molybdenum. Or thermal compensation materials such as constant steel. Although the thermal expansion reducing implant 9 8 in the printed circuit board 9 4 mainly reduces the uncoordinated thermal expansion stress between the printed circuit board 9 4 and the second IC 92, the thermal expansion in the second IC 9 2 reduces the insert 9 6 may Reduce the thermal stress in the IC chip (not shown) in the second IC, and reduce the thermal expansion uncoordinated stress between the first IC 90 and the second IC 92. Because of different operating temperatures or because of different thermal expansion coefficients of the two components, thermal expansion stress inconsistencies can occur between the first and second ICs. The thermal expansion reduction insert 96 in the second IC can reduce thermal stress in the IC wafer by adding strength to the IC wafer or by maintaining or loading the IC wafer in compression. For example, if the insert is a constant steel and a Shiba IC chip is mounted on the constant steel insert, when the assembly is heated, the silicon wafer will easily expand beyond the constant steel. Therefore, the insert can hold the IC wafer in compression. As described above, the printed circuit board is prone to expand beyond the constant steel or I C, and thus a tensile-type stress is generated in the I C. The compressive stress provided by the insert will work against this tensile stress and may balance the individual stresses so that the wafer in the IC has little, if any, thermal stress at the operating temperature. In addition, the thermal expansion reducing insert 96 in the second IC 92 can reduce the stress including the binding force between the first IC90 and the second IC92. For example, the first 1C may be a thin film substrate on ceramic or sapphire. In this example, the thermal expansion coefficient of the first IC is the thermal expansion coefficient of the second IC, for example, if the VLS substrate of the second I d 'silicon. Various specific embodiments of the present invention have been fully described, other equivalents or alternatives

O: \ 60 \ 600IS.ptc Page 16 BU 43701 9 _ Case No. 88114105 _ Month and Day __ 5. The structure and method of the invention description (12) _ are clearly visible to those who are usually skilled in the art. For example, although various embodiments have been described with reference to laminated layers of epoxy material, it should be understood that other materials may be used in one or more of the laminated layers. Other materials may include metal layers, such as those used in wafer carriers and lead frames, glass-filled fluoropolymer layers, and alumina-containing ceramic layers, to name just a few. Therefore, the scope of the present invention should not be affected by the above. It is limited by specific specific embodiments but rather by the following patent application scope.

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Claims (1)

4370 1 9 Case No. 88114105 Amendment M ': Six' application patent scope 1. A multilayer circuit edge has an outer surface and an inner surface outer layer, the outer surface has an attachment area for mounting a integrated circuit on the outer surface And a conductive layer laminated on the inner surface of the outer layer, the conductive layer having a first region (which has a first thermal expansion coefficient) and a second region (which has a second thermal expansion coefficient), the second thermal expansion coefficient is less than A coefficient of thermal expansion, where the second region corresponds to the attachment region. 2. The multilayer circuit substrate according to item 1 of the patent application scope, wherein the first region of the conductive layer comprises copper and the second region of the conductive layer comprises a metal having a thermal expansion coefficient of less than about 9 p p m / ° C. 3. For a multilayer circuit substrate according to item 2 of the patent application, the second region of the conductive layer contains I mesh or an alloy with approximately 64% iron and 36% iron. 4. For a multilayer circuit substrate according to item 1 of the patent application scope, wherein the attachment area has long and short sides, and the conductive layer is patterned to form traces, these traces mainly extend parallel to the long sides of the attachment area. 5. The multilayer circuit substrate according to the first and the first patent applications, wherein the conductive layer is configured as a ground plane or a ^ _: 'plane. 6. A multi-layer circuit base includes: an outer surface and an inner surface; an epoxy-based dielectric material laminated layer of a cover '__, the outer surface having an attachment area for mounting integrated circuits outside On the surface; and a conductive layer laminated on the inner surface of the laminated layer, the conductive layer having a first region containing copper and a second region having a second thermal expansion coefficient of less than about 9 ppm / ° C, where t The second area corresponds to the attachment area. O: \ 60 \ 6OO18.ptc Page 19 Λ370 1 9 _ Case No. 88114105 #; _3_ Amendment 6. Scope of patent application., _ 7. — A multilayer metal foil for use in circuit substrates, the foil includes: A foil comprising a first part having a thickness of 铪; a foil of a second part comprising a metal having a thermal expansion coefficient of less than about 9 ppm / ° C, and a second part having a second thickness, the second thickness being substantially First-class and low-conductivity layer covering the first part and the second part with the first thickness, and mechanically and electrically coupling the first part to the second part 8 The low-conductivity layer includes copper and the second portion includes an alloy of 64% 6% nickel or molybdenum. 9. As claimed in claim 7, wherein the total thickness of the foil is between about 6 and 16 mils. 1 0. — Kind of integrated circuit: 栝: a semiconductor wafer with a first thermal expansion edge ^ :; a package with a ball array surface and a wafer attachment surface, which is composed of the wafer attachment surface to receive a dipole integrated circuit, and the semiconductor wafer is configured In the package, 'is between the ball array surface and the wafer attachment surface; and a thermal expansion reduction insert configured in the package is between the semiconductor wafer attachment surface, the thermal expansion reduction insert having a third coefficient of thermal expansion The second thermal expansion system is smaller than the first thermal expansion coefficient. 11. The integrated circuit according to the patent application, wherein the thermal expansion reduction insert includes: approximately ❹,., And 36% of the alloy. 1 2. An electronic combination. Including: a printed circuit substrate having a surface with a wafer attachment area, a dielectric layer having a first thermal expansion coefficient and a first thermal expansion reduction insert phase __Ρ O: \ 60 \ 60018.ptc Page 20 4370 1 9 _ Case No. 88114105_Year_Month__ Sixth, the scope of patent application _-For the wafer attachment area, the first thermal expansion reduction insert has a second thermal expansion coefficient, the first The two thermal expansion coefficients are smaller than the first thermal expansion coefficient; the first integrated circuit is mounted on a surface of a printed circuit-based material in a wafer attachment region, and the first integrated circuit includes a semiconductor having a third thermal expansion coefficient A wafer and a second thermal expansion reducing insert having a fourth thermal expansion coefficient, the fourth thermal expansion coefficient is smaller than the third thermal expansion coefficient, and the second wafer attachment area is on the surface of the first integrated circuit; and is mounted on the first integrated circuit A second integrated circuit on the second wafer attachment area of the circuit. 1 3. According to the combination of item 12 in the scope of patent application, wherein the first integrated circuit is mounted on and in a printed circuit substrate having a ball array, and the second and integrated circuits are mounted on a first substrate having a ball array. On an integrated circuit. O: \ 60 \ 60018.ptc Page 21