JP2000049254A - Chip-sized package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the difference between the coefficients of thermal expansion of a chip-sized package and a printed wiring board on which the package is mounted by increasing the coefficient of thermal expansion of the package as a whole, by firmly sandwiching the wafer at both lower and upper surfaces and fixing a resin having a larger coefficient of thermal expansion than a semiconductor wafer made of an epoxy resin, etc. SOLUTION: Two sheets 12 and 12' of copper foil having a larger coefficient of thermal expansion than an epoxy- or polyimide-based semiconductor wafer 1 has are respectively laminated upon the upper and lower surfaces of the wafer 1. Then pads 4 and 4' for solder bumps are formed by etching off unnecessary parts from the foil 12 and 12', and connection via holes 3 and 3' are formed through the foil 12' to the bonding pads 11 and 11' of the wafer 1. Thereafter, solder bumps 5 and 5' are respectively mounted on the pads 4 and 4' by electroless-plating the via holes 3 and 3' with copper for electrical connection and applying a solder resist 6. Therefore, the fracture of solder junctions can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package and, more particularly, to the elimination of breakage of a solder joint caused by a difference in the coefficient of thermal expansion between a printed wiring board to be mounted and a chip size package.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional chip size package. A conventional chip size package will be described with reference to FIG. In FIG. 3, 1 is a semiconductor wafer, 2 is a resin layer,
3, 3 'are connection vias, 4, 4' are solder bump pads, 5 and 5 'are solder bumps, and 6 is a solder resist for protection. As the semiconductor wafer 1, a silicon wafer is generally used. A resin layer 2 such as an epoxy-based or polyimide-based resin is formed on the terminal forming side of the semiconductor wafer 1, and connection vias 3 and 3 ′ for making an electrical connection with the semiconductor wafer 1 are formed in the resin layer 2. 2, pads 4 and 4 'for solder bumps are formed, and solder bumps 5 and 5' are mounted on the pads 4 and 4 'and the surface is protected by a solder resist 6, thereby forming a chip size package. Here, the resin layer 2 is not formed for changing the coefficient of thermal expansion, but merely for protecting and insulating the semiconductor wafer 1.

The coefficient of thermal expansion of the chip size package thus formed is almost equal to the coefficient of thermal expansion of silicon.
The coefficient of thermal expansion of silicon is 3.5 ppm / ° C. On the other hand, a general printed wiring board on which this chip size package is mounted is glass epoxy which is a composite of epoxy resin and glass cloth, and has a coefficient of thermal expansion of 15 to 18 p.
pm / ゜ C. As described above, since there is a difference in the coefficient of thermal expansion between the chip size package and the printed wiring board on which the chip size package is mounted, simply mounting the chip size package on the printed wiring board causes a break in the solder joint. There is a fear that the processing is performed as shown in FIG. 4 to avoid this. In FIG. 4, 5 and 5 'are solder bumps, 7 is an underfill, 8 is a printed wiring board, and 10 is a chip size package. After connecting the chip size package 10 to the printed wiring board 8 with the solder bumps 5, 5 ',
An underfill 7 is provided between the chip size package 10 and the printed wiring board 8. Underfill 7
Is so-called resin filling.

[0004]

As described above, since there is a difference in the coefficient of thermal expansion between the chip size package 10 and the printed wiring board 8 on which the chip size package 10 is mounted, there is a risk that the solder joints may be broken. There is an underfill 7 to avoid this danger. However, in order to perform underfill, equipment for the underfill is also required, and the time for the underfill is also required, which increases the cost. Furthermore, when underfilling is performed, there is a problem that it is difficult to replace parts of a chip size package. The present invention has been made to solve the above-described problem, and has a small difference in coefficient of thermal expansion from a printed wiring board to be mounted, and a chip size package that does not require an underfill when mounted on a printed wiring board. The purpose is to provide.

[0005]

According to the present invention, in order to achieve the above object, a resin having a higher thermal expansion coefficient than a semiconductor wafer such as an epoxy or polyimide is sandwiched from above and below the semiconductor wafer and fixed. The thermal expansion coefficient of the entire chip size package is increased, and the difference from the thermal expansion coefficient of the printed wiring board to be mounted is reduced. At this time, the ratio of the thickness of the semiconductor wafer to the thickness of the upper or lower resin layer sandwiching the semiconductor wafer is appropriately 1: 5. At this time, the semiconductor wafer is thinned (0.1 mm to 0.2 mm).
2mm), the resin layer to be sandwiched can be made thinner,
Finish the entire chip size package thinly.

[0006]

FIG. 1 is a sectional view of a chip size package showing one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor wafer, which is a silicon wafer in this embodiment. The original thickness is 0.4 to 0.6 mm, which is reduced to about 0.2 mm by polishing or the like. is there.
2, 2 'are resin layers, 3, 3' are connection vias for making electrical connection with bonding pads of the semiconductor wafer 1,
Reference numerals 4 and 4 'denote pads for mounting the solder bumps 5 and 5', and reference numeral 6 denotes a solder resist. Semiconductor wafer 1
The reason for reducing the thickness is that the amount of the resin layers 2 and 2 ′ can be reduced when the thermal expansion coefficient of the entire chip size package is set to a predetermined value. Conversely, the thickness of the resin layer 2, 2 'is determined from the thickness of the semiconductor wafer 1. In the present embodiment, the required thermal expansion coefficient was obtained by setting the thickness of the semiconductor wafer 1 to about 0.2 mm and the thickness of each of the resin layers 2 and 2 ′ to about 1.0 mm.

FIG. 2 is a view showing a manufacturing process of a chip size package according to the present invention. In FIG. 2, 1 is a semiconductor wafer, 11 and 11 'are bonding pads of the semiconductor wafer 1, 12 and 12' are copper foil with resin, 3 and 3 'are connection vias, and 4 and 4' are pads for solder bumps. 5 'is a solder bump, and 6 is a solder resist.

The manufacturing process of the chip size package according to the present invention will be described with reference to FIG. First, the semiconductor wafer 1 is thinned by polishing or the like. The portion where polishing or the like is performed is the portion indicated by the broken line in FIG. 2A, and the result of thinning is FIG. 2B. Subsequently, resin-coated copper foils 12, 12 'are laminated on and under the semiconductor wafer 1 (FIG. 2C). Unnecessary copper foil is removed from the copper foil with resin 12, 12 'by etching. Thus, pads 4 and 4 'for solder bumps are formed (FIG. 2D). Next, connection vias 3 and 3 ′ reaching the bonding pads 11 and 11 ′ of the semiconductor wafer 1 are provided by a laser, and the connection vias 3 and 3 ′ are further provided.
Electroless copper plating is applied to 3 'to make electrical connection (Fig. 2
(E)). Finally, a solder resist 6 is applied, and the solder bumps 5, 5 'are mounted on the pads 4, 4' for the solder bumps (FIG. 2 (F)).

When it is necessary to further increase the thickness of the resin layers 2 and 2 ', it is necessary to make the resin layers 2 and 2' thicker as shown in FIGS.
The required thickness can be obtained by repeating the above steps. In this embodiment, the resin layers 2 and 2 'are formed by laminating the copper foils 12 and 12' with resin. However, a method such as adhesion of a resin tape and coating of a liquid resin may be used.

In this embodiment, a silicon wafer is used as a semiconductor wafer and a glass epoxy is used as a substrate for a printed wiring board. However, if a resin having an appropriate coefficient of thermal expansion is selected, other types of semiconductor wafers can be used. It can also be applied to printed wiring boards.

According to the present invention, a resin having a higher thermal expansion coefficient than that of a semiconductor wafer such as an epoxy-based or polyimide-based resin is sandwiched and fixed from above and below the semiconductor wafer to form a chip-size package. Since the difference between the coefficient of thermal expansion and the coefficient of thermal expansion of the printed wiring board on which the chip size package is mounted is reduced, there is no danger of the solder joint breaking even without underfill. Therefore, no equipment and time are required for underfill, which contributes to cost reduction. Further, since there is no underfill, it is easy to replace parts of the chip size package, which contributes to cost reduction in terms of maintenance. Since the semiconductor wafer is evenly sandwiched and fixed from above and below the semiconductor wafer, this chip size package does not generate distortion or warpage due to a temperature change or the like.

[Brief description of the drawings]

FIG. 1 is a sectional view of a chip size package showing one embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a chip size package according to the present invention.

FIG. 3 is a sectional view of a conventional chip size package.

FIG. 4 is a cross-sectional view when a conventional chip size package is mounted on a printed wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2, 2 'Resin layer 3, 3' Connection via 4, 4 'Pad for solder bump 5, 5' Solder bump 6 Solder resist 7 Underfill 8 Printed wiring board 10 Chip size package 11, 11 'Semiconductor wafer Bonding pads 12, 12 'Copper foil with resin

Claims (3)

[Claims] 1. A chip size package characterized by being sandwiched and fixed from above and below a semiconductor wafer with a resin having a higher thermal expansion coefficient than a semiconductor wafer such as an epoxy or polyimide semiconductor wafer. 2. The method according to claim 1, wherein the ratio of the thickness of the semiconductor wafer to the thickness of a resin sandwiching the semiconductor wafer from above or below is about 1: 1:
The chip size package according to claim 1, wherein the number is 5. 3. The semiconductor wafer has a thickness of about 0.1 m.
The chip size package according to claim 1, wherein the size is from m to 0.2 mm.