JPS62234350A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62234350A JPS62234350A JP7781486A JP7781486A JPS62234350A JP S62234350 A JPS62234350 A JP S62234350A JP 7781486 A JP7781486 A JP 7781486A JP 7781486 A JP7781486 A JP 7781486A JP S62234350 A JPS62234350 A JP S62234350A
- Authority
- JP
- Japan
- Prior art keywords
- interconnection
- layer
- bump electrode
- wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 description 3
- 239000010953 base metal Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
本発明は、半導体基板上に絶縁膜を介して積層さ作る複
数層の配線を有し、その配線に接続されるバンプ電極が
設けられ、そのバンプ電極が絶縁基板上の導体に固着さ
れる半導体装置の製造方法に関する。The present invention relates to a semiconductor having multiple layers of wiring formed on a semiconductor substrate by laminating them with an insulating film interposed therebetween, a bump electrode connected to the wiring, and a bump electrode fixed to a conductor on the insulating substrate. The present invention relates to a method for manufacturing a device.
多層配線を存し、ワイヤレスボンディング方式で絶縁基
板上に実装される半導体基板のバンプ電極は、従来最上
層の配線に下地金属膜を介してめっきにより設けられて
いたが、このようなバンプ電極は、その下に存在する配
線導体膜と酸化物のような無機絶縁物あるいは有機絶縁
物からなる層間絶縁膜との積層体との弾性率、熱膨張係
数の相違により剥離が生じやすく、断線の原因となる問
題があった。Bump electrodes on semiconductor substrates that have multilayer wiring and are mounted on insulating substrates using the wireless bonding method are conventionally provided on the top layer of wiring by plating through a base metal film. The difference in elastic modulus and coefficient of thermal expansion between the underlying wiring conductor film and the interlayer insulation film made of an inorganic insulator such as an oxide or an organic insulator causes peeling, which can easily cause disconnection. There was a problem.
本発明は、上述の問題を解決して絶縁基板上の導体と接
続されるバンプ電極のIA*などによって断線のおそれ
のない、信転性の高い半導体装置の製造方法を提供する
ことを目的とする。An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device with high reliability, which is free from the risk of disconnection due to IA* of bump electrodes connected to conductors on an insulating substrate. do.
本発明は、半導体基板上に絶縁膜を介して第一層目の配
線を形成する際、バンプ電極への配線も形成し、次いで
配線のバンプ電極部を露出させて層間絶&!膜、第二層
目以降の配線を交互に積層したのち、バンプ電極部の配
線上にバンプ電極を形成するもので、バンプ電極が半導
体基板の上に直接絶縁膜を介して形成されるため剥離の
起こることがなくなり、上述の目的が達成される。In the present invention, when forming a first layer of wiring on a semiconductor substrate via an insulating film, wiring to a bump electrode is also formed, and then the bump electrode portion of the wiring is exposed to separate the layers. After alternately laminating the film and the wiring from the second layer onward, a bump electrode is formed on the wiring in the bump electrode section.The bump electrode is formed directly on the semiconductor substrate via an insulating film, so there is no peeling. The above-mentioned purpose is achieved.
第1図は本発明の一実施例の半導体基板を示し、シリコ
ン基板1は上面は薄い酸化膜2で覆われている。この基
板1にはMOSFETあるいはバイポーラトランジスタ
などの半導体素子が集積されていて、その部分は厚い絶
縁膜3で覆われている。
次に、酸化膜2および絶縁膜3の上にM膜を蒸着し、パ
ターニングして第一層配&l14を形成する。
同時にこの配線を延長して素子部の外側にバッド電極5
を形成する。つづいて素子部を酸化膜、塗布膜などの層
間絶縁膜6により被覆し、配線4と同様に第二層配線7
を形成する0層間絶a膜6および配線7のためのFX着
膜のバターニングの際には、バッド″1i5の上の部分
は除去し、パッド電極を露出させておく、第二層配線7
とバンド電極5との接続は、第一層配線4に達するスル
ーホールを介して行われる。露出したバッド電極5の上
に、下地金属層を介してめっきなどによりはんだあるい
は金のバンプ電極8を形成する。最後にCVD法による
Sl、N、などからなるバンシベーシッン[99により
素子部を覆う。
第1図に示したような半導体基板は、このあとフェース
ダウンでのフリップチップ方式あるいはフェースアンプ
でのTAB方式なのでバンプ電極を絶縁基板あるいはテ
ープ上の導体に融着させて実装する。フェースダウンの
場合は、バンプ電極8の高さは素子部の高さより高くし
ておく。
【発明の効果]
本発明によれば、バンプ電極を多層配線の上層配線上に
設けないで半導体基板上の第一層配線の延長部上に設け
ることによってバンプ電極の下に弾性率、熱膨張係数の
異なる積層体が無くなるためβ線との接続部に生ずる応
力が小さくなり、接続部に招けるIAjllが阻止され
、ICチップなどを実装した半導体装置の信頼性を高く
することができる。FIG. 1 shows a semiconductor substrate according to an embodiment of the present invention, in which the upper surface of a silicon substrate 1 is covered with a thin oxide film 2. As shown in FIG. Semiconductor elements such as MOSFETs or bipolar transistors are integrated on this substrate 1, and this portion is covered with a thick insulating film 3. Next, an M film is deposited on the oxide film 2 and the insulating film 3 and patterned to form a first layer interconnection &l4. At the same time, extend this wiring and connect the pad electrode 5 to the outside of the element part.
form. Next, the element portion is covered with an interlayer insulating film 6 such as an oxide film or a coating film, and a second layer wiring 7 is formed in the same manner as the wiring 4.
When patterning the FX deposited film for the 0-layer insulation film 6 and wiring 7 that form the second layer wiring 7, the part above the pad "1i5 is removed to expose the pad electrode.
The connection between the band electrode 5 and the band electrode 5 is made through a through hole that reaches the first layer wiring 4. A solder or gold bump electrode 8 is formed on the exposed pad electrode 5 by plating or the like with a base metal layer interposed therebetween. Finally, the element portion is covered with a bancibasin [99] made of Sl, N, etc. by the CVD method. Since the semiconductor substrate shown in FIG. 1 is then mounted using a face-down flip-chip method or a TAB method using a face amplifier, bump electrodes are fused to an insulating substrate or a conductor on a tape. In the case of face down, the height of the bump electrode 8 is set higher than the height of the element section. Effects of the Invention According to the present invention, by providing the bump electrode not on the upper layer wiring of the multilayer wiring but on the extension of the first layer wiring on the semiconductor substrate, the elastic modulus and thermal expansion can be reduced under the bump electrode. Since there is no stack of layers with different coefficients, the stress generated at the connection with the β rays is reduced, IAjll is prevented from being induced at the connection, and the reliability of a semiconductor device mounted with an IC chip or the like can be increased.
第1図は本発明の一実施例による半導体装置の半導体基
板を示す斜視図である。
l:シリコン基板、2:酸化膜、3:絶縁膜、4:第一
層配線、5:パッド電極、6:N間絶縁膜、7:第二層
配線、8:バンプ電極、9:バフ第1図FIG. 1 is a perspective view showing a semiconductor substrate of a semiconductor device according to an embodiment of the present invention. 1: Silicon substrate, 2: Oxide film, 3: Insulating film, 4: First layer wiring, 5: Pad electrode, 6: N interlayer insulation film, 7: Second layer wiring, 8: Bump electrode, 9: Buff layer Figure 1
Claims (1)
配線を有し、該配線と絶縁基板上の導体との接続がバン
プ電極の固着によって行われるものの製造方法において
、バンプ電極への配線を第一層目の配線と同時に形成し
、ついで該配線のバンプ電極部を露出させて層間絶縁膜
、第二層目以降の配線を交互に積層したのち、前記バン
プ電極部の配線上にバンプ電極を形成することを特徴と
する半導体装置の製造方法。 2)特許請求の範囲第1項記載の方法において、最後に
半導体基板上にバンプ電極部を露出させてパッシベーシ
ョン膜を被着することを特徴とする半導体装置の製造方
法。[Claims] 1) A manufacturing method for a device having multiple layers of wiring laminated on a semiconductor substrate with an insulating film interposed therebetween, and in which the wiring and a conductor on the insulating substrate are connected by fixing bump electrodes. In this step, the wiring to the bump electrode is formed at the same time as the wiring in the first layer, and then the bump electrode part of the wiring is exposed and the interlayer insulating film and the wiring in the second and subsequent layers are alternately laminated. A method of manufacturing a semiconductor device, comprising forming a bump electrode on wiring of an electrode section. 2) A method for manufacturing a semiconductor device according to claim 1, wherein the bump electrode portion is finally exposed on the semiconductor substrate and a passivation film is deposited on the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7781486A JPS62234350A (en) | 1986-04-04 | 1986-04-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7781486A JPS62234350A (en) | 1986-04-04 | 1986-04-04 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62234350A true JPS62234350A (en) | 1987-10-14 |
Family
ID=13644492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7781486A Pending JPS62234350A (en) | 1986-04-04 | 1986-04-04 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62234350A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5379460A (en) * | 1976-12-24 | 1978-07-13 | Toshiba Corp | Manufacture of semiconductor device |
JPS5739556A (en) * | 1980-08-22 | 1982-03-04 | Citizen Watch Co Ltd | Ic electrode structure |
JPS5996761A (en) * | 1982-11-25 | 1984-06-04 | Mitsubishi Electric Corp | Multi-stage semiconductor device |
-
1986
- 1986-04-04 JP JP7781486A patent/JPS62234350A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5379460A (en) * | 1976-12-24 | 1978-07-13 | Toshiba Corp | Manufacture of semiconductor device |
JPS5739556A (en) * | 1980-08-22 | 1982-03-04 | Citizen Watch Co Ltd | Ic electrode structure |
JPS5996761A (en) * | 1982-11-25 | 1984-06-04 | Mitsubishi Electric Corp | Multi-stage semiconductor device |
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