JPS5379460A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5379460A
JPS5379460A JP15503676A JP15503676A JPS5379460A JP S5379460 A JPS5379460 A JP S5379460A JP 15503676 A JP15503676 A JP 15503676A JP 15503676 A JP15503676 A JP 15503676A JP S5379460 A JPS5379460 A JP S5379460A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
protrusion electrode
wiring
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15503676A
Other languages
Japanese (ja)
Inventor
Yoshiaki Komatsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15503676A priority Critical patent/JPS5379460A/en
Publication of JPS5379460A publication Critical patent/JPS5379460A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

PURPOSE: To avoid erosion of the Al wiring and to obtain a highly dependable protrusion electrode, by providing a protrusion electrode directly on the surface of a semiconductor substrate which contains an Al wiring layer coated with the PSG film.
COPYRIGHT: (C)1978,JPO&Japio
JP15503676A 1976-12-24 1976-12-24 Manufacture of semiconductor device Pending JPS5379460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15503676A JPS5379460A (en) 1976-12-24 1976-12-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15503676A JPS5379460A (en) 1976-12-24 1976-12-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5379460A true JPS5379460A (en) 1978-07-13

Family

ID=15597262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15503676A Pending JPS5379460A (en) 1976-12-24 1976-12-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5379460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62234350A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62234350A (en) * 1986-04-04 1987-10-14 Fuji Electric Co Ltd Manufacture of semiconductor device

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