JPS52150966A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS52150966A
JPS52150966A JP6768176A JP6768176A JPS52150966A JP S52150966 A JPS52150966 A JP S52150966A JP 6768176 A JP6768176 A JP 6768176A JP 6768176 A JP6768176 A JP 6768176A JP S52150966 A JPS52150966 A JP S52150966A
Authority
JP
Japan
Prior art keywords
semiconductor device
wiring layer
protecting film
cracking
occurrence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6768176A
Other languages
Japanese (ja)
Inventor
Tatsu Ito
Toru Kawanobe
Keiji Miyamoto
Hiroshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6768176A priority Critical patent/JPS52150966A/en
Publication of JPS52150966A publication Critical patent/JPS52150966A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To prevent the occurrence of cracking in a protecting film by providing corrosion resistant electrodes on the protecting film of the portion where there is no wiring layer, protruding part thereof to a certain portion of the wiring layer and connecting both.
COPYRIGHT: (C)1977,JPO&Japio
JP6768176A 1976-06-11 1976-06-11 Semiconductor device Pending JPS52150966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6768176A JPS52150966A (en) 1976-06-11 1976-06-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6768176A JPS52150966A (en) 1976-06-11 1976-06-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS52150966A true JPS52150966A (en) 1977-12-15

Family

ID=13351971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6768176A Pending JPS52150966A (en) 1976-06-11 1976-06-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS52150966A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232940A (en) * 1986-04-02 1987-10-13 Nec Corp Semiconductor device
JPH05206441A (en) * 1991-11-20 1993-08-13 Nec Corp Semiconductor integrated circuit device
JP2009524922A (en) * 2006-01-24 2009-07-02 エヌエックスピー ビー ヴィ Stress buffer package for semiconductor components

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232940A (en) * 1986-04-02 1987-10-13 Nec Corp Semiconductor device
JPH05206441A (en) * 1991-11-20 1993-08-13 Nec Corp Semiconductor integrated circuit device
JP2009524922A (en) * 2006-01-24 2009-07-02 エヌエックスピー ビー ヴィ Stress buffer package for semiconductor components
US8338967B2 (en) 2006-01-24 2012-12-25 Nxp B.V. Stress buffering package for a semiconductor component

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