JP2004018964A5 - - Google Patents
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- JP2004018964A5 JP2004018964A5 JP2002176692A JP2002176692A JP2004018964A5 JP 2004018964 A5 JP2004018964 A5 JP 2004018964A5 JP 2002176692 A JP2002176692 A JP 2002176692A JP 2002176692 A JP2002176692 A JP 2002176692A JP 2004018964 A5 JP2004018964 A5 JP 2004018964A5
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Claims (14)
(b)前記配線の一部が露出するように前記チップ領域上に第1絶縁膜を形成する工程と、(B) forming a first insulating film on the chip region so that a part of the wiring is exposed;
(c)前記チップ領域、前記スクライブ領域、及び前記禁止領域上に第1導電性膜を形成する工程と、(C) forming a first conductive film on the chip region, the scribe region, and the forbidden region;
(d)前記チップ領域における前記第1導電性膜の一部と前記禁止領域における前記第1導電性膜の一部が夫々露出するように前記第1導電性膜上にレジスト膜を形成する工程と、(D) forming a resist film on the first conductive film so that a part of the first conductive film in the chip region and a part of the first conductive film in the prohibited region are exposed; When,
(e)前記(d)工程により、前記レジスト膜から露出した前記第1導電性膜上に第2導電性膜を形成する工程と、(E) forming a second conductive film on the first conductive film exposed from the resist film by the step (d);
(f)前記レジスト膜、及び前記レジスト膜と平面的に重なる前記第1導電性膜を除去する工程と、(F) removing the resist film and the first conductive film overlapping the resist film in a plane;
(g)前記チップ領域における前記第2導電性膜の一部と前記禁止領域における前記第2導電性膜上に夫々第2絶縁膜を形成する工程と、(G) forming a second insulating film on a part of the second conductive film in the chip region and on the second conductive film in the prohibited region;
(h)前記チップ領域における前記第2絶縁膜から露出した前記第2導電性膜上にバンプ電極を形成する工程と、(H) forming a bump electrode on the second conductive film exposed from the second insulating film in the chip region;
を有することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
前記第1絶縁膜は、窒化シリコン膜および酸化シリコン膜を積層した後にポリイミド樹脂膜を堆積して形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the first insulating film is formed by depositing a polyimide resin film after laminating a silicon nitride film and a silicon oxide film.
前記第1導電性膜は、前記半導体基板の表面の全面に形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the first conductive film is formed on the entire surface of the semiconductor substrate.
前記第2導電性膜は、銅膜上にニッケル膜を堆積して形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the second conductive film is formed by depositing a nickel film on a copper film.
前記第2導電性膜は、電界メッキにより形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the second conductive film is formed by electroplating.
前記複数の配線は第1の間隔で形成し、The plurality of wirings are formed at a first interval,
前記(h)工程では、前記第1の間隔よりも広い第2の間隔で前記バンプ電極を形成することを特徴とする半導体装置の製造方法。In the step (h), the bump electrodes are formed at a second interval wider than the first interval.
前記バンプ電極はAu膜を介して前記第2導電性膜上に形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the bump electrode is formed on the second conductive film through an Au film.
前記(h)工程の前に、Before the step (h),
(i)前記第2絶縁膜上にテープを接着する工程と、(I) adhering a tape on the second insulating film;
(j)前記(i)工程の後、前記半導体基板における前記テープを接着した側とは反対側を研磨する工程と、(J) After the step (i), polishing the opposite side of the semiconductor substrate to the side to which the tape is bonded;
を有することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
前記テープは、前記チップ領域における前記配線から前記第2絶縁膜までの総厚よりも厚い接着部を有していることを特徴とする半導体装置の製造方法。The method for manufacturing a semiconductor device, wherein the tape has an adhesive portion thicker than a total thickness from the wiring to the second insulating film in the chip region.
前記テープは接着部を有し、The tape has an adhesive portion;
前記接着部を前記スクライブ領域における前記テープと前記半導体基板の間に充填させることを特徴とする半導体装置の製造方法。A manufacturing method of a semiconductor device, wherein the bonding portion is filled between the tape and the semiconductor substrate in the scribe region.
前記第2絶縁膜は、前記半導体基板の表面の端部に沿って形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the second insulating film is formed along an edge of the surface of the semiconductor substrate.
前記(d)工程では、前記チップ領域における前記レジスト膜と前記禁止領域における前記レジスト膜を同時に転写することを特徴とする半導体装置の製造方法。In the step (d), the resist film in the chip region and the resist film in the prohibited region are simultaneously transferred.
(b)前記半導体基板の表面に第1導電性膜を形成する工程と、(B) forming a first conductive film on the surface of the semiconductor substrate;
(c)前記チップ領域及び前記外周部の前記第1導電性膜上に開口部を有する絶縁膜を形成する工程と、(C) forming an insulating film having an opening on the chip region and the first conductive film on the outer periphery;
(d)前記第1導電性膜上であり、かつ前記絶縁膜の開口部内に第2導電性膜を形成する工程と、(D) forming a second conductive film on the first conductive film and in the opening of the insulating film;
を有することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
前記第2導電性膜は、電界メッキにより形成することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the second conductive film is formed by electroplating.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002176692A JP2004018964A (en) | 2002-06-18 | 2002-06-18 | Semiconductor wafer and production method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002176692A JP2004018964A (en) | 2002-06-18 | 2002-06-18 | Semiconductor wafer and production method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JP2004018964A JP2004018964A (en) | 2004-01-22 |
JP2004018964A5 true JP2004018964A5 (en) | 2005-10-13 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2002176692A Pending JP2004018964A (en) | 2002-06-18 | 2002-06-18 | Semiconductor wafer and production method of semiconductor device |
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JP (1) | JP2004018964A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006339189A (en) * | 2005-05-31 | 2006-12-14 | Oki Electric Ind Co Ltd | Semiconductor wafer and semiconductor device using the same |
WO2012036017A1 (en) * | 2010-09-13 | 2012-03-22 | 株式会社村田製作所 | Dielectric thin film element, anti-fuse element, and method for producing dielectric thin film element |
JP5869902B2 (en) | 2012-02-14 | 2016-02-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and wafer |
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2002
- 2002-06-18 JP JP2002176692A patent/JP2004018964A/en active Pending
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