JP2004342862A - Semiconductor device and its manufacturing method, false wafer and its manufacturing method, and multi-chip module - Google Patents

Semiconductor device and its manufacturing method, false wafer and its manufacturing method, and multi-chip module Download PDF

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JP2004342862A
JP2004342862A JP2003138136A JP2003138136A JP2004342862A JP 2004342862 A JP2004342862 A JP 2004342862A JP 2003138136 A JP2003138136 A JP 2003138136A JP 2003138136 A JP2003138136 A JP 2003138136A JP 2004342862 A JP2004342862 A JP 2004342862A
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chip
semiconductor device
manufacturing
wiring
external terminal
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Masaki Hatano
正喜 波多野
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Sony Corp
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has an external terminal easily connected with a plurality of chip components and an external apparatus and can be formed at a low cost and its manufacturing method, a false wafer and its manufacturing method, and a multi-chip module. <P>SOLUTION: A W-shaped recess is formed on the external side face 31 of a chip component 3. An interconnection 20 extracted from the electrode 5 of the chip component 3 is led to the rear face 36 side along the inclined surface of the W-shaped recess. Then, the rear face 36 is ground to expose the interconnection 20 at the bottom of the recess. After the interconnection 22 of the rear face 36 is formed in connection with the exposed part of the interconnection 20, an opening is formed in a protection film 21 formed on the front surface 35 to form the external terminal 16 of the front surface 35, and an opening is formed in a protection film 25 formed on the rear face 36 to form an external terminal 23 of the rear face 36. A series of these processes are conducted as one job on the false wafer 29. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びにマルチチップモジュールに関するものである。
【０００２】
【従来の技術】
従来、携帯用電子機器の小型・軽量化、高速化の要求に対し、一つの方法として、ＩＣの高集積化、微細化を図って複数の機能をワンチップ（システムＬＳＩ）化しているが、歩留低下等による製造コストの増大等の問題でシステムＬＳＩを低コストで実現することが難しくなっている。一方で、複数の半導体チップをワンパッケージ化したＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）が提案されている。
【０００３】
ＭＣＭは多層配線基板に半導体チップを配置しているが、搭載する半導体チップの接続端子ピッチが狭くなると配線基板の製造が難しくなり、基板のコストアップとなる。また、バンプやワイヤボンディング、タブ等で接続するため、接続端子数に制限がある上、その平面視面積は搭載半導体チップの平面視面積の総和より大きくなってしまう。更に、信号伝達が遅くなり、性能低下等の問題がある。
【０００４】
ＭＣＭの製造技術については、複数のベアチップをその表面が平坦になるように支持基板上に貼り付けて配線することにより、生産性よく配線することが開示されている（後述の特許文献１参照）。また、機能別に作製した複数個の半導体チップを互いに隣接して接着することにより、四辺形に形成した合成チップをウェーハ上に貼り付け、このチップのアクティブ面を平坦化して露出させたチップの外部接続端子から配線することにより、小面積化した合成チップを小さいパッケージに形成することが開示されている（後述の特許文献２参照）。更に、支持基板に良品チップを貼り付けた後に、保護物質を被着して剥離することで疑似ウェーハを作製し、その上に半導体プロセスにより配線することが開示されている（後述の特許文献３参照）。
【０００５】
このうち、本出願人が提起した特許文献３（以下、先願発明と称する。）は、自社製又は他社製の区別なく、ウェーハより半導体チップを切り出した後、オープン／ショート或いはＤＣ（直流）電圧測定により良品と確認された半導体ベアチップのみを疑似ウェーハ上に再配置し、これに所定の製造工程を施してチップ状電子部品を作製するものであるが、その製造プロセスを図２５に示す。
【０００６】
即ち、図２５（ａ）は、仮の支持基板として用いた石英基板１を示す。但し、基板への加熱プロセスは４００℃以下であるため、安価なガラス基板も使用でき、また、この石英基板１は繰り返し使用可能である。
【０００７】
次に、図２５（ｂ）のように、石英基板１上に、紫外線を照射されると粘着力が低下する例えばアクリル系の粘着シート２を貼り付ける。
【０００８】
次に、図２５（ｃ）のように、良品と確認された複数の良品ベアチップ３をチップ表面（デバイス面）２８を下向きに配列して粘着シート２に貼り付ける。なお、良品ベアチップ３は、通常のウェーハ工程でダイシングして、使用したダイシングシート（図示せず）の延伸状態から取り出してもよく、チップトレイから移載してもよい。
【０００９】
次に、図２５（ｄ）のように、良品ベアチップ３上から有機系絶縁性樹脂、例えばエポキシ系等の樹脂４をスピンコート法か印刷法により、均一に塗布する。
【００１０】
次に、図２５（ｅ）のように、石英基板１の裏側５１より紫外線を照射して、粘着シート２の粘着力を弱め、樹脂４で側面及び裏面が連続して固められた複数の良品ベアチップ（以下、半導体チップ、チップ又はチップ部品と称することがある。）３を配した疑似ウェーハ２９を石英基板１から接着面５２で剥離する。
【００１１】
次に図２５（ｆ）のように、良品ベアチップ表面２８（デバイス面）が上になるように疑似ウェーハ２９をひっくり返す。下図は疑似ウェーハ２９の一部を拡大図示したものであり、図示の如く、Ｓｉ基板上にＳｉＯ２膜７を介してＡ１電極パッド５及びパッシベーション膜８が形成されている。
【００１２】
その後、無電解めっき法により、開口されたＡｌ電極パッド５の上面のみに、選択的にＮｉめっき層を形成し、この上に配したはんだペーストを加熱溶融してはんだバンプをウェーハ一括で形成後に、再度プローブ検査により電気的特性を測定することにより、更により確実に良品チップのみを選別する。
【００１３】
上記のように形成した半導体チップ３は、ワンチップに個片化後、例えば図２８に示すようにはんだバンプ３３を介して回路基板３９の電極４０にマウントしたり、例えば図２９に示すようにチップ３を並列に配し、この複数のチップ３間の再配置配線１２（半導体チップ内の配線をチップ上の任意の位置に引き出して行う配線）を行うことにより、回路構成をしてＭＣＭを構成することができる。また、図示しないが半導体チップ３の電極パッド５から接続孔を介して絶縁層上に配線を導出し、更にこのような構造を積み上げて多層構造化することにより、回路基板へのマウント時に任意の位置に再配置配線を行って多ピン化に対応することもでき、これらを疑似ウェーハ２９上で一括して行うことができる。
【００１４】
このように、先願発明によれば、半導体チップの電極面以外（即ち、チップの側面及び裏面）が連続した保護物質によって保護されるので、チップ化後のハンドリングにおいてチップが保護され、ハンドリングが容易となる。
【００１５】
また、半導体ウェーハから切出した良品のみを選択して再配置しているので、あたかも全品が良品チップからなる疑似ウェーハが得られ、配置した良品チップに対してウェーハ一括でのバンプ処理等が可能となり、低コストのバンプチップを形成できると共に、半導体チップを疑似ウェーハから切り出す際に、チップ間の保護物質の部分を切断することになるので、半導体チップ本体への悪影響（歪みやばり、亀裂等のダメージ）を抑えて容易に切断することができる。
【００１６】
しかも、保護物質によってチップの側面及び裏面が覆われているため、Ｎｉ無電解めっき処理も可能である。そして、自社製ウェーハのみならず、他社から購入したベアチップでも容易にはんだバンプ処理等が可能になる。
【００１７】
また、ＭＣＭに搭載される異種ＬＳＩチップを全て同一半導体メーカーから供給されるケースは少なく、ＳＲＡＭ、フラッシュメモリーやマイコン、更にＣＰＵ（中央演算処理ユニット）を、それぞれ得意とする半導体メーカーから別々にチップで供給してもらい、これらをＭＣＭ化することもできる等の優れた特徴を有している。
【００１８】
上記した先願発明の半導体チップ３の再配置配線を疑似ウェーハ２９上で行う場合、例えば図２６〜図２７のような方法で行うことができる。
【００１９】
図２６（ａ）は、上記した図２５（ｆ）の下図（一部の拡大図）を示す。即ち、疑似ウェーハ２９を構成する保護物質としての樹脂４により、側面及び裏面を覆われて一体化された半導体チップ３上に、Ａｌからなる電極パッド５（以下、電極と称する。）が配され、この電極５が露出するようにパッシベーション膜８が形成されている。
【００２０】
この後に形成する配線はセミアディティブ法により形成されるが、簡略して図示する。まず、図２６（ｂ）に示すように、パッシベーション膜８を被覆するように層間絶縁膜９を形成後に、図２６（ｃ）に示すように、上面の全面にめっき用の電極となるシードメタルとして、Ａｌと密着性の良いＴｉのスパッタ膜１０を形成する。
【００２１】
次に、図２６（ｄ）に示すように、スパッタ膜１０上にフォトリソグラフィ技術によってフォトレジスト膜１１を形成後に、図２７（ｅ）に示すように、Ｃｕを用いて配線となる電解めっき膜１２Ａを形成する。これにより、Ａｌと密着性の良いＴｉをシードメタルとすることにより、Ｔｉのスパッタ膜１０上にＣｕを容易にめっきすることができる。
【００２２】
次に、図２７（ｆ）に示すように、フォトレジスト膜１１を除去し、このフォトレジスト膜１１下のスパッタ膜１０をウェットエッチング等で除去することにより、再配置した配線１２が形成される。
【００２３】
次に、図２７（ｇ）に示すように、上部の全面を保護膜１３で被覆後に、図２７（ｈ）に示すように、保護膜１３に配線１２との接続孔６を形成し、外部端子１５を露出させる。
【００２４】
上記の方法により、同一の疑似ウェーハ２９上に複数個又は複数種のチップ部品を並列に配し、ＭＣＭの回路を形成するための再配置配線をウェーハレベルで一度に行うことができる。しかも、先願発明は、半導体ウェーハから切り出した良品チップのみを選んで再配置し、その側面及び裏面を樹脂で覆って一体化し、更に特性検査を行って、１００％良品チップが配された疑似ウェーハ上で、これらのチップに対して一括してチップ間の再配置配線を行うことができ、ＭＣＭを疑似ウェーハ段階で形成することができる等の優れた特長を有している。
【００２５】
【特許文献１】
特開平７−２０２１１５号（第５頁左欄、図１及び図３）
【特許文献２】
特開平１１−３３０３５０号（第６頁右欄、図５及び図６）
【特許文献３】
特開２００１−３０８１１６号（第５頁左欄、第７頁右欄及び図２）
【００２６】
【発明が解決しようとする課題】
しかしながら、従来は先願発明においても、半導体チップ３の外部端子が疑似ウェーハ２９の表面側にしか形成されていないため、裏面側で外部機器等との接続ができないという問題や、積層構造のＭＣＭを形成できないという問題があった。
【００２７】
そこで本発明の目的は、複数のチップ部品間及び外部機器との接続が容易な外部端子を有し、かつこれを低コストで形成可能な半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びにマルチチップモジュールを提供することにある。
【００２８】
【課題を解決するための手段】
即ち、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われているチップ部品を有する半導体装置において、前記チップ部品の前記電極の外部端子が、前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成されていることを特徴とする、半導体装置（以下、本発明の半導体装置と称する。）に係るものである。
【００２９】
また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質によって一体化されてなる疑似ウェーハを作製する工程と、
前記疑似ウェーハにおける前記チップ部品の前記電極の外部端子を前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成する工程と、
前記複数個のチップ部品間で少なくとも前記保護物質を切断する工程と
を有することを特徴とする、半導体装置の製造方法（以下、本発明の半導体装置の製造方法と称する。）に係るものである。
【００３０】
本発明の半導体装置及びその製造方法によれば、一方の面側に電極を設けられたチップ部品が、電極面以外の少なくとも側面及び他方の面が保護物質で覆われているので、チップ化後のハンドリング時にチップ部品が保護され、ハンドリングが容易となると共に、保護物質の位置で切断してチップ部品に個片化することができるために、切断時にチップ部品がダメージ（亀裂や歪み等）を受けることがない。
【００３１】
この構造において、チップ部品の外部端子が、一方の面とこれとは反対側の他方の面とのうち、少なくとも他方の面に形成されるので、このチップ部品の実装基板への実装時には、少なくとも他方の面の外部端子を介して接続が可能であり、また、他方の面の任意の位置に外部端子を設けることができ、設計の自由度が大きいと共に、この外部端子を介して実装可能であるために実装時の熱ストレスによるチップ部品の一方の面側（電極面側）への影響を緩和することができる。
【００３２】
この場合、側面及び他方の面が保護物質で覆われているため、この保護物質によってチップ部品に対し絶縁分離を行いながら、保護物質の側面又は内部を通して一方の面の電極を他方の面側の外部端子に導びくための配線を形成することができ、かつ、保護物質によって前記配線を保護することができる。
【００３３】
また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質によって一体化されてなる疑似ウェーハであって、前記チップ部品の前記電極の外部端子が前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成されている、疑似ウェーハ（以下、本発明の疑似ウェーハと称する。）に係るものである。
【００３４】
また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質によって一体化されてなる疑似ウェーハの製造方法において、前記疑似ウェーハにおける前記チップ部品の前記電極の外部端子を前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成する工程を有することを特徴とする、疑似ウェーハの製造方法（以下、本発明の疑似ウェーハの製造方法と称する。）に係るものである。
【００３５】
本発明の疑似ウェーハ及びその製造方法によれば、一方の面側に電極を設けられたチップ部品の複数個が、その電極面以外の少なくとも側面及び他方の面が保護物質で覆われ、一体化されているので、良品チップのみを選択して再配置し、あたかも全品が良品チップからなる疑似ウェーハ上で、チップ部品に対して一括での低コストなバンプ処理が可能となると共に、保護物質の位置で切断してチップ部品に個片化することができるので、チップ部品がダメージ（歪み、亀裂等）を受けることがなく、しかも、保護物質によってチップ部品の側面及び他方の面が覆われているため、Ｎｉ無電解めっき処理も可能であり、自社製、他社製の区別なくはんだバンプ処理等が可能になる。
【００３６】
そして、このチップ部品の外部端子が、一方の面とこれとは反対側の他方の面とのうち少なくとも他方の面に形成されるので、この疑似ウェーハを切断して得られたチップ部品の実装基板への実装時には、少なくとも他方の面の外部端子を介して接続が可能であり、上記した本発明の半導体装置と同様の効果が奏せられる、再現性の良いチップ部品を有する疑似ウェーハを提供できる。
【００３７】
また、本発明は、上記した本発明の半導体装置によって構成され、この半導体装置が有する複数の前記チップ部品間が前記外部端子を介して互いに接続されている、マルチチップモジュール（以下、本発明のマルチチップモジュールと称する。）に係るものである。
【００３８】
本発明のマルチチップモジュールによれば、このマルチチップモジュールを構成するチップ部品が、上記した本発明の半導体装置によって構成されるので、複数のチップ部品の積層構造又は並列配置のマルチチップモジュールであっても、この複数のチップ部品間の接続をこれらのチップ部品の外部端子を介して行うことができる。
【００３９】
【発明の実施の形態】
上記した本発明の半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びにマルチチップモジュールにおいては、前記側面の保護物質の外側面に、前記一方の面（電極面又は表面）の外部端子と、他方の面（裏面）の外部端子とを接続するための導電体が形成され、前記導電体が、前記保護物質に傾斜外側面又は垂直貫通孔を設け、この傾斜外側面または垂直貫通孔に形成されていることが、めっき膜の如き導電体を形成し易くし、他方の面に外部端子を形成し易い点で望ましい。
【００４０】
この場合、前記複数個のチップ部品間において、前記側面の保護物質に凹部（例えば傾斜面を有する溝、又はスルーホール）を形成し、この面上に前記一方の面の外部端子と他方の面の外部端子とを接続するための導電体を形成した後、前記他方の面側から少なくとも前記保護物質を部分的に研削により除去し、この除去面に前記導電体を露出させ、この露出した導電体に接続した前記他方の面の前記外部端子を形成することが望ましい。
【００４１】
更に、前記凹部を前記チップ部品の厚みよりも深く形成することにより、前記保護物質の部分的除去によって、傾斜面又は垂直面を呈した前記凹部の面上に前記導電体を残し、この除去面に導電体を露出させることが望ましい。
【００４２】
また、前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、前記凹部においてこの絶縁性保護膜の材料が、前記側面の保護物質の材料に対し、物性が大きく異なる場合や凹部の平坦化が得られない場合には、前記凹部に対しては、前記絶縁性保護膜とは異なる絶縁物質（側面の保護物質と同じ材料）を前記傾斜外側面の前記導電体上に設け、この上に絶縁性保護膜を形成し、二重構造にしてもよい。
【００４３】
また、前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、導電性物質（例えばペースト）を前記外側面の前記導電体上に接して設けてもよい。これにより、前記他方の面側の保護物質の過剰な除去等による前記導電体の接続不良を補うことができる。
【００４４】
そして、特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製し、更に、前記疑似ウェーハの状態において再度前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択することが、歩留りを高める点で望ましい。
【００４５】
これにより、上記した半導体装置を製造するための疑似ウェーハを得て、これを個片化した前記複数のチップ部品を接続するための前記外部端子が、一方のチップ部品の前記一方の面側（電極面側）と、他方のチップ部品の前記他方の面側（裏面側）にそれぞれ形成され、この外部端子を接続した積層構造のマルチチップモジュールを形成することもでき、また、前記複数のチップ部品を接続するための前記外部端子が、前記一方の面側（電極面側）又は前記他方の面側（裏面側）に形成され、この外部端子を接続した平置き（並列配置）構造のマルチチップモジュールを形成することもできる。
【００４６】
次に、上記した本発明の好ましい実施の形態を図面参照下で具体的に説明する。
【００４７】
実施形態１
図１は、本実施の形態の半導体装置５０を示す。図示の如く、チップ部品３の電極５から導出された配線２０が、チップ３の外側面３１の樹脂４内において裏面３６側へ斜めに配線され、その先端が反対方向へ対称形に屈折し、配線２０の下端が裏面３６に設けた配線２２に接続されている。そして、引き出された配線２０の一部分が、電極５近傍の表面３５側で露出されて表面３５側の外部端子１６が形成され、裏面３６側の外部端子２３は、配線２２の一部分を露出して形成されている。そして上下の外部端子１６、２３は対向配置され、この外部端子１６、２３は、それぞれ保護膜２１、２５に配線２０、２２との接続孔２７、２４の開口によって形成されている。
【００４８】
図２は、上記した半導体装置５０を積層した図を示す。上記したように、上下の外部端子１６、２３が対向配置されているため、下方の半導体装置５０の表面３５側の外部端子１６と上方の半導体装置５０の裏面３６側の外部端子２３とを、例えばはんだバンプ３３等を介して接続できることにより、積層構造のＭＣＭ等を形成することが可能となり、ＭＣＭの小型化も可能になる。
【００４９】
図３〜図５は、本実施の形態の半導体装置５０を作成するために、疑似ウェーハ工程から、これを個片化して半導体装置とするまでの製造プロセスを示すものであるが、図３（ａ）〜（ｅ）は先願発明における図２５（ｂ）〜（ｆ）と同様であるので、この間のプロセスの説明は省略する。
【００５０】
しかし、本実施の形態は先願発明とは異なり、チップ部品３の裏面３６側にも外部端子を形成するために、チップ３の外側面３１の樹脂４の部分において、裏面３６側へ導びくための配線２０が斜めに導出され、これに接続された配線２２が設けられ、配線２０の一部を露出させて表面３５に外部端子１６と、配線２２の一部を露出させて裏面３６に外部端子２３とを設け、半導体装置５０の両面に外部端子を形成する。
【００５１】
従って、図３（ｅ）のように、石英基板から剥離した疑似ウェーハ２９に対し、図３（ｆ）に示すように、配線を斜めに導出するために、チップ間の樹脂４に例えばＷ字状の溝１８をダイサー等で切り出し形成する。そして、この溝１８は疑似ウェーハ２９に配置しているチップ３の厚みＴより深く（Ｄ＞Ｔ）形成し、かつ、疑似ウェーハ２９の反りや強度が、その後の配線形成プロセスに耐え得る厚みが残せるように疑似ウェーハを形成することが必要である。この溝１８はチップ３を配置前に樹脂４の成形時に形成してもよい。
【００５２】
また、Ｗ字状の溝１８の角度は鋭角であると、その後の配線形成が難しくなるので、配線形成プロセスを考慮した角度で形成するのがよい。できれば４５度より鈍角で形成するのが好ましい。
【００５３】
図４（ｇ）は図３（ｆ）におけるＡ部の拡大図であるが、既述した図２６（ａ）と同様に、チップ３の側面及び裏面が樹脂４で覆われて一体化され、チップ３の電極５が露出するようにパッシベーション膜８が形成されている。
【００５４】
次に、図４（ｈ）に示すように、層間膜９をチップ３の電極５を開口するようにフォトリソグラフィ技術により所定のパターンで形成後に、層間膜９上の全面にスパッタ膜１０を形成する。パッシベーション膜８の表面は荒れているので、これを平坦化するために層間膜９は不可欠であり、層間膜９の形成により平坦化され、これにより後に形成する配線を均一に形成できる。
【００５５】
層間膜９の材料には感光性絶縁樹脂等を使用し、液状のものをスピンコートして塗布するか、又はドライフィルムをラミネーターで貼り付ける等にて行う。この時Ｗ字状の溝１８が鋭角だと、溝部の層間膜９の厚みが厚くなり、溝１８が層間膜９によって埋められて浅くなる可能性があるので、その場合は、スプレー塗布等を利用して全体を薄めに塗布し、Ｗ字状の溝部の層間膜９の厚みが厚くならないように、均一に形成することが必要である。
【００５６】
次に、チップ３の電極５の外部端子を形成するための引き出し配線を形成するが、この配線は例えば次のごときプロセスで行うセミアディティブ法（スパッタ膜形成→めっきレジスト形成→めっき→めっきレジスト剥離→スパッタ膜エッチング）等で形成する。
【００５７】
まず図４（ｉ）に示すように、層間膜９上にめっきの電極となるシードメタルとして、Ａｌ電極５との密着性の良いＴｉ等により形成したスパッタ膜１０上の全面に、例えばポジ型のフォトレジスト膜１１Ａを形成する。
【００５８】
次に、図４（ｊ）に示すように、フォトレジスト膜１１Ａ上にパターン開口部４３ａを有する露光マスク４２を配置し、フォトレジスト膜１１Ａを露光する。この露光光４５によってマスク４２のパターン開口部４３ａ下のレジスト膜１１Ａが硬化され、レジストマスク１１の一部が形成される。
【００５９】
次に、図５（ｋ）に示すように、露光マスク４２の別のパターン開口部４３ｂを所定位置に配し、フォトレジスト膜１１Ａを露光する。この露光によって、後に個片化時の切断位置となるＷ字状の溝１８の中央部領域が硬化され、レジストマスク１１の他の部分が形成される。この露光マスク４２はこのように同一のマスクを使い分けてもよく、別々のマスクを用いてもよい。
【００６０】
上記したフォトレジスト膜１１Ａの露光に際しては、パターン開口部４３ａと４３ｂとを同時に露光できるマスク４２を使用し、同時に露光してもよいが、溝１８の部分とチップ３の上部とではレジスト膜４１Ａの厚さに大きな差があり、焦点深度が大きく違ってしまうため、溝１８の部分とチップ３上のフォトレジスト膜とを同時には解像できない可能性がある。従って、この場合は、上記したように溝１８の部分とチップ３上とを別々に露光するのがよい。
【００６１】
次に、図５（ｌ）に示すように、露光後のフォトレジスト膜１１Ａを現像することにより、硬化部にレジストマスク１１が形成され、これをマスクとしてＣｕの電解めっきを行うことにより、裏面３６側へ配線を導びく経路が傾斜面であるためめっきが付き易く、図５（ｍ）に示すように、配線を形成するためのめっき膜１２Ａが段切れすることもなく、良好に形成される。
【００６２】
次に、図６（ｎ）に示すように、レジストマスク１１を剥離除去後に、レジストマスク１１下のスパッタ膜１０をウェットエッチング等で除去することにより、再配置した配線２０が形成される。ここでスパッタ膜は配線２０の一部とみなし、これ以降の図においては図示省略する。
【００６３】
次に、図６（ｏ）に示すように、配線２０を含む上部の全面に保護膜２１を形成する。
【００６４】
ここで、保護膜２１として使用する材料が、樹脂４の材料に対して物性的（線膨張係数、ヤング率、硬化収縮等）に大きく違う場合や、溝１８部分の平坦化が十分に得られない場合は、図１２に示すように、保護膜２１の形成前に、溝１８部分のみに保護膜２１ａを形成し、その後に形成する保護膜２１との２層構造としてもよい。保護膜２１ａとしては、樹脂４と同じ材料や感光性絶縁樹脂等を使用し、ディスペンス法又は印刷法等により溝１８部分のみに形成する。
【００６５】
次に、図６（ｐ）に示すように、樹脂４を裏面３６から研削し、溝１８の底に形成されている配線２０を露出させる。研削はＳｉウェーハの裏面研削用のグラインダー等で行う。
【００６６】
本実施の形態は、配線２０が溝１８の底部分で露出されるように研削するのが特徴であり、露出した配線２０の露出部２０ａが、その後の裏面３６側の配線２２に接続される。
【００６７】
この場合、露出部２０ａの面積はできるだけ広い方がよい。従って、露出部２０ａを広くとるために、チップ３の裏面が少し削られる程度に研削してもよい。しかし、削り過ぎると溝底部の配線２０が断線するので、Ｄ＞Ｔ（即ち、チップ厚よりも溝が深い）が保たれる限り、予め溝１８を浅く形成しておいてもよい。
【００６８】
次に、図６（ｑ）に示すように、裏面３６側の外部端子となる配線２２を形成する。この配線形成は、例えば前記配線２０と同様にセミアディティブ法（ここでは図示省略する。）で形成する。
【００６９】
次に、図６（ｒ）に示すように、裏面３６側の配線２２に、外部端子２３となる部分を開口するように、表面３５の層間膜９と同様に所定のパターンで保護膜２５を形成する。この保護膜２５の材料としては、既述した感光性絶縁樹脂等を使用し、層間膜９と同様に行うことで形成できる。符号３７は個片化する際の切断線を示し、この位置で切断して個片化することにより、図１に示したように、両面に外部端子１６、２３を有する半導体装置５０が得られる。そして、チップ３の電極面以外が連続した樹脂４によって保護されるので、チップ化後のハンドリングにおいてチップが保護され、ハンドリングが容易であると共に、導出した配線２０が樹脂４によりチップ３に対して絶縁されながら保護される。
【００７０】
また、良品チップ３のみを選択して再配置しているので、あたかも全品が良品チップからなる疑似ウェーハ２９が得られ、自社製、他社製の区別なく配置し、ウェーハレベルで一括処理が可能であり、低コストで外部端子を形成できると共に、チップ３を疑似ウェーハ２９から切り出す際に、側面３１の樹脂４の部分を切断するので、チップ３本体へのダメージ（歪みやばり、亀裂等）を抑えて容易に切断することができる。
【００７１】
しかも、樹脂４によってチップ３の側面３１及び裏面３６が覆われているため、Ｎｉ無電解めっき処理も可能である。
【００７２】
上記した如く、疑似ウェーハ２９上における各チップ３毎の外部端子の形成プロセスを断面図にて説明したが、図７（ａ）はこれを部分的に平面図として示し、図７（ｂ）は同じくその底面図として示した概略図であり、隣接するチップ３との間に導出した配線２０及び裏面３６の配線２２を示したものであって、いずれも配線の形状を明示するために、表面３５側の配線２０及び裏面３６の配線２２を実線で示した。
【００７３】
即ち、外部端子を形成するために、チップ３の電極５から導出した配線２０は、チップ３の各辺（図７では一辺のみに簡略図示している。）に配置されている電極５から図７のように導出され、チップ間の樹脂４に設けられたＷ字状の溝１８の形状に沿って裏面３６側へ引き出された状態を示している。
【００７４】
上記したように、疑似ウェーハ２９の表面３５にＷ字状の溝１８を形成し、チップ３の電極５から導出してＷ字状の溝１８に形成した配線２０を、疑似ウェーハ２９の裏面３６を研削して露出させ、その露出部２０ａに接続した配線２２の一部を露出させて裏面３６側の外部端子２３を形成し、これを疑似ウェーハ２９上で一括して形成することにより、低コストで裏面への外部端子を形成できると共に、両面に外部端子が形成されていることにより、積層構造（スタック構造）のＭＣＭが可能となる。しかも、外部端子１６、２３がチップ３の側面寄りに位置するため、実装時の熱ストレスによりチップ３が歪む又は反る等の影響を受けることが少ない利点がある。
【００７５】
図８〜１０は、上記のように形成した半導体装置５０の代表的な実装例を示す図であり、上記のようにして疑似ウェーハ段階で外部端子を形成した後に、これを個片化した半導体装置５０をプリント基板３９に搭載した実装例である。
【００７６】
図８はその一例を示す。本実施の形態による半導体装置５０は、表面３５側に外部端子１６を有し、裏面３６側にも外部端子２３を有するので、プリント基板３９の電極端子４０に対して、ワイヤボンディングの如き配線を要せず、はんだバンプ３３等を介してフェイスアップにて接続することができる。この場合、半導体装置５０の外部端子１６と２３は対向配置しているが、裏面側の外部端子２３はプリント基板３９の電極端子４０の位置に合せて配置してもよい。即ち、裏面側は電極面側のように、チップ３のアクティブ領域を避ける等の位置的制約がないため、設計上の自由度が大きく、任意の位置に外部端子を形成できる。
【００７７】
図９は他の実装例を示すものであり、記述した図２と同様に積層構造とし、複数（図９では２層構造であるが２層以上でもよい。）の半導体装置５０をプリント基板３９に実装した状態である。このように積層構造においては、表面３５の外部端子１６と裏面３６の外部端子２３が対向配置されていることにより、はんだバンプ３３等を介して簡単に接続することができる。そして、この場合もプリント基板３９に接する半導体装置５０の裏面３６側の外部端子２３は、プリント基板３９の電極４０の位置に合せて配置することもできる。
【００７８】
図１０は、更に他の実装例を示すものであり、図示の如く、半導体装置５０を並列に配し、隣接する半導体装置５０との間の配線は、裏面３６側へ導出した配線２０に接続した配線２２を連結してもよい。この場合もプリント基板３９に接続する裏面３６の外部端子は、プリント基板３９の電極４０の位置に合せて設けることもでき、また、並列に配置する半導体装置の数はこれに限らず、２個以上を配置することができる。
【００７９】
本実施の形態によれば、チップ３の表面３５以外の少なくとも側面３１及び裏面３６が樹脂４で覆われているので、チップ化後のハンドリング時にチップ３が保護され、ハンドリングが容易となると共に、樹脂４の位置で切断してチップ３に個片化することができるために、切断時にチップ３がダメージ（亀裂や歪み等）を受けることがない。
【００８０】
この構造において、チップ３の外部端子が、表面３５と裏面３６とのうち少なくとも裏面３６に形成されるので、このチップ３の実装基板３９への実装時には、少なくとも裏面３６の外部端子２３を介して接続が可能であり、また、裏面３６の任意の位置に外部端子２３を設けることができ、設計の自由度が大きいと共に、この外部端子２３を介して実装可能であるために実装時の熱ストレスによるチップ３の電極面側への影響を緩和することができる。
【００８１】
この場合、側面３１及び裏面３６が樹脂４で覆われているため、この樹脂４によってチップ３に対し絶縁分離を行いながら、樹脂４の側面又は内部を通して表面３５の電極５を裏面３６側の外部端子２３に導びくための配線２０を形成することができ、かつ、樹脂４によって前記配線２０を保護することができる。
【００８２】
更に、表面３５と裏面３６との両面に外部端子１６、２３を設けることにより、複数のチップ３を積層して外部端子１６、２３を接続することも可能であると共に、疑似ウェーハ段階で隣接チップ間の接続も可能であるため、積層構造のみならず、平置き構造のＭＣＭの作製も容易である。このように表裏両面に外部端子１６、２３を有するチップ３を疑似ウェーハ製造時に一括して作製するので、先願発明の優れた特長を保持しながら、更に接続性に優れた半導体装置５０を低コストで作製することができる。また、外部端子を裏面にも設ける構造は、既述した特許文献３のみならず、特許文献１及び２にも適用可能である。
【００８３】
実施形態２
図１１は、本実施の形態による半導体装置作製のプロセスを示すものであり、Ｗ字状の溝１８の形成方法が、実施形態１のダイサーによる形成とは異なり、入れ子により形成する方法である。
【００８４】
図１１（ａ）は、既述した図２５による先願発明と同様のプロセスにより、石英基板１上に、紫外線照射によって粘着力が低下する粘着シート２が貼り付けられた状態、そして図１１（ｂ）は、複数の良品ベアチップ３の表面（電極面）を下向きにして粘着シート２に貼り付け状態を示す。
【００８５】
次に、図１１（ｃ）に示すように、各チップ間に断面がＷ字を伏せた形状の入れ子３０を配し、粘着シート２に貼り付ける。この場合、入れ子３０の高さＤとチップ３の厚さＴとの関係は、Ｄ＞Ｔであることが重要であると共に、入れ子３０の突状部は４５度より鈍角であることが望ましい。
【００８６】
次に、図１１（ｄ）に示すように、チップ３上から有機系絶縁性樹脂、例えばエポキシ系等の樹脂４をスピンコート法または印刷法により、均一に塗布する。
【００８７】
次に、図１１（ｅ）に示すように、石英基板１の裏側から紫外線Ｌを照射して、粘着シート２の粘着力を弱め、側面及び裏面が樹脂４で固められた複数のチップ３を配した疑似ウェーハ２９を石英基板１から剥離する。
【００８８】
上記のプロセスを経ることにより、図１１（ｆ）に示すような疑似ウェーハ２９（図１１（ｅ）における疑似ウェーハをひっくり返したもの。）を得ることができ、前記した実施形態１（図３（ｆ）参照）と同様な形状の疑似ウェーハ２９を形成することができる。
【００８９】
従って、これ以降は実施形態１と同様のプロセスを経ることにより、実施形態１と同様な形状と機能を有する半導体装置を得ることができる。
【００９０】
本実施の形態によれば、実施形態１と同様なＷ字状の溝を形成するものの、その形成方法のみが異なり、その他の製造プロセスは同様に行われ、全く同様の半導体装置が形成されるので、実施形態１と同様な機能を有し、同様な効果を発揮できる半導体装置を得ることができる。
【００９１】
実施形態３
図１３は、本実施の形態による半導体装置（図１に対応する）５０Ａを示す。この半導体装置５０Ａが実施形態１の半導体装置５０（図１参照）と異なる点は、チップ３の電極５から導出された配線２０が、チップ３の側面において裏面３６側へ傾斜しているだけで、その先端が裏面３６に設けた配線２２に接続していることであり、その他は実施形態１と同様な構成となっている。この製造プロセスを図１４により説明する。
【００９２】
図１４（ａ）は、既述した実施形態１における図３（ｆ）及び実施形態２における図１２（ｆ）に対応する図であるが、図示のように、溝１８の形状が実施形態１のＷ字状の溝とは異なり、梯形となっている。この場合も、溝１８の深さＤとチップ３の厚さＴとの関係は、Ｄ＞Ｔとなっている。この溝１８は例えば切削により形成してもよく、実施形態２のように入れ子を用いて形成してもよい。そして、溝の形状が梯形であるためＷ字状の場合よりも隣接するチップ間の間隔を小さくでき、効率的なチップの配置が可能である。これ以降のプロセスは実施形態１と同様に行う。
【００９３】
即ち、図１４（ｂ）（図１４（ａ）部の拡大図）に示すように、チップ３の電極５を開口するように、層間膜９を所定パターンに形成する。層間膜９の材料としては感光性絶縁樹脂等を用い、液状のものをスピンコートして塗布するか又は、ドライフィルをラミネーターで貼り付けてもよい。
【００９４】
次に、図１４（ｃ）に示すように、チップ３の電極５から配線２０を導出して溝１８内に配し、この配線２０と隣接チップ３の電極５から導出した配線２０が、溝１８内で連続するように形成する。勿論この配線も、既述した図４（ｈ）〜図５（ｍ）と同様にセミアディティブ法により形成するが、ここでは簡略に図示する。
【００９５】
次に、図１４（ｄ）に示すように、配線２０を含む上部の全面に保護膜２１を形成する。この材料としては、層間膜９と同様に感光性絶縁樹脂等を用いる。この場合、溝１８の部分とその他の部分との平坦性が得られない場合には、図１２に示したのと同様に、ディスペンス法又は印刷法等によって溝１８部を先に塗布後に、再度全体を塗布するようにしてもよい。
【００９６】
次に、図１４（ｅ）に示すように、裏面３６側の樹脂４を研削し、溝１８の底面の配線２０を露出させる。この研削はＳｉウェーハ裏面研削用のグラインダー等で行う。
【００９７】
次に、図１４（ｆ）に示すように、裏面に露出した配線２０の露出部２０ａに接続させて裏面３６の配線２２を形成する。この配線も上記と同様にセミアディティブ法にて行う。
【００９８】
次に、図１４（ｇ）に示すように、上記した層間膜９と同様の材料により裏面３６の保護膜２５を形成後に、電極５から導出した配線２０との接続孔２７を保護膜２１に形成することにより、表面３５側の外部端子１６を形成する。また、保護膜２５に裏面３６側に設けた配線２２との接続孔２４を形成することにより、この面の外部端子２３を形成する。そしてこのようなプロセスを疑似ウェーハ２９上で一括して行うことができる。
【００９９】
その後、切断線３７の位置で切断することにより、図１３に示したように、実施形態１と同等の機能を有し、両面に外部端子１６、２３を有する半導体装置５０Ａを得ることができる。そして、この半導体装置５０Ａは、実施形態１と同様に、外部端子の配置位置に関する設計上の自由度を有すると共に、図８のようにワンチップでのプリント基板への実装及び図９のような積層構造での実装、並びに図１０のように平置き構造で実装することもできる。
【０１００】
本実施の形態によれば、実施形態１とは溝１８の形状が異なるものの、実施形態１と同様な機能を有し、同様な効果を発揮できる半導体装置５０Ａを得ることができる上に、隣接するチップ３の間隔を小さくできることにより、同一の疑似ウェーハ２９に対し、チップ３の増配置によって生産の効率化が可能な利点を有している。
【０１０１】
実施形態４
図１５は、本実施の形態による半導体装置（図１に対応する）５０Ｂを示す。この半導体装置５０Ｂが上記した各実施の形態の半導体装置と異なる点は、チップ３の側面の樹脂４内における裏面３６側への配線の導出方法が、スルーホール状の垂直貫通孔を介していることであり、その他は上記した各実施の形態と同様な構成になっているが、前記した実施形態３と同様に、チップ３の間隔を小さくできる。この製造プロセスを図１６により説明する。
【０１０２】
図１６（ａ）は、図２５（ｆ）の拡大図と同様の状態の疑似ウェーハ２９に対し、チップ３の電極５を開口するように層間膜９が形成された状態である。
【０１０３】
次に、図１６（ｂ）に示すように、チップ３の側面の樹脂４内に、裏面３６側に配線２０を導出するためのブラインドホール３２をチップ３毎に間欠的に形成する（図１８参照）。このブラインドホール３２の深さＤもチップ３の厚さＴとの関係は、Ｄ＞Ｔとなっている。このブラインドホール３２は、例えばレーザー又はドリルによる切削等にて形成することができる。
【０１０４】
次に、図１６（ｃ）に示すように、チップ３の電極から導出した配線２０をブラインドホール３２を介して裏面３６側へ導びく。この配線もセミアディティブ法によるプロセス（図４（ｈ）〜図５（ｎ）参照）を経て形成するものであるが、ブラインドホール３２内に均一に十分なスパッタ膜を施すことにより、配線用の金属めっきでブラインドホール３２を埋め込むことが可能である。ここでは配線の詳細なプロセスは図示省略する。
【０１０５】
次に、図１６（ｄ）に示すように、チップ３上面の配線２０を含む全面に保護膜２１を形成する。保護膜２１の材料としては、層間膜９と同様に感光性絶縁樹脂を用い、ディスペンス法又は印刷法により塗布する。
【０１０６】
次に、図１７（ｅ）に示すように、裏面３６側の樹脂４を研削し、ブラインドホール３２に導びいた配線２０の露出部２０ａを形成する。この研削はＳｉウェーハの裏面研削用のグラインダー等で行う。
【０１０７】
次に、図１７（ｆ）に示すように、裏面３６に露出した配線２０の露出部２０ａに接続させて裏面３６の配線２２を形成する。これも例えば上記と同様にセミアディティブ法で行う。
【０１０８】
次に、図１７（ｇ）に示すように、層間膜９と同様の材料を用い、裏面３６側の保護膜２５を形成した後に、表面３５側の保護膜２１に、電極５から導出した配線との接続孔２７を形成することにより、表面３５側の外部端子１６を形成する。また、保護膜２５に、配線２０に接続した配線２２との接続孔２４を形成することにより、裏面３６側の外部端子２３を形成する。これらの外部端子１６、２３等の開口部の形成は、感光性絶縁樹脂からなる保護膜２１、２５に対するフォトリソグラフィ技術にて行うことができる。そして、このようなプロセスは疑似ウェーハ２９の製造工程において、一括に行うことができる。
【０１０９】
その後、切断線３７の位置で切断することにより、図１５に示したように、実施形態１と同等の機能を有し、両面に外部端子１６、２３を有する半導体装置５０Ｂを得ることができる。そしてこの半導体装置５０Ｂは、実施形態１と同様に、外部端子の配置位置の設計の自由度を有すると共に、図８のようにワンチップでのプリント基板への実装及び図９のような積層構造での実装もでき、図１０のように平置き構造で実装することもできる。
【０１１０】
図１８は、要部を平面図（配線のみ実線で示す。）で示した概略図であるが、本実施の形態の特徴は、実施形態１〜３においてチップ３の外側面に沿って形成する線状の溝とは異なり。間欠的に形成したブラインドホール３２（破線で表示した）を介して、配線２０を裏面３６へ導びいていることである。従って、チップ３の側面の樹脂４の強度を保つことができると共に、このように強度が保てることにより、更に後述する変形例（図１９参照）のような利点がある。
【０１１１】
図１９（ａ）は、実施形態４の変形例を示す概略図であり、図１６（ｂ）と同様の状態を示す。
【０１１２】
そして図１９（ｂ）は、裏面３６側の研削工程を示している。即ち、前記したように、間欠的に形成するブラインドホール３２であるため、チップ間の樹脂４の強度が保てることにより、裏面３６の研削が可能になる。
【０１１３】
従って、次は図１９（ｃ）に示すように、表面３５側の配線２０と裏面３６側の配線２２を、前記した各配線と同様にセミアディティブ法を用いて、同一のめっき工程にて形成することができる。上記の研削によりブラインドホール３２は、図１９（ｂ）に示すように貫通孔と化しているため、この両面同時めっきにより貫通孔内のめっきによる埋め込みも容易になる。
【０１１４】
次は、実施の形態４と同様に、所要のプロセスを経ることにより、図１９（ｄ）に示すような状態を形成することができる。従って製造工程を簡略して実施形態４と同様の構造及び機能を有する半導体装置５０Ｂが、疑似ウェーハ段階で一括して作製可能となる。
【０１１５】
本実施の形態によれば、チップ３の電極５から導出した配線２０を裏面３６へ導びく方法が、他の実施形態とは異なるものの、他の実施形態と同様の機能を有し、同等の効果を発揮できることに加え、隣接するチップ３の間隔を小さくし、チップ３の増配置による生産の効率化が図れると共に、チップ間の樹脂４の強度が保たれることにより、表裏両面の同時めっきも可能になり、製造工程の簡略化により更に生産性を向上することができる。
【０１１６】
図２０は、上記した各実施の形態に共通の変形例を示す図であるが、実施形態３の構造により説明する。
【０１１７】
即ち図２０（ａ）は、実施形態３において、裏面を研削する前の状態（図１４（ｄ））と同様の状態であるが、この例が他と異なる点は、既述した各実施形態のチップ３の厚みよりも厚いチップ３Ａを疑似ウェーハ２９に配置していることである。溝１８の深さＤは実施形態３と同一であるが、チップ３Ａの厚みＴ１は溝１８の深さＤよりも大きく、Ｄ＜Ｔ１となっている。
【０１１８】
図２０（ａ）の状態の疑似ウェーハ２９に対し、図２０（ｂ）に示すように、裏面３６側をチップ３Ａの大半が除去されるまで研削し、配線２０の底面の露出部２０ａを形成する。この研削によって、チップ３Ａの厚さは、前記した各実施の形態におけるチップ３の厚みよりも薄くなることもあるが、Ｓｉウェーハ上に形成されている半導体素子に影響を及ぼすことはない。これにより更に薄型の半導体装置を形成することが可能であり、特に積層構造のＭＣＭに好適である。
【０１１９】
次に図２０（ｃ）に示すように、研削したチップ３Ａの裏面を層間絶縁膜１４で被覆した後に、上記した実施形態３と同様のプロセスで処理を行う。即ち、裏面側に露出した配線２０の露出部２０ａに裏面３６の配線２２を接続し、図２０（ｄ）に示すように、裏面３６の保護膜２５を形成後に、保護膜２１に配線２０との接続孔２７を形成することにより、表面３５側の外部端子１６を形成し、また保護膜２５に裏面３６の配線２２との接続孔２４の形成により外部端子２３を形成する。これにより両面に外部端子１６、２３を有する半導体装置を疑似ウェーハ段階で一括して形成することができる。
【０１２０】
図２１は、他の変形例を示す図であるが、これも実施形態４を除く他の実施の形態に共通する。この例も実施形態３の構造により、上記の変形例（図２０）と同様のチップ３Ａを配した図により説明する。上記した変形例（図２０）に限らず、裏面３６の過剰な研削により、溝１８内の配線２０が局部的に断線された場合でも、この例の方法により断線部の接続を保つことができる。
【０１２１】
即ち、図２１（ａ）に示すように、溝１８内に導出した配線２０を形成後に、溝１８の底部の配線２０上に局部的に、例えばペースト４７等の如き導電性物質を配しておき、この上に図２１（ｂ）のように保護膜２１を形成する。
【０１２２】
以後は、図２０に示した変形例と同様に裏面３６を研削により部分的に除去するが、図２１（ｃ）に示すように、過剰な研削により露出されるべき配線２０が断線され、露出部２０ａが分断されても、疑似ウェーハ２９全体の強度が保てるような局部的な断線であれば、疑似ウェーハ２９が破壊されることなく、ペースト４７によって断線部の接続を保つことができる。
【０１２３】
従って、図２１（ｄ）に示すように、研削によって露出したチップ３Ａの裏面を層間絶縁膜１４で被覆後に、上記した図２０と同様のプロセスを経て、図２１（ｅ）のように、両面に外部端子１６、２３を有する半導体装置を疑似ウェーハ段階で一括形成できる。
【０１２４】
図２２は、他の変形例を示す図であるが、これも実施形態４を除く他の実施の形態に共通する。この例も実施形態３の構造により、上記した変形例と同様のチップ３Ａを配した図により説明するが、この例は上記した変形例（図２１）のように、断線時のために予めペーストを配しておくのではなく、研削し過ぎにより断線した場合に施す処理法である。
【０１２５】
即ち、図２２（ａ）の状態から、裏面３６側を研削して除去することにより、図２２（ｂ）に示すように、研削過剰により溝１８底部の配線に断線部２０ｂが生じた場合は、図２２（ｃ）に示すように、断線部２０ｂに例えばドリル等で孔３４をあける。この孔３４は、孔３４の内壁面に配線２０の断面積をできるだけ大きく露出させ、しかも浅い方がよい。そして孔３４を形成後に、研削によって露出したチップ３Ａの裏面を層間絶縁膜１４で被覆する。図２３は、孔３４をあけた状態を示す底面図（孔を誇張図示した）である。
【０１２６】
次に、図２２（ｄ）に示すように、裏面３６に配線２２をセミアディティブ法によって形成することにより、断線部２０ｂに形成した孔３４がスパッタ膜とめっき膜とによって同時に埋められるため、断線した配線２０が接続される。
【０１２７】
次は、所定のプロセスを経ることにより、図２２（ｅ）に示すように、両面に外部端子１６、２３を有する半導体装置が形成され、上記した処理を含む一連の処理を疑似ウェーハ段階で一括して行うことができる。
【０１２８】
また、上記した各実施の形態及び変形例の半導体装置は、図２４に示すように外部端子は裏面だけに設けてもよい。この例を実施形態１（図１参照）の構造で説明する。
【０１２９】
図示の如く、この半導体装置５０ｃは、チップ３の電極５から導出した外部端子を表面３５側には設けず、裏面３６側のみに設けるものである。従って、既述した図１と同様の製造プロセスによって形成され、外部端子２３を裏面３６側のみに形成している。
【０１３０】
図２４において、外部端子２３も図１と全く同じ位置になっているが、例えば実装基板の外部端子の位置に合せるなど、任意の位置に配置が可能であるため設計の自由度が大きく、実装時の熱ストレスを緩和し、チップへの影響を最小限にすることのできる位置に外部端子を配置できると共に、プリント基板へフェイスアップで実装できる。
【０１３１】
上記した各実装の形態は、本発明の技術的思想に基づいて種々に変形が可能である。
【０１３２】
例えば、チップ３の表面３５の電極５から導出した配線２０を裏面３６側へ導びく方法は、実施形態１のＷ字状の溝、実施形態３の梯形溝、実施の形態４のブラインドホールに限らず、これ以外の適宜な方法であってよく、これらの溝１８の形成方法もダイサー及び入れ子以外の方法が可能である。
【０１３３】
また、配線２０、２２の形成方法は、めっきに限らず、物理蒸着、又はスクリーン印刷により形成してもよい。また、積層構造の外部端子間の接続やプリント基板への実装時の外部端子の接続は、はんだバンプに限らずＡＣＦ（異方性導電フィルム）を用いてもよい。
【０１３４】
また、チップ３の外部端子をチップの表面及び裏面のうち少なくとも裏面に形成することは、半導体チップ以外の例えば発光ダイオード又はフォトダイオード等のチップ部品に適用できる。
【０１３５】
【発明の作用効果】
上述した如く、本発明によれば、チップ部品の複数個が、電極面以外の少なくとも側面及び他方の面が保護物質で覆われた疑似ウェーハ工程を経て形成されているので、チップ化後のハンドリング時にチップ部品が保護され、ハンドリングが容易となると共に、保護物質の位置で切断してチップ部品に個片化することができるために、切断時にチップ部品がダメージ（亀裂や歪み等）を受けることがない。
【０１３６】
そして、このチップ部品の実装基板への実装時には、少なくとも他方の面の外部端子を介して接続が可能であり、また、他方の面の任意の位置に外部端子を設けることができ、設計の自由度が大きいと共に、この外部端子を介して実装可能であるために、実装時の熱ストレスによるチップ部品の一方の面側（電極面側）への影響を緩和することができる。
【０１３７】
この場合、この保護物質によってチップ部品に対し絶縁分離を行いながら、保護物質の側面又は内部を通して一方の面の電極を他方の面側の外部端子に導びくための配線を形成することができ、かつ、保護物質によって前記配線を保護することができる。
【０１３８】
そして、このチップ部品を個片化した半導体装置を用いて、複数のチップ部品の積層構造又は並列配置のマルチチップモジュールであっても、この複数のチップ部品間の接続をこれらのチップ部品の外部端子を介して行うことができる。
【図面の簡単な説明】
【図１】本発明の実施形態１による半導体装置を示す概略断面図である。
【図２】同、半導体装置の積層例を示す概略断面図である。
【図３】同、半導体装置の作製プロセスを示す概略断面図である。
【図４】同、半導体装置の作製プロセスを示す概略断面図である。
【図５】同、半導体装置の作製プロセスを示す概略断面図である。
【図６】同、半導体装置の作製プロセスを示す概略断面図である。
【図７】同、半導体装置の要部を示し、（ａ）は概略断面図、（ｂ）は概略底面図である。
【図８】同、半導体装置の実装例を示す概略断面図である。
【図９】同、半導体装置の実装例を示す概略断面図である。
【図１０】同、半導体装置の実装例を示す概略断面図である。
【図１１】本発明の実施形態２による半導体装置の作製プロセスを示す概略断面図である。
【図１２】同、実施形態１及び２の変形例を示す概略断面図である。
【図１３】本発明の実施形態３による半導体装置を示す概略断面図である。
【図１４】同、半導体装置の作製プロセスを示す概略断面図である。
【図１５】本発明の実施形態４による半導体装置を示す概略断面図である。
【図１６】同、半導体装置の作製プロセスを示す概略断面図である。
【図１７】同、半導体装置の作製プロセスを示す概略断面図である。
【図１８】同、半導体装置の要部を示す概略平面図である。
【図１９】同、実施形態４の変形例の作製プロセスを示す概略断面図である。
【図２０】同、実施形態３の構造で示した変形例の作製プロセスを示す概略断面図である。
【図２１】同、実施形態３の構造で示した他の変形例の作製プロセスを示す概略断面図である。
【図２２】同、実施形態３の構造で示した更に他の変形例の作製プロセスを示す概略断面図である。
【図２３】図２２（ｃ）の状態における要部を示す概略底面図である。
【図２４】実施の形態１の構造で示した変形例の概略断面図である。
【図２５】従来例による半導体装置の作製プロセスを示す概略断面図である。
【図２６】同、半導体装置の作製プロセスを示す概略断面図である。
【図２７】同、半導体装置の作製プロセスを示す概略断面図である。
【図２８】同、半導体装置の実装例を示す概略断面図である。
【図２９】同、半導体装置の実装例を示す概略断面図である。
【符号の説明】
１…石英基板、２…粘着シート、３、３Ａ…良品ベアチップ（半導体チップ）、
４…樹脂、４ａ…保護膜、５…電極、２４、２７…接続孔、７…ＳｉＯ２膜、
８…パッシベーション膜、９、１４…層間絶縁膜、１０…スパッタ膜、
１１…レジストマスク、１１Ａ…フォトレジスト膜、１２Ａ…めっき膜、
２０、２２…配線、２１、２５、３８…保護膜、１６、２３…外部端子、
１８…溝、２０ａ…露出部、２０ｂ…断線部、２９…疑似ウェーハ、
３０…入れ子、３１…外側面、３２、３４…孔、３３…はんだバンプ、
３５…表面、３６…裏面、３７…切断線、３９…プリント基板、４０…電極、
４２…マスク、４３ａ、４３ｂ…開口部、４５…露光光、４７…ペースト、
５０…半導体装置、Ｌ…紫外線、Ｔ…半導体チップの厚み、Ｄ…溝の深さ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and its manufacturing method, a pseudo wafer and its manufacturing method, and a multi-chip module.
[0002]
[Prior art]
Conventionally, in response to the demand for smaller, lighter, and faster portable electronic devices, as one method, a plurality of functions are integrated into one chip (system LSI) by increasing the integration and miniaturization of ICs. It is difficult to realize a system LSI at low cost due to a problem such as an increase in manufacturing cost due to a decrease in yield. On the other hand, an MCM (Multi Chip Module) in which a plurality of semiconductor chips are packaged in one package has been proposed.
[0003]
In the MCM, a semiconductor chip is arranged on a multilayer wiring board. However, if the connection terminal pitch of the semiconductor chip to be mounted becomes narrow, it becomes difficult to manufacture the wiring board, and the cost of the board increases. In addition, since connection is performed by bumps, wire bonding, tabs, or the like, the number of connection terminals is limited, and the area in plan view is larger than the total area in plan view of the mounted semiconductor chip. Furthermore, there is a problem that signal transmission is slowed down and performance is reduced.
[0004]
Regarding the MCM manufacturing technique, it is disclosed that wiring is performed with high productivity by attaching a plurality of bare chips on a support substrate and wiring them so that their surfaces become flat (see Patent Document 1 described later). . In addition, by bonding a plurality of semiconductor chips manufactured for each function adjacent to each other, a quadrangular composite chip is attached to a wafer, and the active surface of the chip is flattened and exposed to the outside of the chip. It is disclosed that a composite chip having a reduced area is formed in a small package by wiring from a connection terminal (see Patent Document 2 described later). Furthermore, it is disclosed that after attaching a good chip to a supporting substrate, a protective substance is applied and peeled off to produce a pseudo wafer, and wiring is performed thereon by a semiconductor process (see Patent Document 3 described later). reference).
[0005]
Among these, Patent Document 3 (hereinafter, referred to as the prior application invention) filed by the present applicant discloses a method in which semiconductor chips are cut out from a wafer without any distinction between in-house and other companies, and then open / short or DC (direct current). Only semiconductor bare chips that have been confirmed as non-defective by voltage measurement are rearranged on a pseudo wafer and subjected to predetermined manufacturing steps to produce chip-shaped electronic components. The manufacturing process is shown in FIG.
[0006]
That is, FIG. 25A shows a quartz substrate 1 used as a temporary support substrate. However, since the process of heating the substrate is 400 ° C. or less, an inexpensive glass substrate can be used, and the quartz substrate 1 can be used repeatedly.
[0007]
Next, as shown in FIG. 25B, for example, an acrylic pressure-sensitive adhesive sheet 2 whose adhesive strength is reduced when irradiated with ultraviolet rays is attached onto the quartz substrate 1.
[0008]
Next, as shown in FIG. 25C, a plurality of non-defective bare chips 3 confirmed as non-defective are attached to the adhesive sheet 2 with the chip surface (device surface) 28 arranged downward. The non-defective bare chip 3 may be diced in a normal wafer process and taken out of a stretched state of a used dicing sheet (not shown), or may be transferred from a chip tray.
[0009]
Next, as shown in FIG. 25D, an organic insulating resin, for example, an epoxy resin 4 is uniformly applied on the non-defective bare chip 3 by a spin coating method or a printing method.
[0010]
Next, as shown in FIG. 25 (e), ultraviolet rays are radiated from the back side 51 of the quartz substrate 1 to weaken the adhesive force of the adhesive sheet 2, and a plurality of non-defective products whose side and back surfaces are continuously solidified with the resin 4 The pseudo wafer 29 on which the bare chip (hereinafter, sometimes referred to as a semiconductor chip, a chip or a chip component) 3 is disposed is separated from the quartz substrate 1 by the bonding surface 52.
[0011]
Next, as shown in FIG. 25 (f), the pseudo wafer 29 is turned over so that the non-defective bare chip surface 28 (device surface) faces upward. The lower figure is an enlarged view of a part of the pseudo wafer 29. As shown in FIG.2An A1 electrode pad 5 and a passivation film 8 are formed via a film 7.
[0012]
Thereafter, a Ni plating layer is selectively formed only on the upper surface of the opened Al electrode pad 5 by an electroless plating method, and the solder paste disposed thereon is heated and melted to form solder bumps on the wafer collectively. By measuring the electrical characteristics again by the probe test, only non-defective chips are selected more reliably.
[0013]
After the semiconductor chip 3 formed as described above is singulated into one chip, it is mounted on the electrode 40 of the circuit board 39 via the solder bump 33 as shown in FIG. 28, for example, or as shown in FIG. By arranging the chips 3 in parallel and performing the rearrangement wiring 12 (wiring performed by drawing the wiring in the semiconductor chip to an arbitrary position on the chip) between the plurality of chips 3, the circuit configuration is performed and the MCM is implemented. Can be configured. Although not shown, wiring is led out from the electrode pad 5 of the semiconductor chip 3 to the insulating layer through the connection hole, and furthermore, such a structure is stacked to form a multilayer structure. It is also possible to deal with an increase in the number of pins by performing relocation wiring at positions, and these can be collectively performed on the pseudo wafer 29.
[0014]
As described above, according to the invention of the prior application, since the surface other than the electrode surface of the semiconductor chip (that is, the side surface and the back surface of the chip) is protected by the continuous protective material, the chip is protected in handling after chip formation, and the handling is improved. It will be easier.
[0015]
In addition, since only non-defective products cut from the semiconductor wafer are selected and rearranged, a pseudo wafer consisting of all non-defective chips can be obtained, and bump processing can be performed on the arranged non-defective chips in a batch of wafers. In addition, a low-cost bump chip can be formed, and when a semiconductor chip is cut from a pseudo wafer, a portion of a protective material between the chips is cut, so that the semiconductor chip body is adversely affected (such as distortion, burrs, cracks, etc.). Damage) can be easily cut.
[0016]
In addition, since the side and back surfaces of the chip are covered with the protective substance, Ni electroless plating can be performed. Then, solder bump processing and the like can be easily performed not only on in-house manufactured wafers but also on bare chips purchased from other companies.
[0017]
In addition, there are few cases in which all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker. The SRAM, flash memory, microcomputer, and CPU (Central Processing Unit) are separately manufactured by the semiconductor maker that is good at each. It has excellent features such as that they can be supplied as MCM and can be converted to MCM.
[0018]
When the relocation wiring of the semiconductor chip 3 of the above-mentioned prior invention is performed on the pseudo wafer 29, it can be performed, for example, by a method as shown in FIGS.
[0019]
FIG. 26A shows a lower view (a partially enlarged view) of the above-described FIG. 25F. That is, the electrode pad 5 (hereinafter, referred to as an electrode) made of Al is arranged on the integrated semiconductor chip 3 with the side surface and the back surface covered with the resin 4 as the protective substance constituting the pseudo wafer 29. A passivation film 8 is formed such that electrode 5 is exposed.
[0020]
Wiring to be formed thereafter is formed by a semi-additive method, but is shown in a simplified manner. First, as shown in FIG. 26 (b), after forming an interlayer insulating film 9 so as to cover the passivation film 8, as shown in FIG. 26 (c), a seed metal to be an electrode for plating is formed on the entire upper surface. Then, a Ti sputtered film 10 having good adhesion to Al is formed.
[0021]
Next, as shown in FIG. 26D, after forming a photoresist film 11 on the sputtered film 10 by a photolithography technique, as shown in FIG. Form 12A. Thus, by using Ti having good adhesion to Al as a seed metal, Cu can be easily plated on the Ti sputtered film 10.
[0022]
Next, as shown in FIG. 27F, the photoresist film 11 is removed, and the sputtered film 10 under the photoresist film 11 is removed by wet etching or the like, whereby the rearranged wiring 12 is formed. .
[0023]
Next, as shown in FIG. 27 (g), after covering the entire upper surface with a protective film 13, a connection hole 6 with the wiring 12 is formed in the protective film 13 as shown in FIG. The terminal 15 is exposed.
[0024]
According to the above-described method, a plurality of or a plurality of types of chip components can be arranged in parallel on the same pseudo wafer 29, and relocation wiring for forming an MCM circuit can be performed at a wafer level at a time. In addition, the prior invention selects and rearranges only non-defective chips cut out of a semiconductor wafer, covers the side and back surfaces with a resin, integrates them, further performs a characteristic test, and performs a pseudo test in which 100% non-defective chips are arranged. These chips have excellent features such as reallocation of wiring between these chips on a wafer at a time, and formation of an MCM at a pseudo wafer stage.
[0025]
[Patent Document 1]
JP-A-7-202115 (left column of page 5, FIGS. 1 and 3)
[Patent Document 2]
JP-A-11-330350 (page 6, right column, FIGS. 5 and 6)
[Patent Document 3]
JP 2001-308116 A (page 5 left column, page 7 right column and FIG. 2)
[0026]
[Problems to be solved by the invention]
However, conventionally, in the prior application, since the external terminals of the semiconductor chip 3 are formed only on the front side of the pseudo wafer 29, connection to external devices or the like cannot be performed on the rear side, and the MCM having a multilayer structure has a problem. There was a problem that cannot be formed.
[0027]
Therefore, an object of the present invention is to provide a semiconductor device having external terminals that can be easily connected between a plurality of chip components and to external devices, and that can be formed at low cost, a method of manufacturing the same, a pseudo wafer, and a method of manufacturing the same. Another object of the present invention is to provide a multi-chip module.
[0028]
[Means for Solving the Problems]
That is, the present invention provides a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface and the other surface are covered with a protective substance, A semiconductor device (hereinafter, referred to as a semiconductor device of the present invention), wherein external terminals are formed on at least the other surface of the one surface and the other surface opposite to the one surface. ).
[0029]
According to the present invention, an electrode is provided on one surface side, and a plurality of chip components in which at least a side surface other than the electrode surface and the other surface are covered with a protective material are integrated by the protective material. Producing a pseudo wafer;
Forming external terminals of the electrodes of the chip components in the pseudo wafer on at least the other surface of the one surface and the other surface opposite to the one surface,
Cutting at least the protective material between the plurality of chip components; and
The present invention relates to a method for manufacturing a semiconductor device (hereinafter, referred to as a method for manufacturing a semiconductor device of the present invention).
[0030]
According to the semiconductor device and the method of manufacturing the same of the present invention, since the chip component provided with the electrode on one surface side is covered with the protective material on at least the side surface and the other surface other than the electrode surface, The chip components are protected during handling, which makes handling easier and the chip components can be cut into individual chip components by cutting at the position of the protective substance. I will not receive it.
[0031]
In this structure, the external terminals of the chip component are formed on at least the other surface of the one surface and the other surface on the opposite side. Therefore, at least when the chip component is mounted on the mounting board, Connection can be made via external terminals on the other surface, and external terminals can be provided at any position on the other surface, so that the degree of freedom in design is large and mounting via these external terminals is possible. For this reason, the influence on the one surface side (electrode surface side) of the chip component due to the thermal stress at the time of mounting can be reduced.
[0032]
In this case, since the side surface and the other surface are covered with the protective material, the electrode on one surface is connected to the other surface side through the side surface or the inside of the protective material while insulating and separating the chip component with the protective material. Wiring for leading to an external terminal can be formed, and the wiring can be protected by a protective substance.
[0033]
According to the present invention, an electrode is provided on one surface side, and a plurality of chip components in which at least a side surface other than the electrode surface and the other surface are covered with a protective material are integrated by the protective material. A pseudo wafer (hereinafter referred to as a pseudo wafer) in which external terminals of the electrodes of the chip component are formed on at least the other surface of the one surface and the other surface opposite to the one surface. This is referred to as a pseudo wafer of the invention.).
[0034]
According to the present invention, an electrode is provided on one surface side, and a plurality of chip components in which at least a side surface other than the electrode surface and the other surface are covered with a protective material are integrated by the protective material. The method for manufacturing a pseudo wafer, comprising a step of forming external terminals of the electrodes of the chip components in the pseudo wafer on at least the other surface of the one surface and the other surface opposite thereto. (Hereinafter, referred to as a pseudo wafer manufacturing method of the present invention).
[0035]
According to the pseudo wafer and the method for manufacturing the same of the present invention, a plurality of chip components provided with electrodes on one surface side are covered with a protective substance on at least the side surface and the other surface other than the electrode surface, and integrated. In this way, only non-defective chips are selected and rearranged, enabling low-cost bump processing of chip components all at once on a pseudo wafer consisting of all non-defective chips, as well as protection substances. Since the chip component can be cut into individual pieces by cutting at the position, the chip component is not damaged (distorted, cracked, etc.), and the side surface and the other surface of the chip component are covered with the protective substance. Therefore, Ni electroless plating can be performed, and solder bump processing and the like can be performed irrespective of whether it is made in-house or made by another company.
[0036]
Then, since the external terminals of the chip component are formed on at least the other surface of one surface and the other surface on the opposite side, mounting of the chip component obtained by cutting the pseudo wafer is performed. At the time of mounting on a substrate, it is possible to provide a pseudo wafer having chip parts with good reproducibility, which can be connected via at least the external terminal on the other surface, and which has the same effect as the semiconductor device of the present invention described above. it can.
[0037]
According to another aspect of the present invention, there is provided a multi-chip module (hereinafter, referred to as a multi-chip module) configured by the above-described semiconductor device of the present invention, wherein the plurality of chip components included in the semiconductor device are connected to each other via the external terminals. Multi-chip module).
[0038]
According to the multi-chip module of the present invention, since the chip components constituting the multi-chip module are configured by the above-described semiconductor device of the present invention, the multi-chip module has a multilayer structure of a plurality of chip components or a multi-chip module having a parallel arrangement. However, the connection between the plurality of chip components can be made via the external terminals of these chip components.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
In the above-described semiconductor device and the method for manufacturing the same, the pseudo wafer, the method for manufacturing the same, and the multi-chip module according to the present invention, the external surface of the one surface (electrode surface or surface) is provided on the outer surface of the protective material on the side surface. A conductor for connecting to an external terminal on the other surface (back surface) is formed, and the conductor provides an inclined outer surface or a vertical through hole in the protective material, and the inclined outer surface or the vertical through hole is formed in the inclined outer surface or the vertical through hole. It is desirable that it is formed because it facilitates formation of a conductor such as a plating film, and facilitates formation of external terminals on the other surface.
[0040]
In this case, a concave portion (for example, a groove having an inclined surface, or a through hole) is formed in the protective material on the side surface between the plurality of chip components, and the external terminal on one surface and the other surface are formed on this surface. After forming a conductor for connecting to the external terminal of the above, at least the protective material is partially removed from the other surface side by grinding, and the conductor is exposed on the removed surface. It is desirable to form the external terminal on the other surface connected to the body.
[0041]
Further, by forming the concave portion deeper than the thickness of the chip component, the conductor is partially removed to leave the conductor on the surface of the concave portion having an inclined surface or a vertical surface. It is desirable to expose the conductor.
[0042]
In addition, under the insulating protective film for forming the external terminal on the one surface, the material of the insulating protective film in the concave portion may have significantly different physical properties from the material of the protective material on the side surface. When the flattening of the concave portion cannot be obtained, an insulating material (the same material as the protective material on the side surface) different from the insulating protective film is provided on the conductor on the inclined outer surface for the concave portion. Alternatively, an insulating protective film may be formed thereon to form a double structure.
[0043]
Further, a conductive substance (for example, a paste) may be provided in contact with the outer surface of the conductor under the insulating protective film for forming the external terminal on the one surface. This makes it possible to compensate for a poor connection of the conductor due to excessive removal of the protective material on the other surface side.
[0044]
Then, the pseudo wafer having the chip component determined to be non-defective by the characteristic measurement is produced, and further, the characteristics of the chip component are measured again in the state of the pseudo wafer, and a non-defective chip component or a chip-shaped electronic component is measured. Selection is desirable in terms of increasing the yield.
[0045]
Thereby, a pseudo wafer for manufacturing the above-described semiconductor device is obtained, and the external terminals for connecting the plurality of chip components obtained by singulating the same are connected to the one surface side of one chip component ( The multi-chip module is formed on the electrode surface) and on the other surface side (rear surface side) of the other chip component, and can form a multi-chip module having a laminated structure in which the external terminals are connected. The external terminal for connecting a component is formed on the one surface side (electrode surface side) or the other surface side (back surface side), and a multi-unit (parallel arrangement) structure in which the external terminals are connected is provided. Chip modules can also be formed.
[0046]
Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0047]
Embodiment 1
FIG. 1 shows a semiconductor device 50 of the present embodiment. As shown in the drawing, the wiring 20 led out from the electrode 5 of the chip component 3 is wired obliquely toward the back surface 36 in the resin 4 on the outer surface 31 of the chip 3, and its tip is bent symmetrically in the opposite direction, The lower end of the wiring 20 is connected to the wiring 22 provided on the back surface 36. Then, a part of the extracted wiring 20 is exposed on the front surface 35 side near the electrode 5 to form the external terminal 16 on the front surface 35, and the external terminal 23 on the back surface 36 exposes a part of the wiring 22. Is formed. The upper and lower external terminals 16 and 23 are opposed to each other, and the external terminals 16 and 23 are formed in the protective films 21 and 25 by the openings of the connection holes 27 and 24 with the wirings 20 and 22, respectively.
[0048]
FIG. 2 shows a diagram in which the above-described semiconductor devices 50 are stacked. As described above, since the upper and lower external terminals 16 and 23 are opposed to each other, the external terminal 16 on the front surface 35 of the lower semiconductor device 50 and the external terminal 23 on the rear surface 36 of the upper semiconductor device 50 are For example, since the connection can be made via the solder bumps 33 or the like, an MCM or the like having a laminated structure can be formed, and the size of the MCM can be reduced.
[0049]
FIG. 3 to FIG. 5 show a manufacturing process from a pseudo wafer process to individualization into a semiconductor device in order to produce the semiconductor device 50 of the present embodiment. FIGS. 25A to 25E are the same as FIGS. 25B to 25F in the prior invention, and the description of the process during this period will be omitted.
[0050]
However, this embodiment is different from the prior application invention in that the external terminals are also formed on the back surface 36 side of the chip component 3, so that the resin 4 on the outer surface 31 of the chip 3 is guided to the back surface 36 side. The wiring 20 is obliquely led out, and the wiring 22 connected thereto is provided. The external terminals 16 are exposed on the front surface 35 by exposing a part of the wiring 20 and the external terminals 16 are exposed on the back surface 36 by exposing a part of the wiring 22. External terminals 23 are provided, and external terminals are formed on both surfaces of the semiconductor device 50.
[0051]
Therefore, as shown in FIG. 3F, in order to derive the wiring obliquely, as shown in FIG. The groove 18 is cut out and formed with a dicer or the like. The groove 18 is formed deeper (D> T) than the thickness T of the chip 3 arranged on the pseudo wafer 29, and the thickness or the warp or strength of the pseudo wafer 29 is sufficient to withstand the subsequent wiring forming process. It is necessary to form a pseudo wafer so that it can be left. The groove 18 may be formed at the time of molding the resin 4 before disposing the chip 3.
[0052]
Further, if the angle of the W-shaped groove 18 is an acute angle, it is difficult to form wiring thereafter, so it is preferable to form the W-shaped groove 18 at an angle in consideration of the wiring forming process. If possible, it is preferable to form at an obtuse angle of more than 45 degrees.
[0053]
FIG. 4 (g) is an enlarged view of a portion A in FIG. 3 (f). As in FIG. 26 (a), the side and back surfaces of the chip 3 are covered with the resin 4 and integrated, The passivation film 8 is formed so that the electrode 5 of the chip 3 is exposed.
[0054]
Next, as shown in FIG. 4H, after forming an interlayer film 9 in a predetermined pattern by photolithography so as to open the electrode 5 of the chip 3, a sputtered film 10 is formed on the entire surface of the interlayer film 9. I do. Since the surface of the passivation film 8 is rough, the interlayer film 9 is indispensable for flattening the passivation film 8, and the passivation film 8 is flattened by forming the interlayer film 9, whereby a wiring to be formed later can be formed uniformly.
[0055]
A photosensitive insulating resin or the like is used as a material of the interlayer film 9 and a liquid material is spin-coated and applied, or a dry film is attached by a laminator or the like. At this time, if the W-shaped groove 18 is at an acute angle, the thickness of the interlayer film 9 in the groove portion becomes thick, and the groove 18 may be filled with the interlayer film 9 and become shallow. It is necessary that the entirety be applied thinly by using it and be formed uniformly so that the thickness of the interlayer film 9 in the W-shaped groove does not increase.
[0056]
Next, lead wires for forming external terminals of the electrodes 5 of the chip 3 are formed. This wire is formed by, for example, a semi-additive method (sputter film formation → plating resist formation → plating → plating resist peeling) performed in the following process. (→ sputter film etching).
[0057]
First, as shown in FIG. 4 (i), as a seed metal serving as a plating electrode on the interlayer film 9, a positive type Is formed.
[0058]
Next, as shown in FIG. 4J, an exposure mask 42 having a pattern opening 43a is arranged on the photoresist film 11A, and the photoresist film 11A is exposed. The resist film 11A under the pattern opening 43a of the mask 42 is cured by the exposure light 45, and a part of the resist mask 11 is formed.
[0059]
Next, as shown in FIG. 5K, another pattern opening 43b of the exposure mask 42 is arranged at a predetermined position, and the photoresist film 11A is exposed. By this exposure, the central region of the W-shaped groove 18 which will be a cutting position at the time of singulation is hardened, and another portion of the resist mask 11 is formed. As the exposure mask 42, the same mask may be selectively used as described above, or different masks may be used.
[0060]
When exposing the photoresist film 11A, a mask 42 capable of exposing the pattern openings 43a and 43b at the same time may be used and may be exposed at the same time. Since there is a large difference in the thickness of the substrate and the depth of focus, the portion of the groove 18 and the photoresist film on the chip 3 may not be simultaneously resolved. Therefore, in this case, it is preferable to separately expose the groove 18 and the chip 3 as described above.
[0061]
Next, as shown in FIG. 5 (l), by developing the exposed photoresist film 11A, a resist mask 11 is formed in the cured portion, and Cu is electroplated using the mask as a mask to form a back surface. Since the path for leading the wiring to the 36 side is an inclined surface, plating is easy to be applied, and as shown in FIG. 5 (m), the plating film 12A for forming the wiring is formed well without being disconnected. You.
[0062]
Next, as shown in FIG. 6 (n), after the resist mask 11 is peeled and removed, the sputtered film 10 under the resist mask 11 is removed by wet etching or the like, so that the rearranged wiring 20 is formed. Here, the sputtered film is regarded as a part of the wiring 20, and is not shown in the drawings thereafter.
[0063]
Next, as shown in FIG. 6 (o), a protective film 21 is formed on the entire upper surface including the wiring 20.
[0064]
Here, when the material used for the protective film 21 is significantly different from the material of the resin 4 in physical properties (linear expansion coefficient, Young's modulus, curing shrinkage, etc.), or the groove 18 is sufficiently flattened. If not, as shown in FIG. 12, a protective film 21a may be formed only in the groove 18 before the protective film 21 is formed, and a two-layer structure with the protective film 21 formed thereafter may be adopted. As the protective film 21a, the same material as the resin 4, a photosensitive insulating resin, or the like is used, and is formed only in the groove 18 by a dispense method or a printing method.
[0065]
Next, as shown in FIG. 6 (p), the resin 4 is ground from the back surface 36 to expose the wiring 20 formed at the bottom of the groove 18. Grinding is performed by a grinder or the like for grinding the back surface of the Si wafer.
[0066]
The present embodiment is characterized in that the wiring 20 is ground so that the wiring 20 is exposed at the bottom portion of the groove 18, and the exposed portion 20 a of the exposed wiring 20 is connected to the wiring 22 on the back surface 36 side thereafter. .
[0067]
In this case, the area of the exposed portion 20a is preferably as large as possible. Therefore, in order to widen the exposed portion 20a, the chip 3 may be ground to such an extent that the back surface of the chip 3 is slightly ground. However, if the shaving is excessive, the wiring 20 at the bottom of the groove will be broken. Therefore, as long as D> T (that is, the groove is deeper than the chip thickness) is maintained, the groove 18 may be formed to be shallow in advance.
[0068]
Next, as shown in FIG. 6 (q), the wiring 22 serving as an external terminal on the back surface 36 side is formed. This wiring is formed by, for example, a semi-additive method (not shown here) similarly to the wiring 20.
[0069]
Next, as shown in FIG. 6 (r), a protective film 25 is formed in a predetermined pattern on the wiring 22 on the back surface 36 in a predetermined pattern in the same manner as the interlayer film 9 on the front surface 35 so as to open a portion to be the external terminal 23. Form. The material of the protective film 25 can be formed by using the above-described photosensitive insulating resin or the like and performing the same process as the interlayer film 9. Reference numeral 37 denotes a cutting line for singulation, and a semiconductor device 50 having external terminals 16 and 23 on both surfaces is obtained as shown in FIG. 1 by cutting at this position and singulation. . Then, since the portion other than the electrode surface of the chip 3 is protected by the continuous resin 4, the chip is protected in handling after chip formation, handling is easy, and the derived wiring 20 is separated from the chip 3 by the resin 4. Protected while insulated.
[0070]
Also, since only the non-defective chips 3 are selected and rearranged, a pseudo wafer 29 in which all the non-defective chips are formed of non-defective chips can be obtained. Yes, external terminals can be formed at low cost, and when the chip 3 is cut out from the pseudo wafer 29, the resin 4 on the side surface 31 is cut off, so that damage to the chip 3 body (distortion, burrs, cracks, etc.) is prevented. It can be cut easily with holding down.
[0071]
Moreover, since the side surface 31 and the back surface 36 of the chip 3 are covered with the resin 4, Ni electroless plating can be performed.
[0072]
As described above, the process of forming the external terminals for each chip 3 on the pseudo wafer 29 has been described with reference to the cross-sectional view. FIG. 7A is a partial plan view, and FIG. FIG. 3 is a schematic diagram also shown as a bottom view thereof, showing the wiring 20 led out between the adjacent chip 3 and the wiring 22 on the back surface 36. The wiring 20 on the 35 side and the wiring 22 on the back surface 36 are shown by solid lines.
[0073]
That is, in order to form an external terminal, the wiring 20 derived from the electrode 5 of the chip 3 is drawn from the electrode 5 arranged on each side of the chip 3 (only one side is shown in FIG. 7). 7, and is drawn to the back surface 36 side along the shape of the W-shaped groove 18 provided in the resin 4 between the chips.
[0074]
As described above, the W-shaped groove 18 is formed in the front surface 35 of the pseudo wafer 29, and the wiring 20 formed in the W-shaped groove 18 derived from the electrode 5 of the chip 3 is connected to the back surface 36 of the pseudo wafer 29. Is ground and exposed, and a part of the wiring 22 connected to the exposed portion 20a is exposed to form the external terminal 23 on the back surface 36 side. The external terminals can be formed on the back surface at a low cost, and the external terminals are formed on both surfaces, so that an MCM having a stacked structure (stack structure) can be realized. In addition, since the external terminals 16 and 23 are located near the side surface of the chip 3, there is an advantage that the chip 3 is hardly affected by distortion or warpage due to thermal stress during mounting.
[0075]
8 to 10 are views showing a typical mounting example of the semiconductor device 50 formed as described above. After forming external terminals in the pseudo wafer stage as described above, the semiconductor device 50 is singulated. This is a mounting example in which the device 50 is mounted on a printed circuit board 39.
[0076]
FIG. 8 shows an example. Since the semiconductor device 50 according to the present embodiment has the external terminals 16 on the front surface 35 side and the external terminals 23 on the rear surface 36 side, wiring such as wire bonding is applied to the electrode terminals 40 of the printed circuit board 39. The connection can be made face-up via the solder bumps 33 or the like without the need. In this case, the external terminals 16 and 23 of the semiconductor device 50 are arranged to face each other, but the external terminals 23 on the back side may be arranged in accordance with the positions of the electrode terminals 40 of the printed circuit board 39. That is, unlike the electrode surface side, there is no positional restriction such as avoiding the active area of the chip 3 on the rear surface side, so that the degree of freedom in design is large and external terminals can be formed at arbitrary positions.
[0077]
FIG. 9 shows another example of mounting, in which the semiconductor device 50 has a laminated structure like FIG. 2 described above, and a plurality of (two or more layers in FIG. 9 may be used) semiconductor devices 50 are printed circuit boards 39. It is in the state of being mounted on. In this way, in the laminated structure, since the external terminals 16 on the front surface 35 and the external terminals 23 on the rear surface 36 are arranged to face each other, they can be easily connected via the solder bumps 33 and the like. Also in this case, the external terminals 23 on the back surface 36 side of the semiconductor device 50 that are in contact with the printed circuit board 39 can be arranged in accordance with the positions of the electrodes 40 on the printed circuit board 39.
[0078]
FIG. 10 shows still another mounting example, in which semiconductor devices 50 are arranged in parallel as shown in the figure, and wiring between adjacent semiconductor devices 50 is connected to wiring 20 led out to the back surface 36 side. May be connected. In this case as well, the external terminals on the back surface 36 connected to the printed circuit board 39 can be provided in accordance with the positions of the electrodes 40 on the printed circuit board 39, and the number of semiconductor devices arranged in parallel is not limited to this. The above can be arranged.
[0079]
According to the present embodiment, since at least the side surface 31 and the back surface 36 other than the front surface 35 of the chip 3 are covered with the resin 4, the chip 3 is protected at the time of handling after chipping, and handling is facilitated. Since the chip 3 can be cut into individual pieces by cutting at the position of the resin 4, the chip 3 is not damaged (crack, distortion, or the like) at the time of cutting.
[0080]
In this structure, since the external terminals of the chip 3 are formed on at least the rear surface 36 of the front surface 35 and the rear surface 36, at the time of mounting the chip 3 on the mounting board 39, at least via the external terminals 23 of the rear surface 36. Connection is possible, and the external terminal 23 can be provided at an arbitrary position on the back surface 36, so that the degree of freedom of design is large. Of the chip 3 on the electrode surface side can be reduced.
[0081]
In this case, since the side surface 31 and the back surface 36 are covered with the resin 4, the electrode 5 on the front surface 35 is connected to the outside of the back surface 36 through the side surface or inside of the resin 4 while insulating and separating the chip 3 with the resin 4. The wiring 20 for leading to the terminal 23 can be formed, and the wiring 20 can be protected by the resin 4.
[0082]
Further, by providing the external terminals 16 and 23 on both surfaces of the front surface 35 and the rear surface 36, it is possible to laminate the plurality of chips 3 and connect the external terminals 16 and 23, and to connect the adjacent terminals at the pseudo wafer stage. Since connection between them is also possible, it is easy to manufacture not only a laminated structure but also an MCM having a flat structure. As described above, since the chip 3 having the external terminals 16 and 23 on both the front and back surfaces is collectively manufactured at the time of manufacturing the pseudo wafer, the semiconductor device 50 having more excellent connectivity while maintaining the excellent features of the prior application is reduced. It can be manufactured at cost. The structure in which the external terminals are provided on the back surface is also applicable to Patent Documents 1 and 2 as well as Patent Document 3 described above.
[0083]
Embodiment 2
FIG. 11 shows a process for fabricating a semiconductor device according to the present embodiment, in which a W-shaped groove 18 is formed by nesting, unlike the dicer of the first embodiment.
[0084]
FIG. 11A shows a state in which an adhesive sheet 2 whose adhesive strength is reduced by ultraviolet irradiation is attached to a quartz substrate 1 by the same process as the above-described prior application according to FIG. 25, and FIG. b) shows a state in which the surfaces (electrode surfaces) of the plurality of non-defective bare chips 3 are attached to the adhesive sheet 2 with the surfaces facing downward.
[0085]
Next, as shown in FIG. 11C, a nest 30 having a W-shaped cross section is arranged between the chips and attached to the adhesive sheet 2. In this case, it is important that the relationship between the height D of the nest 30 and the thickness T of the chip 3 satisfies D> T, and it is desirable that the protrusion of the nest 30 has an obtuse angle of more than 45 degrees.
[0086]
Next, as shown in FIG. 11D, an organic insulating resin, for example, an epoxy resin 4 is uniformly applied on the chip 3 by spin coating or printing.
[0087]
Next, as shown in FIG. 11 (e), ultraviolet rays L are irradiated from the back side of the quartz substrate 1 to weaken the adhesive force of the adhesive sheet 2, and a plurality of chips 3 whose side and back surfaces are fixed with resin 4 are removed. The arranged pseudo wafer 29 is separated from the quartz substrate 1.
[0088]
Through the above-described process, a pseudo wafer 29 as shown in FIG. 11 (f) (the pseudo wafer in FIG. 11 (e) is turned over) can be obtained. A pseudo wafer 29 having the same shape as that of (f) can be formed.
[0089]
Therefore, the semiconductor device having the same shape and function as the first embodiment can be obtained by performing the same processes as the first embodiment thereafter.
[0090]
According to the present embodiment, although a W-shaped groove similar to that of the first embodiment is formed, only the forming method is different, and the other manufacturing processes are performed in the same manner, and a completely similar semiconductor device is formed. Therefore, it is possible to obtain a semiconductor device having the same functions as the first embodiment and exhibiting the same effects.
[0091]
Embodiment 3
FIG. 13 shows a semiconductor device (corresponding to FIG. 1) 50A according to the present embodiment. This semiconductor device 50A is different from the semiconductor device 50 of the first embodiment (see FIG. 1) only in that the wiring 20 derived from the electrode 5 of the chip 3 is inclined toward the back surface 36 on the side surface of the chip 3. The other end is connected to the wiring 22 provided on the back surface 36, and the other configuration is the same as that of the first embodiment. This manufacturing process will be described with reference to FIG.
[0092]
FIG. 14A is a view corresponding to FIG. 3F of the first embodiment and FIG. 12F of the second embodiment, and as shown in FIG. Unlike the W-shaped groove, the groove has a trapezoidal shape. Also in this case, the relationship between the depth D of the groove 18 and the thickness T of the chip 3 is D> T. The groove 18 may be formed by cutting, for example, or may be formed by using a nest as in the second embodiment. And since the shape of the groove is trapezoidal, the spacing between adjacent chips can be made smaller than in the case of a W-shape, and efficient chip arrangement is possible. Subsequent processes are performed in the same manner as in the first embodiment.
[0093]
That is, as shown in FIG. 14B (enlarged view of FIG. 14A), the interlayer film 9 is formed in a predetermined pattern so as to open the electrode 5 of the chip 3. As a material of the interlayer film 9, a photosensitive insulating resin or the like is used, and a liquid material may be spin-coated and applied, or a dry fill may be attached with a laminator.
[0094]
Next, as shown in FIG. 14C, the wiring 20 is led out from the electrode 5 of the chip 3 and arranged in the groove 18, and the wiring 20 and the wiring 20 led out from the electrode 5 of the adjacent chip 3 18 so as to be continuous. Of course, this wiring is also formed by the semi-additive method as in FIGS. 4 (h) to 5 (m) described above, but is simply illustrated here.
[0095]
Next, as shown in FIG. 14D, a protective film 21 is formed on the entire upper surface including the wiring 20. As this material, a photosensitive insulating resin or the like is used similarly to the interlayer film 9. In this case, when the flatness between the groove 18 and the other parts cannot be obtained, the groove 18 is first applied by a dispense method or a printing method, as shown in FIG. The whole may be applied.
[0096]
Next, as shown in FIG. 14E, the resin 4 on the rear surface 36 is ground to expose the wiring 20 on the bottom surface of the groove 18. This grinding is performed by a grinder for grinding the back surface of the Si wafer.
[0097]
Next, as shown in FIG. 14F, the wiring 22 on the back surface 36 is formed by connecting to the exposed portion 20a of the wiring 20 exposed on the back surface. This wiring is also performed by the semi-additive method as described above.
[0098]
Next, as shown in FIG. 14G, after forming the protective film 25 on the back surface 36 with the same material as the above-mentioned interlayer film 9, a connection hole 27 with the wiring 20 derived from the electrode 5 is formed in the protective film 21. By forming, the external terminal 16 on the surface 35 side is formed. Further, by forming a connection hole 24 with the wiring 22 provided on the back surface 36 side in the protective film 25, the external terminal 23 on this surface is formed. Such a process can be collectively performed on the pseudo wafer 29.
[0099]
Thereafter, by cutting at the position of the cutting line 37, as shown in FIG. 13, a semiconductor device 50A having the same function as that of the first embodiment and having the external terminals 16 and 23 on both surfaces can be obtained. The semiconductor device 50A has a degree of freedom in designing the arrangement positions of the external terminals, as in the first embodiment, and is mounted on a printed circuit board in one chip as shown in FIG. It can also be mounted in a laminated structure, or as a flat structure as shown in FIG.
[0100]
According to the present embodiment, although the shape of the groove 18 is different from that of the first embodiment, it is possible to obtain a semiconductor device 50A having the same function as the first embodiment and exhibiting the same effect, and Since the distance between the chips 3 can be reduced, the production efficiency can be increased by increasing the arrangement of the chips 3 with respect to the same pseudo wafer 29.
[0101]
Embodiment 4
FIG. 15 shows a semiconductor device (corresponding to FIG. 1) 50B according to the present embodiment. The semiconductor device 50B is different from the semiconductor device of each of the above-described embodiments in that a method for leading a wiring to the back surface 36 side in the resin 4 on the side surface of the chip 3 is through a through-hole vertical through hole. In other respects, the configuration is the same as that of each of the above-described embodiments. However, similarly to the above-described third embodiment, the interval between the chips 3 can be reduced. This manufacturing process will be described with reference to FIG.
[0102]
FIG. 16A shows a state in which the interlayer film 9 is formed on the pseudo wafer 29 in the same state as the enlarged view of FIG.
[0103]
Next, as shown in FIG. 16B, in the resin 4 on the side surface of the chip 3, a blind hole 32 for leading out the wiring 20 to the back surface 36 side is intermittently formed for each chip 3 (FIG. 18). reference). The relationship between the depth D of the blind hole 32 and the thickness T of the chip 3 is D> T. The blind hole 32 can be formed by, for example, cutting with a laser or a drill.
[0104]
Next, as shown in FIG. 16C, the wiring 20 led out from the electrode of the chip 3 is guided to the back surface 36 side through the blind hole 32. This wiring is also formed through a semi-additive process (see FIGS. 4 (h) to 5 (n)). By providing a sufficient sputter film uniformly in the blind hole 32, the wiring for the wiring is formed. The blind holes 32 can be embedded by metal plating. Here, a detailed wiring process is not shown.
[0105]
Next, as shown in FIG. 16D, a protective film 21 is formed on the entire surface including the wiring 20 on the upper surface of the chip 3. As the material of the protective film 21, a photosensitive insulating resin is used similarly to the interlayer film 9, and is applied by a dispense method or a printing method.
[0106]
Next, as shown in FIG. 17E, the resin 4 on the rear surface 36 is ground to form an exposed portion 20a of the wiring 20 led to the blind hole 32. This grinding is performed by a grinder or the like for grinding the back surface of the Si wafer.
[0107]
Next, as shown in FIG. 17F, the wiring 22 on the back surface 36 is formed by connecting to the exposed portion 20a of the wiring 20 exposed on the back surface 36. This is also performed, for example, by the semi-additive method as described above.
[0108]
Next, as shown in FIG. 17G, after the protective film 25 on the back surface 36 is formed using the same material as the interlayer film 9, the wiring derived from the electrode 5 is formed on the protective film 21 on the front surface 35. The external terminal 16 on the front surface 35 side is formed by forming the connection hole 27 with. Further, by forming a connection hole 24 with the wiring 22 connected to the wiring 20 in the protective film 25, the external terminal 23 on the back surface 36 side is formed. The openings such as the external terminals 16 and 23 can be formed by photolithography on the protective films 21 and 25 made of a photosensitive insulating resin. Such a process can be performed at once in the manufacturing process of the pseudo wafer 29.
[0109]
Thereafter, by cutting at the position of the cutting line 37, as shown in FIG. 15, a semiconductor device 50B having the same function as that of the first embodiment and having the external terminals 16 and 23 on both surfaces can be obtained. The semiconductor device 50B has a degree of freedom in designing the positions of the external terminals, as in the first embodiment, and is mounted on a printed circuit board as a single chip as shown in FIG. 8 and a laminated structure as shown in FIG. , And can be mounted in a flat structure as shown in FIG.
[0110]
FIG. 18 is a schematic diagram showing a main part in a plan view (only wiring is shown by solid lines). The feature of this embodiment is that it is formed along the outer surface of the chip 3 in the first to third embodiments. Unlike linear grooves. That is, the wiring 20 is guided to the back surface 36 via the blind holes 32 (indicated by broken lines) formed intermittently. Therefore, the strength of the resin 4 on the side surface of the chip 3 can be maintained, and by maintaining the strength in this manner, there is an advantage such as a modified example (see FIG. 19) described later.
[0111]
FIG. 19A is a schematic diagram showing a modification of the fourth embodiment, and shows a state similar to FIG. 16B.
[0112]
FIG. 19B shows a grinding step for the back surface 36 side. That is, as described above, since the blind holes 32 are formed intermittently, the strength of the resin 4 between the chips can be maintained, so that the back surface 36 can be ground.
[0113]
Therefore, next, as shown in FIG. 19C, the wiring 20 on the front surface 35 and the wiring 22 on the rear surface 36 are formed in the same plating step by using the semi-additive method in the same manner as the above-described respective wirings. can do. Since the blind hole 32 is formed into a through-hole as shown in FIG. 19B by the above-described grinding, the simultaneous plating on both sides facilitates the filling of the through-hole by plating.
[0114]
Next, similarly to the fourth embodiment, through a required process, a state as shown in FIG. 19D can be formed. Accordingly, the manufacturing process is simplified, and the semiconductor device 50B having the same structure and function as in the fourth embodiment can be collectively manufactured at the pseudo wafer stage.
[0115]
According to this embodiment, the method of guiding the wiring 20 derived from the electrode 5 of the chip 3 to the back surface 36 is different from the other embodiments, but has the same function as the other embodiments, and In addition to being able to exhibit the effect, the interval between adjacent chips 3 is reduced, and the production efficiency can be improved by increasing the arrangement of the chips 3, and the strength of the resin 4 between the chips is maintained, so that simultaneous plating on the front and back surfaces can be performed. And the productivity can be further improved by simplifying the manufacturing process.
[0116]
FIG. 20 is a diagram showing a modified example common to each of the above-described embodiments. The description will be made with reference to the structure of the third embodiment.
[0117]
That is, FIG. 20A is a state similar to the state before grinding the back surface (FIG. 14D) in the third embodiment, but the difference between this example and the other is that each embodiment described above is different. That is, a chip 3A thicker than the thickness of the chip 3 is arranged on the pseudo wafer 29. The depth D of the groove 18 is the same as that of the third embodiment, but the thickness T of the chip 3A is1Is greater than the depth D of the groove 18 and D <T1It has become.
[0118]
As shown in FIG. 20B, the back surface 36 of the pseudo wafer 29 in the state of FIG. 20A is ground until most of the chips 3A are removed, thereby forming an exposed portion 20a on the bottom surface of the wiring 20. I do. By this grinding, the thickness of the chip 3A may be smaller than the thickness of the chip 3 in each of the above-described embodiments, but does not affect the semiconductor elements formed on the Si wafer. This allows a thinner semiconductor device to be formed, and is particularly suitable for an MCM having a laminated structure.
[0119]
Next, as shown in FIG. 20C, after the back surface of the ground chip 3A is covered with the interlayer insulating film 14, the same process as in the third embodiment is performed. That is, the wiring 22 on the back surface 36 is connected to the exposed portion 20a of the wiring 20 exposed on the back surface side, and after forming the protective film 25 on the back surface 36, as shown in FIG. The external terminal 16 on the front surface 35 side is formed by forming the connection hole 27 of the above, and the external terminal 23 is formed on the protective film 25 by forming the connection hole 24 with the wiring 22 on the rear surface 36. As a result, semiconductor devices having external terminals 16 and 23 on both surfaces can be collectively formed at the pseudo wafer stage.
[0120]
FIG. 21 is a diagram showing another modification, which is also common to the other embodiments except the fourth embodiment. This example will also be described with reference to a diagram in which a chip 3A similar to that of the above-described modified example (FIG. 20) is arranged according to the structure of Embodiment 3. Not only in the above-described modified example (FIG. 20), even if the wiring 20 in the groove 18 is locally disconnected due to excessive grinding of the back surface 36, the connection of the disconnected portion can be maintained by the method of this example. .
[0121]
That is, as shown in FIG. 21A, after forming the wiring 20 led out in the groove 18, a conductive material such as a paste 47 is locally disposed on the wiring 20 at the bottom of the groove 18. Then, a protective film 21 is formed thereon as shown in FIG.
[0122]
Thereafter, as in the modification shown in FIG. 20, the back surface 36 is partially removed by grinding. However, as shown in FIG. 21C, the wiring 20 to be exposed due to excessive grinding is disconnected, and Even if the portion 20a is divided, if the local disconnection is such that the strength of the entire pseudo wafer 29 can be maintained, the connection of the disconnected portion can be maintained by the paste 47 without breaking the pseudo wafer 29.
[0123]
Therefore, as shown in FIG. 21D, after the back surface of the chip 3A exposed by the grinding is covered with the interlayer insulating film 14, the same process as in FIG. 20 described above is performed, and as shown in FIG. The semiconductor device having the external terminals 16 and 23 can be collectively formed at the pseudo wafer stage.
[0124]
FIG. 22 is a diagram showing another modification, which is also common to the other embodiments except the fourth embodiment. This example will also be described with reference to a diagram in which a chip 3A similar to the above-described modified example is arranged according to the structure of the third embodiment. However, this example is similar to the above-described modified example (FIG. 21) in that a paste is previously prepared for disconnection. This is a processing method to be performed when a wire is broken due to excessive grinding instead of disposing.
[0125]
That is, by grinding and removing the back surface 36 side from the state of FIG. 22 (a), as shown in FIG. 22 (b), when the disconnection portion 20b occurs in the wiring at the bottom of the groove 18 due to excessive grinding. As shown in FIG. 22C, a hole 34 is made in the disconnection portion 20b by, for example, a drill. The hole 34 exposes the cross-sectional area of the wiring 20 as large as possible on the inner wall surface of the hole 34, and it is better that it is shallow. After forming the holes 34, the back surface of the chip 3A exposed by the grinding is covered with the interlayer insulating film 14. FIG. 23 is a bottom view (a hole is exaggerated) showing a state where a hole 34 is formed.
[0126]
Next, as shown in FIG. 22D, by forming the wiring 22 on the back surface 36 by a semi-additive method, the holes 34 formed in the disconnection portions 20b are simultaneously filled with the sputtered film and the plating film. Wiring 20 is connected.
[0127]
Next, through a predetermined process, a semiconductor device having external terminals 16 and 23 on both sides is formed as shown in FIG. 22E, and a series of processes including the above-described processes are collectively performed at a pseudo wafer stage. You can do it.
[0128]
Further, in the semiconductor device of each of the above-described embodiments and modifications, the external terminals may be provided only on the back surface as shown in FIG. This example will be described with the structure of the first embodiment (see FIG. 1).
[0129]
As shown in the figure, in the semiconductor device 50c, external terminals derived from the electrodes 5 of the chip 3 are not provided on the front surface 35 side, but are provided only on the rear surface 36 side. Accordingly, the external terminals 23 are formed by the same manufacturing process as that of FIG.
[0130]
In FIG. 24, the external terminals 23 are also in exactly the same position as in FIG. 1, but they can be arranged at any position, for example, matching the positions of the external terminals on the mounting board, so that the degree of freedom of design is large, and The external terminals can be arranged at positions where thermal stress at the time can be reduced and the influence on the chip can be minimized, and can be mounted face-up on a printed circuit board.
[0131]
The above embodiments can be variously modified based on the technical idea of the present invention.
[0132]
For example, the method of guiding the wiring 20 derived from the electrode 5 on the front surface 35 of the chip 3 to the back surface 36 side is as follows: the W-shaped groove of the first embodiment, the trapezoidal groove of the third embodiment, and the blind hole of the fourth embodiment. The method is not limited to this, and any other appropriate method may be used. The method of forming these grooves 18 may be a method other than dicing and nesting.
[0133]
The method of forming the wirings 20 and 22 is not limited to plating, and may be formed by physical vapor deposition or screen printing. Further, the connection between the external terminals of the laminated structure and the connection of the external terminals at the time of mounting on a printed circuit board are not limited to the solder bumps, and an ACF (anisotropic conductive film) may be used.
[0134]
Forming the external terminals of the chip 3 on at least the back surface of the front and back surfaces of the chip can be applied to chip components other than the semiconductor chip, such as light emitting diodes or photodiodes.
[0135]
Operation and Effect of the Invention
As described above, according to the present invention, since a plurality of chip components are formed through a pseudo wafer process in which at least the side surfaces other than the electrode surfaces and the other surface are covered with a protective substance, handling after chip formation Sometimes chip components are protected, handling becomes easier, and the chip components can be damaged (cracks, distortions, etc.) during cutting because they can be cut into individual chip components by cutting at the position of the protective substance. There is no.
[0136]
At the time of mounting this chip component on a mounting board, connection can be made via at least external terminals on the other surface, and external terminals can be provided at arbitrary positions on the other surface. Since the degree of heat is large and mounting is possible via the external terminals, the influence of thermal stress during mounting on one surface side (electrode surface side) of the chip component can be reduced.
[0137]
In this case, it is possible to form wiring for leading the electrode on one surface to the external terminal on the other surface through the side surface or the inside of the protection material while insulating and separating the chip component by the protective material, In addition, the wiring can be protected by a protective substance.
[0138]
Then, even if the chip device is singulated and the multi-chip module having a stacked structure of a plurality of chip components or a parallel arrangement is used, the connection between the plurality of chip components is made external to these chip components. It can be done through terminals.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view illustrating a stacked example of the semiconductor device.
FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIGS. 7A and 7B show a main part of the semiconductor device, wherein FIG. 7A is a schematic sectional view and FIG. 7B is a schematic bottom view.
FIG. 8 is a schematic sectional view showing a mounting example of the semiconductor device.
FIG. 9 is a schematic cross-sectional view showing a mounting example of the semiconductor device.
FIG. 10 is a schematic cross-sectional view showing a mounting example of the semiconductor device.
FIG. 11 is a schematic sectional view showing a manufacturing process of the semiconductor device according to Embodiment 2 of the present invention;
FIG. 12 is a schematic sectional view showing a modification of the first and second embodiments.
FIG. 13 is a schematic sectional view showing a semiconductor device according to a third embodiment of the present invention.
FIG. 14 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 15 is a schematic sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 16 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 17 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 18 is a schematic plan view showing a main part of the semiconductor device.
FIG. 19 is a schematic cross-sectional view showing a manufacturing process of a modification of the fourth embodiment.
FIG. 20 is a schematic cross-sectional view showing a manufacturing process of the modification shown in the structure of the third embodiment.
FIG. 21 is a schematic sectional view showing a manufacturing process of another modified example shown in the structure of Embodiment 3;
FIG. 22 is a schematic cross-sectional view showing a manufacturing process of still another modification shown in the structure of Embodiment 3;
FIG. 23 is a schematic bottom view showing a main part in the state of FIG. 22 (c).
FIG. 24 is a schematic cross-sectional view of a modification shown in the structure of the first embodiment.
FIG. 25 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional example.
FIG. 26 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 27 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
FIG. 28 is a schematic sectional view showing a mounting example of the semiconductor device.
FIG. 29 is a schematic cross-sectional view showing a mounting example of the semiconductor device.
[Explanation of symbols]
1: Quartz substrate, 2: Adhesive sheet, 3, 3A: Good bare chip (semiconductor chip),
4 ... Resin, 4a ... Protective film, 5 ... Electrode, 24, 27 ... Connection hole, 7 ... SiO2film,
8 passivation film, 9, 14 interlayer insulating film, 10 sputtered film,
11: resist mask, 11A: photoresist film, 12A: plating film,
20, 22 ... wiring, 21, 25, 38 ... protective film, 16, 23 ... external terminal,
18 groove, 20a exposed part, 20b disconnected part, 29 pseudo wafer,
30 ... nesting, 31 ... outer surface, 32, 34 ... hole, 33 ... solder bump,
35 ... front surface, 36 ... back surface, 37 ... cutting line, 39 ... printed circuit board, 40 ... electrode,
42 ... mask, 43a, 43b ... opening, 45 ... exposure light, 47 ... paste,
50: semiconductor device, L: ultraviolet ray, T: thickness of semiconductor chip, D: depth of groove

Claims (20)

一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われているチップ部品を有する半導体装置において、前記チップ部品の前記電極の外部端子が、前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成されていることを特徴とする、半導体装置。In a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface and the other surface are covered with a protective substance, an external terminal of the electrode of the chip component is the one terminal. A semiconductor device, which is formed on at least the other surface of the surface and the other surface on the opposite side. 前記側面の保護物質の外側面に、前記一方の面の外部端子と、他方の面の外部端子とを接続するための導電体が形成されている、請求項１に記載した半導体装置。The semiconductor device according to claim 1, wherein a conductor for connecting the external terminal on the one surface and the external terminal on the other surface is formed on an outer surface of the protective material on the side surface. 前記導電体が、前記保護物質の傾斜外側面又は垂直貫通孔に形成されている、請求項２に記載した半導体装置。The semiconductor device according to claim 2, wherein the conductor is formed on an inclined outer surface or a vertical through hole of the protective material. 前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、これとは異なる絶縁物質が前記外側面の前記導電体上に設けられている、請求項２に記載した半導体装置。3. The semiconductor device according to claim 2, wherein an insulating material different from the insulating protective film for forming the external terminal on the one surface is provided on the conductor on the outer surface. 前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、導電性物質が前記外側面の前記導電体上に接して設けられている、請求項２に記載した半導体装置。3. The semiconductor device according to claim 2, wherein a conductive material is provided in contact with the conductor on the outer surface under the insulating protective film for forming the external terminal on the one surface. 4. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質
によって一体化されてなる疑似ウェーハを作製する工程と、
前記疑似ウェーハにおける前記チップ部品の前記電極の外部端子を前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成する工程と、
前記複数個のチップ部品間で少なくとも前記保護物質を切断する工程と
を有することを特徴とする、半導体装置の製造方法。A step of producing a pseudo wafer in which a plurality of chip components provided with electrodes on one surface side and at least the side surfaces other than the electrode surfaces and the other surface covered with a protective substance are integrated by the protective substance; When,
Forming external terminals of the electrodes of the chip components in the pseudo wafer on at least the other surface of the one surface and the other surface opposite to the one surface,
Cutting at least the protective material between the plurality of chip components. 前記複数個のチップ部品間において、前記側面の保護物質に凹部を形成し、この面上に前記一方の面の外部端子と他方の面の外部端子とを接続するための導電体を形成した後、前記他方の面側から少なくとも前記保護物質を部分的に除去してこの除去面に前記導電体を露出させ、この露出した導電体に接続した前記他方の面の前記外部端子を形成する、請求項６に記載した半導体装置の製造方法。A recess is formed in the protective material on the side surface between the plurality of chip components, and a conductor for connecting the external terminal on one surface and the external terminal on the other surface is formed on this surface. At least partially removing the protective material from the other surface side to expose the conductor on the removed surface, and forming the external terminal on the other surface connected to the exposed conductor. Item 7. A method for manufacturing a semiconductor device according to Item 6. 前記凹部を前記チップ部品の厚みよりも深く形成する、請求項７に記載した半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 7, wherein the recess is formed deeper than a thickness of the chip component. 前記保護物質の部分的除去によって、傾斜面又は垂直面を呈した前記凹部の面上に前記導電体を残す、請求項７に記載した半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 7, wherein the conductor is left on a surface of the concave portion having an inclined surface or a vertical surface by partially removing the protective material. 前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、これとは異なる絶縁物質を前記外側面の前記導電体上に設ける、請求項７に記載した半導体装置の製造方法。8. The method according to claim 7, wherein a different insulating material is provided on the conductor on the outer surface under the insulating protective film for forming the external terminal on the one surface. 前記一方の面に前記外部端子を形成するための絶縁性保護膜下において、導電性物質を前記外側面の前記導電体上に接して設ける、請求項７に記載した半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 7, wherein a conductive substance is provided in contact with the outer surface of the conductor under the insulating protective film for forming the external terminal on the one surface. 特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製する、請求項６に記載した半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 6, wherein the pseudo wafer having the chip component determined to be non-defective by characteristic measurement is manufactured. 前記疑似ウェーハの状態において前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項６に記載した半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 6, wherein the characteristic of the chip component is measured in the state of the pseudo wafer, and a good chip component or a chip-shaped electronic component is selected. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質によって一体化されてなる疑似ウェーハであって、前記チップ部品の前記電極の外部端子が前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成されている、疑似ウェーハ。An electrode is provided on one surface side, a plurality of chip components at least side surfaces other than this electrode surface and the other surface are covered with a protective material, a pseudo wafer integrated with the protective material, A pseudo wafer, wherein external terminals of the electrodes of the chip component are formed on at least the other surface of the one surface and the other surface opposite to the one surface. 請求項２〜５のいずれか１項に記載した半導体装置を製造するのに用いられる、請求項１４に記載した疑似ウェーハ。The pseudo wafer according to claim 14, which is used for manufacturing the semiconductor device according to any one of claims 2 to 5. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面及び他方の面が保護物質で覆われたチップ部品の複数個が、前記保護物質によって一体化されてなる疑似ウェーハの製造方法において、前記疑似ウェーハにおける前記チップ部品の前記電極の外部端子を前記一方の面とこれとは反対側の他方の面とのうち少なくとも前記他方の面に形成する工程を有することを特徴とする、疑似ウェーハの製造方法。An electrode is provided on one surface side, and a plurality of chip components in which at least a side surface other than the electrode surface and the other surface are covered with a protective material, a method of manufacturing a pseudo wafer integrated with the protective material. Forming the external terminals of the electrodes of the chip components in the pseudo wafer on at least the other surface of the one surface and the other surface opposite to the one surface. Wafer manufacturing method. 請求項７〜１３のいずれか１項に記載した半導体装置の製造方法を適用する、請求項１６に記載した疑似ウェーハの製造方法。A method for manufacturing a pseudo wafer according to claim 16, wherein the method for manufacturing a semiconductor device according to any one of claims 7 to 13 is applied. 請求項１〜５のいずれか１項に記載した半導体装置によって構成され、この半導体装置が有する複数の前記チップ部品間が前記外部端子を介して互いに接続されている、マルチチップモジュール。A multi-chip module configured by the semiconductor device according to claim 1, wherein the plurality of chip components included in the semiconductor device are connected to each other via the external terminal. 前記複数のチップ部品を接続するための前記外部端子が、一方のチップ部品の前記一方の面側と、他方のチップ部品の前記他方の面側にそれぞれ形成されている、請求項１８に記載したマルチチップモジュール。19. The external terminal according to claim 18, wherein the external terminals for connecting the plurality of chip components are formed on the one surface side of one chip component and the other surface side of the other chip component, respectively. Multi-chip module. 前記複数のチップ部品を接続するための前記外部端子が、前記一方の面側又は前記他方の面側に形成されている、請求項１８に記載したマルチチップモジュール。19. The multi-chip module according to claim 18, wherein the external terminals for connecting the plurality of chip components are formed on the one surface side or the other surface side.
JP2003138136A 2003-05-16 2003-05-16 Semiconductor device and its manufacturing method, false wafer and its manufacturing method, and multi-chip module Pending JP2004342862A (en)

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Cited By (9)

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JP2010199129A (en) * 2009-02-23 2010-09-09 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same, and electronic apparatus
US7923291B2 (en) 2008-07-28 2011-04-12 Samsung Electronics Co., Ltd. Method of fabricating electronic device having stacked chips
JP2011524647A (en) * 2008-06-16 2011-09-01 テセラ・リサーチ・リミテッド・ライアビリティ・カンパニー Edge stacking at wafer level
JP2012134231A (en) * 2010-12-20 2012-07-12 Disco Abrasive Syst Ltd Multilayer device manufacturing method and multi layer device
JP2012248583A (en) * 2011-05-25 2012-12-13 Jjtech Co Ltd Manufacturing method of semiconductor device, semiconductor device and manufacturing method of intermediate plate
TWI394272B (en) * 2010-05-17 2013-04-21
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
JP2011524647A (en) * 2008-06-16 2011-09-01 テセラ・リサーチ・リミテッド・ライアビリティ・カンパニー Edge stacking at wafer level
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US7923291B2 (en) 2008-07-28 2011-04-12 Samsung Electronics Co., Ltd. Method of fabricating electronic device having stacked chips
JP2010199129A (en) * 2009-02-23 2010-09-09 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same, and electronic apparatus
US8450853B2 (en) 2009-02-23 2013-05-28 Shinko Electric Industries Co., Ltd. Semiconductor device and a method of manufacturing the same, and an electronic device
TWI394272B (en) * 2010-05-17 2013-04-21
JP2012134231A (en) * 2010-12-20 2012-07-12 Disco Abrasive Syst Ltd Multilayer device manufacturing method and multi layer device
JP2012248583A (en) * 2011-05-25 2012-12-13 Jjtech Co Ltd Manufacturing method of semiconductor device, semiconductor device and manufacturing method of intermediate plate

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