JP2006339189A - Semiconductor wafer and semiconductor device using the same - Google Patents

Semiconductor wafer and semiconductor device using the same Download PDF

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JP2006339189A
JP2006339189A JP2005158497A JP2005158497A JP2006339189A JP 2006339189 A JP2006339189 A JP 2006339189A JP 2005158497 A JP2005158497 A JP 2005158497A JP 2005158497 A JP2005158497 A JP 2005158497A JP 2006339189 A JP2006339189 A JP 2006339189A
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protective film
semiconductor wafer
seal ring
protective layer
wiring
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Takuji Osumi
卓史 大角
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2005158497A priority Critical patent/JP2006339189A/en
Priority to KR1020060027050A priority patent/KR20060124555A/en
Priority to US11/441,196 priority patent/US7915746B2/en
Priority to CNB2006100835143A priority patent/CN100530631C/en
Publication of JP2006339189A publication Critical patent/JP2006339189A/en
Priority to US12/887,798 priority patent/US8164164B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133606—Direct backlight including a specially adapted diffusing, scattering or light controlling members
    • G02F1/133607—Direct backlight including a specially adapted diffusing, scattering or light controlling members the light controlling member including light directing or refracting elements, e.g. prisms or lenses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/04—Materials and properties dye
    • G02F2202/046—Materials and properties dye fluorescent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means to prevent a resist film from being broken during the formation of rewiring even if the aspect ratio of a groove formed in the preventive layer of a semiconductor wafer is more than 0.5. <P>SOLUTION: The semiconductor wafer is provided with a plurality of active areas wherein an integrated circuit is formed, a dicing area provided among the adjoining active areas, a seal ring formed around the edge of the active area, wiring formed close to the inside of the seal ring, a preventive layer covering the active areas, a preventive film formed on the preventive layer on the active areas, and rewiring which is formed on the preventive film and is electrically connected with an interagted circuit. In case when the aspect ratio of a groove formed between the seal ring and the wiring is more than 0.5, the groove is covered with the preventive film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ウェハレベルチップサイズパッケージ型の半導体装置やバンプ電極を有するＩＣチップ等の製造に用いる半導体ウェハおよびそれにより形成した半導体装置に関する。   The present invention relates to a wafer level chip size package type semiconductor device, a semiconductor wafer used for manufacturing an IC chip having bump electrodes, and a semiconductor device formed thereby.

従来のウェハレベルチップサイズパッケージ型の半導体装置やバンプ電極を有するＩＣチップの製造に用いる半導体ウェハは、シリコン基板上に設定された複数の素子領域に集積回路を形成し、隣合う素子領域の間に設定されたダイシング領域にパターン形成精度測定用マークや電気特性評価用素子を形成し、素子領域を覆う保護層を形成するときにダイシング領域のパターン形成精度測定用マーク等を部分的に保護層で覆い、パターン形成精度測定用マーク等に形成された微細な隙間に巻き込まれる空気等による保護層上に再配線を形成する際のレジスト膜の破壊を防止すると共に、パターン形成精度測定用マーク等を覆う保護層と素子領域を覆う保護層との間に設けた所定間隔の未形成領域によりダイシング領域をダイシングソーで切断するときに素子領域上の保護層に生じるクラックを防止している（例えば、特許文献１参照。）。   Conventional wafer level chip size package type semiconductor devices and semiconductor wafers used in the manufacture of IC chips having bump electrodes form an integrated circuit in a plurality of element regions set on a silicon substrate, and between adjacent element regions. When forming a pattern formation accuracy measurement mark or an element for evaluating electrical characteristics in a dicing area set to be set to a protective layer covering the element area, the pattern formation accuracy measurement mark in the dicing area is partially protected In addition to preventing damage to the resist film when rewiring is formed on the protective layer due to air or the like caught in a minute gap formed in the pattern formation accuracy measurement mark, etc., and the pattern formation accuracy measurement mark, etc. The dicing area is cut with a dicing saw by an unformed area at a predetermined interval provided between the protective layer covering the element and the protective layer covering the element area. Thereby preventing cracks occurring in the protective layer on the element region Rutoki (e.g., see Patent Document 1.).

このようなウェハレベルチップサイズパッケージ型の半導体装置等においては、近年の電子機器の小型化や販売拡大に伴って半導体装置の更なる小型化や増産に対する期待が高まってきている。
このような半導体装置の更なる小型化や増産の期待に答えるためには、半導体ウェハに形成する集積回路の高密度化による半導体装置の小型化やダイシング領域の狭小化による１枚の半導体ウェハにより製造する半導体装置の製造数の増加を実現することが必要になる。
特開平１１−１９１５４１号公報（第３頁段落０００７−第４頁段落００１３、第１図、第２図） In such a wafer level chip size package type semiconductor device and the like, the expectation for further miniaturization and increase of production of the semiconductor device is increasing with the recent miniaturization and sales expansion of electronic devices.
In order to respond to the expectation of further miniaturization and increased production of such a semiconductor device, it is possible to reduce the size of the semiconductor device by increasing the density of integrated circuits formed on the semiconductor wafer and to reduce the dicing area by using a single semiconductor wafer. It is necessary to realize an increase in the number of semiconductor devices to be manufactured.
JP-A-11-191541 (3rd page paragraph 0007-4th page paragraph 0013, FIGS. 1 and 2)

しかしながら、上述した従来の技術においては、ダイシング領域の保護層と素子領域を覆う保護層との間に設けた所定間隔の未形成領域によりダイシング領域をダイシングソーで切断するときに素子領域の保護層に生じるクラックを防止しているため、ダイシング領域を狭小化すると所定間隔を十分に広くすることができず、保護層の厚さである深さを所定間隔である幅で除したアスペクト比が０．５以上となる溝、つまり深さが幅の半分以上になる溝となった場合には、その後に再配線を形成する際のレジスト膜のプリベーク時に溝に巻込まれた空気が膨張してレジスト膜に破壊が生じ、予期せぬ部位に不定形でメッキが析出し、外観不良が生じる他、再配線のメッキ厚にバラツキが生じるという問題がある。   However, in the above-described conventional technique, when the dicing area is cut with a dicing saw by a non-formed area at a predetermined interval provided between the protective layer in the dicing area and the protective layer covering the element area, the protective layer in the element area Therefore, when the dicing area is narrowed, the predetermined interval cannot be sufficiently widened, and the aspect ratio obtained by dividing the depth of the protective layer by the width of the predetermined interval is 0. If the groove becomes a groove having a depth of 5 or more, that is, a groove having a depth of more than half of the width, air entrained in the groove during the pre-baking of the resist film during subsequent rewiring is expanded and the resist is expanded. There is a problem that the film is broken, the plating is deposited in an undefined shape at an unexpected part, the appearance is deteriorated, and the plating thickness of the rewiring is varied.

また、半導体装置の小型化のために、電源配線等を統合した配線を能動領域上に形成する場合には、保護層に生じる集積回路へのクラックの進行を食い止めるために配線の外側の能動領域にシールリングを設ける場合がある。
この場合に、小型化を図るためにシールリングを配線に接近させると、シールリングと配線との間の保護層に溝が形成され、この溝のアスペクト比が０．５以上であるときには、前記と同様に再配線を形成する際のレジスト膜に破壊が生じ、予期せぬ部位に不定形でメッキが析出して外観不良や再配線のメッキ厚のバラツキが生じるという問題がある。 In addition, in order to reduce the size of the semiconductor device, when wiring integrated with power supply wiring or the like is formed on the active region, the active region outside the wiring is used to prevent the progress of cracks in the integrated circuit generated in the protective layer. There may be a case where a seal ring is provided.
In this case, when the seal ring is brought close to the wiring in order to reduce the size, a groove is formed in the protective layer between the seal ring and the wiring, and when the aspect ratio of the groove is 0.5 or more, In the same manner as the above, there is a problem that the resist film is broken when the rewiring is formed, and plating is deposited in an unexpected shape at an unpredictable portion, resulting in an appearance defect and a variation in rewiring plating thickness.

本発明は、上記の問題点を解決するためになされたもので、保護層に形成された溝のアスペクト比が０．５以上である場合においても、再配線を形成する際のレジスト膜に破壊が生じることを防止する手段を提供することを目的とする。   The present invention has been made to solve the above-described problems. Even when the aspect ratio of the groove formed in the protective layer is 0.5 or more, the resist film is broken when the rewiring is formed. An object of the present invention is to provide a means for preventing the occurrence of the above.

本発明は、上記課題を解決するために、半導体ウェハが、集積回路を形成した複数の能動領域と、隣合う前記能動領域間に設けられたダイシング領域と、前記能動領域の縁部に形成されたシールリングと、該シールリングの内側に接近して形成された第１の配線と、前記能動領域を覆う保護層と、前記能動領域の保護層上に形成された保護膜と、該保護膜上に形成され、前記集積回路に電気的に接続する第２の配線とを備え、前記シールリングと前記第１の配線との間の前記保護層に形成された溝のアスペクト比が０．５以上の場合に、該溝を前記保護膜で覆うことを特徴とする。   In order to solve the above problems, the present invention provides a semiconductor wafer formed on a plurality of active regions in which an integrated circuit is formed, a dicing region provided between the adjacent active regions, and an edge of the active region. A seal ring, a first wiring formed close to the inside of the seal ring, a protective layer covering the active region, a protective film formed on the protective layer of the active region, and the protective film And a second wiring electrically connected to the integrated circuit, and an aspect ratio of a groove formed in the protective layer between the seal ring and the first wiring is 0.5. In the above case, the groove is covered with the protective film.

これにより、本発明は、アスペクト比が０．５以上の溝を覆う保護膜により溝に残留した気体によるレジスト膜の破壊を防止することができ、予期せぬ部位に不定形でメッキが析出することがなくなり、外観不良や再配線のメッキ厚のバラツキの発生を防止することができるという効果が得られる。   As a result, the present invention can prevent the resist film from being destroyed by the gas remaining in the groove by the protective film covering the groove having an aspect ratio of 0.5 or more, and the plating deposits in an unexpected shape in an undefined shape. Thus, it is possible to prevent the appearance defect and the variation in the plating thickness of the rewiring.

以下に、図面を参照して本発明による半導体ウェハの実施例について説明する。   Embodiments of a semiconductor wafer according to the present invention will be described below with reference to the drawings.

図１は実施例１の半導体ウェハの部分断面を示す説明図、図２は実施例１の半導体ウェハの一部を示す上面から見た説明図である。
なお、図１は図２におけるＡ−Ａ断面線に沿った部分断面の再配線の形成後の状態を拡大して示し、図２は再配線の形成後にレジスト膜を除去した状態で示してある。
図１、図２において、１は半導体ウェハであり、本実施例ではウェハレベルチップサイズパッケージ型の半導体装置を製造するための半導体ウェハである。 FIG. 1 is an explanatory view showing a partial cross section of the semiconductor wafer of Example 1, and FIG. 2 is an explanatory view seen from the top showing a part of the semiconductor wafer of Example 1. FIG.
1 is an enlarged view of a state after the formation of the rewiring of the partial cross section along the line AA in FIG. 2, and FIG. 2 is a state where the resist film is removed after the rewiring is formed. .
1 and 2, reference numeral 1 denotes a semiconductor wafer, which in this embodiment is a semiconductor wafer for manufacturing a wafer level chip size package type semiconductor device.

２はシリコンからなる半導体基板であり、そのおもて面には図示しない集積回路の形成を可能にした領域である能動領域３が複数形成され、ウェハレベルチップサイズパッケージ型の半導体装置を製造するときにダイシングソー等により切断する領域として設定されたダイシング領域４が、隣合う能動領域３の間の隣合う保護層５の端部の端面の間として設定されている。   Reference numeral 2 denotes a semiconductor substrate made of silicon, and a plurality of active regions 3 which are regions capable of forming an unillustrated integrated circuit are formed on the front surface thereof, and a wafer level chip size package type semiconductor device is manufactured. A dicing region 4 that is sometimes set as a region to be cut by a dicing saw or the like is set between the end surfaces of the end portions of the adjacent protective layers 5 between the adjacent active regions 3.

保護層５は、窒化珪素（Ｓｉ３Ｎ４）や２酸化珪素（ＳｉＯ２）等で形成されたいわゆるパッシベーション膜であって、図１に複数のドットを付して示すように半導体基板２の能動領域３の上部および電極パッド６の周縁部に形成され、能動領域３の中央部付近（図１において右側）に形成された集積回路を保護および絶縁する機能を有している。
電極パッド６は、能動領域３上にアルミニウム（Ａｌ）等で形成されたパッドであって、能動領域３に形成された集積回路の所定の部位に電気的に接続されている。 The protective layer 5 is a so-called passivation film formed of silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), or the like. As shown in FIG. The integrated circuit formed in the upper part of the active region 3 and the peripheral part of the electrode pad 6 has a function of protecting and insulating an integrated circuit formed near the center of the active region 3 (right side in FIG. 1).
The electrode pad 6 is a pad formed of aluminum (Al) or the like on the active region 3 and is electrically connected to a predetermined portion of the integrated circuit formed in the active region 3.

７は保護膜であり、図１に網掛けで示すように保護層５上にポリイミド樹脂やエポキシ樹脂、ポリベンゾオキサゾール樹脂等の比較的強度の高い有機材料で形成され、保護層５上および保護層５にエッチング等により形成された穴の側面等の凹凸等の欠陥を覆って滑らかにする機能を有している。
８はシード層であり、図１に太い実線で示すように保護膜７上、保護層５上、電極パッド６上等に形成されたニッケル（Ｎｉ）やチタン（Ｔｉ）、銅（Ｃｕ）等の金属材料で単層または複層に形成された金属薄膜層であって、電解メッキ法による再配線９のメッキの際の一方の電極としての機能、半導体ウェハ１の製造工程で再配線９等の上層を構成する物質が半導体基板２側へ拡散することを防止する機能および再配線９との密着性を向上させる機能を有している。 Reference numeral 7 denotes a protective film, which is formed of a relatively high strength organic material such as polyimide resin, epoxy resin, polybenzoxazole resin, etc. on the protective layer 5 as shown by shading in FIG. The layer 5 has a function of covering and smoothing defects such as irregularities such as side surfaces of holes formed by etching or the like.
Reference numeral 8 denotes a seed layer. As shown by a thick solid line in FIG. 1, nickel (Ni), titanium (Ti), copper (Cu), etc. formed on the protective film 7, the protective layer 5, the electrode pad 6, etc. A metal thin film layer formed of a single metal layer or multiple layers of the above metal material, functioning as one electrode when the rewiring 9 is plated by the electrolytic plating method, the rewiring 9 in the manufacturing process of the semiconductor wafer 1, etc. It has a function of preventing the material constituting the upper layer from diffusing to the semiconductor substrate 2 side and a function of improving the adhesion to the rewiring 9.

第２の配線としての再配線９は、保護膜７上のシード層８に形成された銅等の導電性を有する材料で形成された配線であって、保護層５および保護膜７を貫通するスルーホール９ａにより電極パッド６と電気的に接続すると共に、再配線９上の所定の位置に形成された図示しないポストと電極パッド６とを電気的に接続する機能を有している。
１１はシールリングであり、能動領域３の周囲の縁部３ａの集積回路の素子が形成されていない領域の上にアルミニウム等で環状に形成された環状部材であって、ダイシング領域４をダイシングソー等により切断するときに保護層５の端部に生じるクラックの進行を食い止めてクラックが集積回路に及ぶことを防止する機能を有している。 The rewiring 9 as the second wiring is a wiring formed of a conductive material such as copper formed in the seed layer 8 on the protective film 7 and penetrates the protective layer 5 and the protective film 7. In addition to being electrically connected to the electrode pad 6 through the through hole 9a, the post pad (not shown) formed at a predetermined position on the rewiring 9 and the electrode pad 6 are electrically connected.
Reference numeral 11 denotes a seal ring, which is an annular member formed in an annular shape with aluminum or the like on a region where the integrated circuit element around the active region 3 is not formed. The dicing region 4 is a dicing saw. It has a function of preventing the crack from reaching the integrated circuit by stopping the progress of the crack generated at the end of the protective layer 5 when it is cut by, for example.

１２は第１の配線としての配線であり、集積回路の回路配線の合理化等のために電源配線等を統合して能動領域３上にアルミニウム等で環状に形成された配線であって、能動領域３に形成された集積回路の所定の部位に電気的に接続されている。
１４は溝であり、シールリング１１および配線１２を保護層５で覆ったときにシールリング１１と配線１２との間の保護層５に形成される溝である。 Reference numeral 12 denotes a wiring as a first wiring, which is a wiring formed in an annular shape with aluminum or the like on the active region 3 by integrating power source wiring and the like for rationalization of circuit wiring of the integrated circuit. 3 is electrically connected to a predetermined portion of the integrated circuit formed in the circuit 3.
A groove 14 is formed in the protective layer 5 between the seal ring 11 and the wiring 12 when the seal ring 11 and the wiring 12 are covered with the protective layer 5.

１６はレジスト膜であり、再配線９を形成する際にフォトリソグラフィにより比較的高い粘度を有するレジスト剤をパターニングして形成されるマスク部材であって、レジスト剤を半導体ウェハ１の全面に塗布してプリベークにより熱硬化させ後に、紫外線等の光による露光により露光した部分が変質して現像液に溶解する特性を有するポジ型の感光性を有している。   Reference numeral 16 denotes a resist film, which is a mask member formed by patterning a resist agent having a relatively high viscosity by photolithography when the rewiring 9 is formed. The resist agent is applied to the entire surface of the semiconductor wafer 1. Then, after having been thermally cured by pre-baking, it has a positive type photosensitivity having a characteristic that a portion exposed by exposure to light such as ultraviolet rays is denatured and dissolved in a developer.

図１および図２は、本実施例の説明のために誇張を加えて描いた説明図であるので実際の寸法と異なった状態で描いてあるが、実際の寸法は非常に小さいものであって、例えばシールリング１１や配線１２の高さは２μｍ程度、シールリング１１と配線１２の間隔は２μｍ程度、保護層５の厚さは１μｍ未満に形成されている。
このように、本実施例の溝１４は、保護層５の形成により幅が狭められて深さを幅で除したアスペクト比が０．５以上となり、レジスト膜１６の形成時に溝１４に空気等を巻込んでレジスト膜１６を破壊させる確率が高くなるので、この溝１４を覆うように保護膜７を形成する。 FIG. 1 and FIG. 2 are explanatory drawings drawn with exaggeration for the explanation of the present embodiment, so they are drawn in a state different from the actual dimensions, but the actual dimensions are very small. For example, the height of the seal ring 11 and the wiring 12 is about 2 μm, the distance between the seal ring 11 and the wiring 12 is about 2 μm, and the thickness of the protective layer 5 is less than 1 μm.
As described above, the groove 14 of this embodiment is narrowed by the formation of the protective layer 5 and the aspect ratio obtained by dividing the depth by the width is 0.5 or more. When the resist film 16 is formed, air or the like is formed in the groove 14. Since the probability of destroying the resist film 16 by entraining is increased, the protective film 7 is formed so as to cover the groove 14.

この場合に、保護膜７のエッジ７ａは、シールリング１１の幅方向の中央部に位置するようにし、シールリング１１の幅は保護膜７のエッジ７ａの製作精度の上下限の幅と同等にするとよい。例えばエッジ７ａの製作精度が±３μｍである場合に、シールリング１１の幅は製作精度の上下限の幅である６μｍに設定する。
このようにすれば、エッジ７ａがシールリング１１を超えてダイシング領域４側にずれることによるダイシング領域４の幅が狭くなることや能動領域３の端部にかかってエッジ７ａが品質よく形成できなくなること、およびエッジ７ａがシールリング１１の到らないことによる溝１４を被覆できなくなることを防止してエッジ７ａを常にシールリング１１の平坦な上面上に位置させて品質よく形成することができると共に、溝１４を確実に保護膜７で覆うことができるからである。 In this case, the edge 7a of the protective film 7 is positioned at the center of the seal ring 11 in the width direction, and the width of the seal ring 11 is equal to the upper and lower widths of the manufacturing accuracy of the edge 7a of the protective film 7. Good. For example, when the manufacturing accuracy of the edge 7a is ± 3 μm, the width of the seal ring 11 is set to 6 μm, which is the upper and lower width of the manufacturing accuracy.
In this manner, the width of the dicing region 4 is reduced due to the edge 7a being shifted to the dicing region 4 side beyond the seal ring 11, and the edge 7a cannot be formed with good quality over the end of the active region 3. In addition, the edge 7a can be prevented from becoming unable to cover the groove 14 due to the seal ring 11 not reaching, and the edge 7a can always be positioned on the flat upper surface of the seal ring 11 and formed with good quality. This is because the groove 14 can be reliably covered with the protective film 7.

また、本実施例の保護膜７は上記した有機材料で、１．５気圧以上の耐圧性を備えるように保護膜７の材料および膜厚を設定することが望ましい。
つまり、レジスト膜１６を形成するときのレジスト剤の塗布後における硬化のためのプリベーク時の熱処理温度は１００〜１５０℃であり、この熱処理温度により保護膜７の形成時に溝１４に閉じ込められた空気等の気体は等容変化により１．２７〜１．４４気圧に上昇し、これに耐えるためには１．５気圧以上の耐圧性を要するからである。 Further, the protective film 7 of this embodiment is the above-described organic material, and it is desirable to set the material and film thickness of the protective film 7 so as to have a pressure resistance of 1.5 atmospheres or more.
That is, the heat treatment temperature at the time of pre-baking for curing after applying the resist agent when forming the resist film 16 is 100 to 150 ° C., and the air trapped in the groove 14 when the protective film 7 is formed by this heat treatment temperature. This is because a gas such as gas rises to 1.27 to 1.44 atm due to a change in isovolume, and a pressure resistance of 1.5 atm or more is required to withstand this.

なお、本実施例では保護膜７を有機材料で形成するとして説明するが、保護膜７を形成する材料は窒化珪素や２酸化珪素等の無機材料であってもよい。要は保護膜７としての機能を備え、保護膜７の形成後に１．５気圧以上の耐圧性を有する膜を形成できる材料であればどのような材料であってもよい。
以下に、本実施例の半導体ウェハ１による半導体装置の製造方法について説明する。 In this embodiment, the protective film 7 is described as being formed of an organic material. However, the material for forming the protective film 7 may be an inorganic material such as silicon nitride or silicon dioxide. In short, any material may be used as long as it has a function as the protective film 7 and can form a film having a pressure resistance of 1.5 atm or more after the protective film 7 is formed.
Below, the manufacturing method of the semiconductor device by the semiconductor wafer 1 of a present Example is demonstrated.

円柱状のシリコンをスライスして形成された円形の半導体基板２の複数の能動領域３の中央部に図示しない集積回路を形成した半導体ウェハ１を準備し、半導体基板２のおもて面側の全面にスパッタリング法等によってアルミニウム膜を堆積し、これをシールリング１１、配線１２および電極パッド６の所定の形状にエッチングして能動領域３上にシールリング１１、配線１２および電極パッド６を形成する。   A semiconductor wafer 1 in which an integrated circuit (not shown) is formed at the center of a plurality of active regions 3 of a circular semiconductor substrate 2 formed by slicing columnar silicon is prepared, and the front surface side of the semiconductor substrate 2 is prepared. An aluminum film is deposited on the entire surface by sputtering or the like, and this is etched into a predetermined shape of the seal ring 11, the wiring 12 and the electrode pad 6 to form the seal ring 11, the wiring 12 and the electrode pad 6 on the active region 3. .

シールリング１１等の形成後に、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等によって２酸化珪素からなる保護層５を形成し、電極パッド６の部位およびダイシング領域４の保護層５をエッチングにより除去する。
このとき、シールリング１１と配線１２との間の保護層５に溝１４が形成される。
保護層５および電極パッド６上にスピンコート法等によりポリイミド樹脂からなる保護膜７を形成し、エッチングにより電極パッド６の部位を除去して電極パッド６に到るスルーホール９ａを形成すると共に、シールリング１１の幅方向の中央部よりダイシング領域４側の部位の保護膜７を除去して保護層５の端部を露出させ、溝１４を覆う保護膜７を形成する。 After the formation of the seal ring 11 and the like, the protective layer 5 made of silicon dioxide is formed by a CVD (Chemical Vapor Deposition) method or the like, and the portion of the electrode pad 6 and the protective layer 5 in the dicing region 4 are removed by etching.
At this time, a groove 14 is formed in the protective layer 5 between the seal ring 11 and the wiring 12.
A protective film 7 made of polyimide resin is formed on the protective layer 5 and the electrode pad 6 by spin coating or the like, and a portion of the electrode pad 6 is removed by etching to form a through hole 9a reaching the electrode pad 6, The protective film 7 at the site on the dicing region 4 side is removed from the center in the width direction of the seal ring 11 to expose the end of the protective layer 5, and the protective film 7 covering the groove 14 is formed.

半導体基板２のおもて面側の全面にスパッタリング法等によりシード層８を形成して露出している保護層５および保護膜７、電極パッド６をシード層８で覆う。
リソグラフィ等によりシード層８上にレジスト膜１６を形成して再配線９を形成する部位以外の領域をマスキングし、露出しているシード層８上にシード層８を一方の電極として銅を電解メッキ法により析出させ、電極パッド６に電気的に接続する再配線９を形成する。 A seed layer 8 is formed on the entire front surface of the semiconductor substrate 2 by sputtering or the like, and the exposed protective layer 5, protective film 7, and electrode pad 6 are covered with the seed layer 8.
A resist film 16 is formed on the seed layer 8 by lithography or the like to mask a region other than a portion where the rewiring 9 is formed, and copper is electroplated on the exposed seed layer 8 using the seed layer 8 as one electrode. A rewiring 9 that is deposited by the method and electrically connected to the electrode pad 6 is formed.

このとき、レジスト膜１６の形成のためのプリベークにおいて、温度が上昇したとしても保護膜７が十分な耐圧性を有しているので、保護膜７の形成時に溝１４に残留した気体があったとしてもその圧力上昇により保護膜７が破壊されることはなく、レジスト膜１６に破壊が生じることもない。
剥離剤を用いてレジスト膜１６を除去し、露出したシード層８を酸素ガス雰囲気中でのプラズマエッチング等により除去して保護層５の端部を露出させる。 At this time, in the pre-bake for forming the resist film 16, the protective film 7 has sufficient pressure resistance even if the temperature rises, so there was a gas remaining in the groove 14 when the protective film 7 was formed. However, the protective film 7 is not broken by the pressure rise, and the resist film 16 is not broken.
The resist film 16 is removed using a release agent, and the exposed seed layer 8 is removed by plasma etching or the like in an oxygen gas atmosphere to expose the end portion of the protective layer 5.

そして、半導体ウェハ１のダイシング領域４を保護層５の端部を検出する等して認識し、ダイシング領域４をダイシングソー等により切断して個片に分割し、本実施例の半導体ウェハ１により製造された半導体装置が形成される。
その後、本実施例の半導体装置は、再配線９の所定の部位にワイヤボンディングによりワイヤを接合した後にエポキシ樹脂等の封止樹脂で封止される。 Then, the dicing area 4 of the semiconductor wafer 1 is recognized by detecting the end of the protective layer 5, and the dicing area 4 is cut by a dicing saw or the like to be divided into individual pieces. A manufactured semiconductor device is formed.
Thereafter, the semiconductor device of this embodiment is sealed with a sealing resin such as an epoxy resin after a wire is bonded to a predetermined portion of the rewiring 9 by wire bonding.

なお、本実施例の半導体装置の形成は上記によらずに、再配線９を形成してレジスト膜１６を除去した後に、再度リソグラフィ等によりダイシング領域４の近傍に切断位置を示す識別マークや再配線９の所定の部位にポストを形成し、シード層８を除去して封止樹脂で半導体基板２のおもて面側を封止し、その後、識別マークに基づいて半導体ウェハ１のダイシング領域４をダイシングソー等により切断して個片に分割された半導体装置を形成するようにしてもよい。   The semiconductor device of this embodiment is not formed as described above. After forming the rewiring 9 and removing the resist film 16, the identification mark indicating the cutting position in the vicinity of the dicing region 4 or the like is again formed by lithography or the like. A post is formed at a predetermined portion of the wiring 9, the seed layer 8 is removed, the front surface side of the semiconductor substrate 2 is sealed with a sealing resin, and then the dicing region of the semiconductor wafer 1 is based on the identification mark. 4 may be cut by a dicing saw or the like to form a semiconductor device divided into pieces.

以上説明したように、本実施例では、半導体ウェハの能動領域に形成したシールリングと配線との間の保護層に形成される溝のアスペクト比が０．５以上の場合に、この溝を保護膜で覆うようにしたことによって、半導体ウェハを個片に分割するときに保護層に生じるクラックの進行を防止するためのシールリングと、集積回路の回路配線の合理化のための配線とを接近させて配置したとしても、これらの間に形成される溝を覆う保護膜により溝に残留した気体によるレジスト膜の破壊を防止することができ、予期せぬ部位に不定形でメッキが析出することがなくなり、外観不良や再配線のメッキ厚のバラツキの発生を防止することができる。   As described above, in this embodiment, this groove is protected when the aspect ratio of the groove formed in the protective layer between the seal ring and the wiring formed in the active region of the semiconductor wafer is 0.5 or more. By covering it with a film, the seal ring for preventing the progress of cracks that occur in the protective layer when the semiconductor wafer is divided into individual pieces and the wiring for rationalizing the circuit wiring of the integrated circuit are brought close to each other. The protective film covering the grooves formed between them can prevent the resist film from being damaged by the gas remaining in the grooves, and the plating can be deposited in an undefined shape at an unexpected part. Thus, it is possible to prevent appearance defects and variations in rewiring plating thickness.

また、保護膜のエッジをシールリングの幅方向の中央部に位置させるようにしたことによって、シールリングの平坦な上面上にエッジを位置させて品質の良好な保護膜を有する半導体ウェハを得ることができると共に、溝を保護膜で確実に覆うことができる。
更に、シールリングの幅を保護膜のエッジの製作精度の幅と同等にしたことによって、保護膜のエッジを常にシールリングの平坦な上面上に位置させることができる。 In addition, since the edge of the protective film is positioned at the center in the width direction of the seal ring, the semiconductor wafer having a good quality protective film can be obtained by positioning the edge on the flat upper surface of the seal ring. And the groove can be reliably covered with a protective film.
Furthermore, by making the width of the seal ring equal to the width of the manufacturing accuracy of the edge of the protective film, the edge of the protective film can always be positioned on the flat upper surface of the seal ring.

更に、保護膜の耐圧性を１．５気圧以上にしたことによって、レジスト膜のプリベーク時の温度が１５０℃であったとしても、保護膜の破壊を確実に防止することができる。
更に、保護膜をポリイミド樹脂やエポキシ樹脂、ポリベンゾオキサゾール樹脂等の有機材料で形成するようにしたことによって、前記の耐圧性を有する保護膜を容易に形成することができる。 Furthermore, by setting the pressure resistance of the protective film to 1.5 atm or higher, even if the temperature when the resist film is pre-baked is 150 ° C., the protective film can be reliably prevented from being broken.
Furthermore, by forming the protective film from an organic material such as a polyimide resin, an epoxy resin, or a polybenzoxazole resin, the protective film having the pressure resistance can be easily formed.

なお、本実施例ではシールリングや配線は能動領域の縁部の全周に環状に設けるとして説明したが、シールリングや配線の熱膨張に起因する無機保護膜等の破損を防止するためにそれぞれの一部に切欠き部や重複部を設けるようにしてもよい。   In this embodiment, the seal ring and the wiring are described as being provided in an annular shape all around the edge of the active region. However, in order to prevent the inorganic protective film and the like from being damaged due to the thermal expansion of the seal ring and the wiring, respectively. You may make it provide a notch part and an overlap part in a part of.

図３は実施例２の半導体ウェハの一部を示す上面から見た説明図、図４は実施例２の半導体ウェハの部分断面を示す説明図である。
なお、図４は図３におけるＢ−Ｂ断面線に沿った部分断面の再配線の形成後の状態を拡大して示し、図３は再配線の形成後にレジスト膜を除去した状態で示してある。
また、上記実施例１と同様の部分は、同一の符号を付してその説明を省略する。 FIG. 3 is an explanatory diagram viewed from the top showing a part of the semiconductor wafer of the second embodiment, and FIG. 4 is an explanatory diagram showing a partial cross section of the semiconductor wafer of the second embodiment.
4 is an enlarged view of the state after the formation of the rewiring of the partial cross section along the line BB in FIG. 3, and FIG. 3 is a state where the resist film is removed after the formation of the rewiring. .
Further, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

図３、図４において、２１はガイド溝であり、能動領域３とダイシング領域４とを覆う保護層５の能動領域３の外側とダイシング領域４との間をエッチング等により掘込み、半導体基板２のおもて面を露出させて形成された環状の溝であって、ダイシング領域４をダイシングソー等により切断するときにダイシング領域４を識別して切断部位を示す機能、およびダイシング領域４と能動領域３の保護層５を分離して切断時に保護層５の端部に生じるクラックの進行を食い止めてクラックが集積回路に及ぶことを防止する機能を有している。   3 and 4, reference numeral 21 denotes a guide groove, which is formed by etching or the like between the outside of the active region 3 of the protective layer 5 covering the active region 3 and the dicing region 4 and the dicing region 4. An annular groove formed by exposing the front surface of the dicing area 4. When the dicing area 4 is cut with a dicing saw or the like, the dicing area 4 is identified and the cutting portion is indicated, and the dicing area 4 and active The protective layer 5 in the region 3 is separated and has a function of preventing the crack from reaching the integrated circuit by stopping the progress of the crack generated at the end of the protective layer 5 at the time of cutting.

本実施例のガイド溝２１は、半導体装置の小型化や製造数の増大等のために、アスペクト比が０．５以上となるように形成され、上記実施例１と同様の理由でガイド溝２１を覆うように保護膜７が形成される。
このため、本実施例のダイシング領域４は、隣合う能動領域３の間の保護膜７のエッジ７ａの間として設定されている。 The guide groove 21 of this embodiment is formed to have an aspect ratio of 0.5 or more in order to reduce the size of the semiconductor device or increase the number of manufactured semiconductor devices. For the same reason as in the first embodiment, the guide groove 21 is formed. A protective film 7 is formed so as to cover.
For this reason, the dicing region 4 of this embodiment is set between the edges 7 a of the protective film 7 between the adjacent active regions 3.

また、本実施例の保護膜７は上記実施例１と同様の有機材料で形成され、１．５気圧以上の耐圧性を備えるように設定されている。
以下に、本実施例の半導体ウェハ１による半導体装置の製造方法について説明する。
能動領域３の中央部に集積回路を形成した半導体ウェハ１を準備する工程は上記実施例１と同様である。 Further, the protective film 7 of this embodiment is formed of the same organic material as that of the first embodiment, and is set to have a pressure resistance of 1.5 atm or more.
Below, the manufacturing method of the semiconductor device by the semiconductor wafer 1 of a present Example is demonstrated.
The step of preparing the semiconductor wafer 1 in which an integrated circuit is formed in the central portion of the active region 3 is the same as that in the first embodiment.

準備された半導体ウェハ１の半導体基板２のおもて面側の全面にスパッタリング法等によってアルミニウム膜を堆積し、これを電極パッド６の所定の形状にエッチングして能動領域３上に電極パッド６を形成する。
電極パッド６の形成後に、ＣＶＤ法等によって半導体基板２のおもて面側の全面に２酸化珪素からなる保護層５を形成し、エッチングにより電極パッド６の部位を除去すると共に、能動領域３とダイシング領域４との間のガイド溝２１を形成する領域の保護層５を掘り込んで半導体基板２のおもて面を露出させ、能動領域３の外側にガイド溝２１を形成する。 An aluminum film is deposited on the entire front surface side of the semiconductor substrate 2 of the prepared semiconductor wafer 1 by sputtering or the like, and this is etched into a predetermined shape of the electrode pad 6 so that the electrode pad 6 is formed on the active region 3. Form.
After the formation of the electrode pad 6, a protective layer 5 made of silicon dioxide is formed on the entire front surface side of the semiconductor substrate 2 by the CVD method or the like, the portion of the electrode pad 6 is removed by etching, and the active region 3 The protective layer 5 in the region where the guide groove 21 is formed between the semiconductor substrate 2 and the dicing region 4 is dug to expose the front surface of the semiconductor substrate 2, and the guide groove 21 is formed outside the active region 3.

実施例１と同様にして保護層５等におよび電極パッド６上に保護膜７を形成し、エッチングによりスルーホール９ａを形成すると共に、ガイド溝２１の外側に存在するダイシング領域４の保護膜７を除去して保護層５を露出させ、ガイド溝２１を覆う保護膜７を形成する。
実施例１と同様にしてシード層８を形成し、露出している保護層５および保護膜７、電極パッド６をシード層８で覆う。 In the same manner as in Example 1, a protective film 7 is formed on the protective layer 5 and the like and on the electrode pad 6, a through hole 9 a is formed by etching, and the protective film 7 in the dicing region 4 existing outside the guide groove 21. Is removed to expose the protective layer 5, and the protective film 7 covering the guide groove 21 is formed.
A seed layer 8 is formed in the same manner as in Example 1, and the exposed protective layer 5, protective film 7, and electrode pad 6 are covered with the seed layer 8.

実施例１と同様にしてレジスト膜１６を形成し、電解メッキ法により再配線９を形成する。
このとき、レジスト膜１６の形成のためのプリベークにおいて、温度が上昇したとしても保護膜７が十分な耐圧性を有しているので、保護膜７の形成時にガイド溝２１に残留した気体があったとしてもその圧力上昇により保護膜７が破壊されることはなく、レジスト膜１６に破壊が生じることもない。 A resist film 16 is formed in the same manner as in Example 1, and the rewiring 9 is formed by electrolytic plating.
At this time, in the pre-bake for forming the resist film 16, even if the temperature rises, the protective film 7 has sufficient pressure resistance, so there is a gas remaining in the guide groove 21 when the protective film 7 is formed. Even if the pressure rises, the protective film 7 is not destroyed, and the resist film 16 is not destroyed.

その後の工程は、上記実施例１と同様であるので、その説明を省略する。
このようにして本実施例の半導体ウェハ１により製造された半導体装置が形成される。
この場合に、半導体ウェハ１のダイシング領域４の検出は、ガイド溝２１の検出により行われる。
また、本実施例の半導体装置の形成は上記実施例１で説明したと同様に、封止樹脂で半導体ウェハ１のおもて面側を封止した後に個片に分割して形成するようにしてもよい。 Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.
Thus, the semiconductor device manufactured by the semiconductor wafer 1 of the present embodiment is formed.
In this case, the dicing area 4 of the semiconductor wafer 1 is detected by detecting the guide groove 21.
Further, in the same manner as described in the first embodiment, the semiconductor device of the present embodiment is formed by sealing the front surface side of the semiconductor wafer 1 with a sealing resin and then dividing it into individual pieces. May be.

以上説明したように、本実施例では、半導体ウェハの能動領域の外側に形成したガイド溝のアスペクト比が０．５以上の場合に、このガイド溝を保護膜で覆うようにしたことによって、ガイド溝により半導体ウェハを個片に分割するときに保護層に生じるクラックの進行を防止すると共に、ガイド溝を覆う保護膜によりガイド溝に残留した気体によるレジスト膜の破壊を防止することができ、予期せぬ部位に不定形でメッキが析出することがなくなり、外観不良や再配線のメッキ厚のバラツキの発生を防止することができる。   As described above, in this embodiment, when the aspect ratio of the guide groove formed outside the active region of the semiconductor wafer is 0.5 or more, the guide groove is covered with the protective film, so that the guide groove is covered. In addition to preventing the progress of cracks generated in the protective layer when the semiconductor wafer is divided into individual pieces by the grooves, the protective film covering the guide grooves can prevent the resist film from being destroyed by the gas remaining in the guide grooves. Plating is not deposited in an irregular shape at an undesired portion, and appearance defects and variations in rewiring plating thickness can be prevented.

また、保護膜をポリイミド樹脂やエポキシ樹脂、ポリベンゾオキサゾール樹脂等の有機材料で形成し、その耐圧性を１．５気圧以上にしたことによって、レジスト膜のプリベーク時の温度が１５０℃であったとしても、保護膜の破壊を確実に防止することができると共に、前記の耐圧性を有する保護膜を容易に形成することができる。
なお、上記各実施例においては、保護層で覆われた溝やガイド溝のアスペクト比が０．５以上の溝を保護膜で覆うとして説明したが、アスペクト比が０．５以上の溝を保護膜で埋めるようにしても上記各実施例と同様の効果を得ることができる。 Further, the protective film was formed of an organic material such as polyimide resin, epoxy resin, polybenzoxazole resin, etc., and the pressure resistance was 1.5 atm or higher, so that the temperature at the time of pre-baking the resist film was 150 ° C. However, it is possible to reliably prevent the protective film from being destroyed and to easily form the protective film having the pressure resistance.
In each of the above embodiments, the grooves covered with the protective layer and the grooves with the aspect ratio of 0.5 or more of the guide groove are covered with the protective film. However, the grooves with the aspect ratio of 0.5 or more are protected. Even if it is filled with a film, the same effect as in the above embodiments can be obtained.

また、上記各実施例においては、ウェハレベルチップサイズパッケージ型の半導体装置の製造に用いる半導体ウェハを例に説明したが、バンプ電極を有するＩＣチップの製造に用いる半導体ウェハの場合も同様である。   In each of the above embodiments, a semiconductor wafer used for manufacturing a wafer level chip size package type semiconductor device has been described as an example. However, the same applies to a semiconductor wafer used for manufacturing an IC chip having bump electrodes.

実施例１の半導体ウェハの部分断面を示す説明図Explanatory drawing which shows the partial cross section of the semiconductor wafer of Example 1. FIG. 実施例１の半導体ウェハの一部を示す上面から見た説明図Explanatory drawing which looked at the semiconductor wafer of Example 1 from the upper surface which shows a part 実施例２の半導体ウェハの一部を示す上面から見た説明図Explanatory drawing seen from the upper surface which shows a part of semiconductor wafer of Example 2. FIG. 実施例２の半導体ウェハの部分断面を示す説明図Explanatory drawing which shows the partial cross section of the semiconductor wafer of Example 2. FIG.

符号の説明Explanation of symbols

１ 半導体ウェハ
２ 半導体基板
３ 能動領域
３ａ 縁部
４ ダイシング領域
５ 保護層
６ 電極パッド
７ 保護膜
７ａ エッジ
８ シード層
９ 再配線
９ａ スルーホール
１１ シールリング
１２ 配線
１４ 溝
１６ レジスト膜
２１ ガイド溝
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor substrate 3 Active area | region 3a Edge part 4 Dicing area | region 5 Protective layer 6 Electrode pad 7 Protective film 7a Edge 8 Seed layer 9 Rewiring 9a Through hole 11 Seal ring 12 Wiring 14 Groove 16 Resist film 21 Guide groove

Claims (9)

集積回路を形成した複数の能動領域と、隣合う前記能動領域間に設けられたダイシング領域と、前記能動領域の縁部に形成されたシールリングと、該シールリングの内側に接近して形成された第１の配線と、前記能動領域を覆う保護層と、前記能動領域の保護層上に形成された保護膜と、該保護膜上に形成され、前記集積回路に電気的に接続する第２の配線とを備え、
前記シールリングと前記第１の配線との間の前記保護層に形成された溝のアスペクト比が０．５以上の場合に、該溝を前記保護膜で覆うことを特徴とする半導体ウェハ。 A plurality of active regions forming an integrated circuit, a dicing region provided between the adjacent active regions, a seal ring formed at an edge of the active region, and an inner side of the seal ring. A first wiring, a protective layer covering the active region, a protective film formed on the protective layer of the active region, and a second layer formed on the protective film and electrically connected to the integrated circuit With wiring,
A semiconductor wafer, wherein the groove is covered with the protective film when the aspect ratio of the groove formed in the protective layer between the seal ring and the first wiring is 0.5 or more. 請求項１において、
前記保護膜のエッジが、前記シールリングの幅方向の中央部に位置していることを特徴とする半導体ウェハ。 In claim 1,
The semiconductor wafer according to claim 1, wherein an edge of the protective film is located at a central portion in the width direction of the seal ring. 請求項２において、
前記シールリングの幅が、前記保護膜のエッジの製作精度の上下限の幅と同等であることを特徴とする半導体ウェハ。 In claim 2,
The width of the seal ring is equal to the upper and lower limits of the manufacturing accuracy of the edge of the protective film. 請求項１、請求項２または請求項３において、
前記保護膜が、１．５気圧以上の耐圧性を備えることを特徴とする半導体ウェハ。 In claim 1, claim 2 or claim 3,
A semiconductor wafer, wherein the protective film has a pressure resistance of 1.5 atm or more. 請求項１、請求項２または請求項３において、
前記保護膜が、ポリイミド樹脂とエポキシ樹脂とポリベンゾオキサゾール樹脂のいずれか一つの材料で形成されていることを特徴とする半導体ウェハ。 In claim 1, claim 2 or claim 3,
A semiconductor wafer, wherein the protective film is formed of any one of a polyimide resin, an epoxy resin, and a polybenzoxazole resin. 集積回路を形成した複数の能動領域と、隣合う前記能動領域間に設けられたダイシング領域と、前記能動領域とダイシング領域とを覆う保護層と、該保護層の前記能動領域の外側を掘込んで形成されたガイド溝と、前記能動領域の保護層上を覆う保護膜と、該保護膜上に形成され、前記集積回路に電気的に接続する第２の配線とを備え、
前記ガイド溝のアスペクト比が０．５以上の場合に、該記ガイド溝を前記保護膜で覆うことを特徴とする半導体ウェハ。 A plurality of active regions forming an integrated circuit; a dicing region provided between the adjacent active regions; a protective layer covering the active region and the dicing region; and an outside of the active region of the protective layer. A guide groove formed on the active region, a protective film covering the protective layer of the active region, and a second wiring formed on the protective film and electrically connected to the integrated circuit,
A semiconductor wafer, wherein the guide groove is covered with the protective film when the aspect ratio of the guide groove is 0.5 or more. 請求項６において、
前記保護膜が、ポリイミド樹脂とエポキシ樹脂とポリベンゾオキサゾール樹脂のいずれか一つの材料で形成され、かつ１．５気圧以上の耐圧性を備えることを特徴とする半導体ウェハ。 In claim 6,
A semiconductor wafer, wherein the protective film is formed of any one material of a polyimide resin, an epoxy resin, and a polybenzoxazole resin, and has a pressure resistance of 1.5 atm or more. 請求項１から請求項５のいずれかに記載の半導体ウェハのダイシング領域を切断して個片に形成されたことを特徴とする半導体装置。   6. A semiconductor device, wherein the dicing region of the semiconductor wafer according to claim 1 is cut to be formed into individual pieces. 請求項６または請求項７に記載の半導体ウェハのガイド溝の間のダイシング領域を切断して個片に形成されたことを特徴とする半導体装置。
8. A semiconductor device, wherein a dicing region between guide grooves of a semiconductor wafer according to claim 6 or 7 is cut and formed into individual pieces.
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