JP5503626B2 - Semiconductor wafer and semiconductor device formed thereby - Google Patents

Description

  The present invention relates to a wafer level chip size package type semiconductor device, a semiconductor wafer used for manufacturing an IC chip having bump electrodes, and a semiconductor device formed thereby.

  Conventional wafer level chip size package type semiconductor devices and semiconductor wafers used in the manufacture of IC chips having bump electrodes form an integrated circuit in a plurality of element regions set on a silicon substrate, and between adjacent element regions. When forming a pattern formation accuracy measurement mark or an element for evaluating electrical characteristics in a dicing area set to be set to a protective layer covering the element area, the pattern formation accuracy measurement mark in the dicing area is partially protected In addition to preventing damage to the resist film when rewiring is formed on the protective layer due to air or the like caught in a minute gap formed in the pattern formation accuracy measurement mark, etc., and the pattern formation accuracy measurement mark, etc. The dicing area is cut with a dicing saw by an unformed area at a predetermined interval provided between the protective layer covering the element and the protective layer covering the element area. Thereby preventing cracks occurring in the protective layer on the element region Rutoki (e.g., see Patent Document 1.).

In such a wafer level chip size package type semiconductor device and the like, the expectation for further miniaturization and increase of production of the semiconductor device is increasing with the recent miniaturization and sales expansion of electronic devices.
In order to respond to the expectation of further miniaturization and increased production of such a semiconductor device, it is possible to reduce the size of the semiconductor device by increasing the density of integrated circuits formed on the semiconductor wafer and to reduce the dicing area by using a single semiconductor wafer. It is necessary to realize an increase in the number of semiconductor devices to be manufactured.

JP-A-11-191541 (3rd page paragraph 0007-4th page paragraph 0013, FIGS. 1 and 2)

  However, in the above-described conventional technique, when the dicing area is cut with a dicing saw by a non-formed area at a predetermined interval provided between the protective layer in the dicing area and the protective layer covering the element area, the protective layer in the element area Therefore, when the dicing area is narrowed, the predetermined interval cannot be sufficiently widened, and the aspect ratio obtained by dividing the depth of the protective layer by the width of the predetermined interval is 0. If the groove becomes a groove having a depth of 5 or more, that is, a groove having a depth of more than half of the width, air entrained in the groove during the pre-baking of the resist film during subsequent rewiring is expanded and the resist is expanded. There is a problem that the film is broken, the plating is deposited in an undefined shape at an unexpected part, the appearance is deteriorated, and the plating thickness of the rewiring is varied.

In addition, in order to reduce the size of the semiconductor device, when wiring integrated with power supply wiring or the like is formed on the active region, the active region outside the wiring is used to prevent the progress of cracks in the integrated circuit generated in the protective layer. There may be a case where a seal ring is provided.
In this case, when the seal ring is brought close to the wiring in order to reduce the size, a groove is formed in the protective layer between the seal ring and the wiring, and when the aspect ratio of the groove is 0.5 or more, In the same manner as the above, there is a problem that the resist film is broken when the rewiring is formed, and plating is deposited in an unexpected shape at an unpredictable portion, resulting in an appearance defect and a variation in rewiring plating thickness.

  The present invention has been made to solve the above-described problems. Even when the aspect ratio of the groove formed in the protective layer is 0.5 or more, the resist film is broken when the rewiring is formed. An object of the present invention is to provide a means for preventing the occurrence of the above.

In order to solve the above problems, the present invention provides a semiconductor wafer in which a semiconductor substrate on which a plurality of active regions in which an integrated circuit is formed is formed , a dicing region provided between the adjacent active regions, and the active region A protective layer covering the substrate and the dicing region, a guide groove formed by digging between the active region and the dicing region of the protective layer until the semiconductor substrate is exposed, and a protective layer on the active region And a second wiring formed on the protective film and electrically connected to the integrated circuit, and the guide groove is formed when the aspect ratio of the guide groove is 0.5 or more. It is characterized by covering with a protective film.

  As a result, the present invention can prevent the resist film from being destroyed by the gas remaining in the groove by the protective film covering the groove having an aspect ratio of 0.5 or more, and the plating deposits in an unexpected shape in an undefined shape. Thus, it is possible to prevent the appearance defect and the variation in the plating thickness of the rewiring.

Explanatory drawing which shows the partial cross section of the semiconductor wafer of Example 1. FIG. Explanatory drawing which looked at the semiconductor wafer of Example 1 from the upper surface which shows a part Explanatory drawing seen from the upper surface which shows a part of semiconductor wafer of Example 2. FIG. Explanatory drawing which shows the partial cross section of the semiconductor wafer of Example 2. FIG.

  Embodiments of a semiconductor wafer according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view showing a partial cross section of the semiconductor wafer of Example 1, and FIG. 2 is an explanatory view seen from the top showing a part of the semiconductor wafer of Example 1. FIG.
1 is an enlarged view of a state after the formation of the rewiring of the partial cross section along the line AA in FIG. 2, and FIG. 2 is a state where the resist film is removed after the rewiring is formed. .
1 and 2, reference numeral 1 denotes a semiconductor wafer, which in this embodiment is a semiconductor wafer for manufacturing a wafer level chip size package type semiconductor device.

  Reference numeral 2 denotes a semiconductor substrate made of silicon, and a plurality of active regions 3 which are regions capable of forming an unillustrated integrated circuit are formed on the front surface thereof, and a wafer level chip size package type semiconductor device is manufactured. A dicing region 4 that is sometimes set as a region to be cut by a dicing saw or the like is set between the end surfaces of the end portions of the adjacent protective layers 5 between the adjacent active regions 3.

The protective layer 5 is a so-called passivation film formed of silicon nitride (Si 3 N 4), silicon dioxide (SiO 2), or the like, and the active layer 3 of the semiconductor substrate 2 is shown in FIG. It has a function of protecting and insulating an integrated circuit formed on the upper portion and the peripheral portion of the electrode pad 6 and near the central portion of the active region 3 (right side in FIG. 1).
The electrode pad 6 is a pad formed of aluminum (Al) or the like on the active region 3 and is electrically connected to a predetermined portion of the integrated circuit formed in the active region 3.

Reference numeral 7 denotes a protective film, which is formed of a relatively high strength organic material such as polyimide resin, epoxy resin, polybenzoxazole resin, etc. on the protective layer 5 as shown by shading in FIG. The layer 5 has a function of covering and smoothing defects such as irregularities such as side surfaces of holes formed by etching or the like.
Reference numeral 8 denotes a seed layer. As shown by a thick solid line in FIG. 1, nickel (Ni), titanium (Ti), copper (Cu), etc. formed on the protective film 7, the protective layer 5, the electrode pad 6, etc. A metal thin film layer formed of a single metal layer or multiple layers of the above metal material, functioning as one electrode when the rewiring 9 is plated by the electrolytic plating method, the rewiring 9 in the manufacturing process of the semiconductor wafer 1, etc. It has a function of preventing the material constituting the upper layer from diffusing to the semiconductor substrate 2 side and a function of improving the adhesion to the rewiring 9.

The rewiring 9 as the second wiring is a wiring formed of a conductive material such as copper formed in the seed layer 8 on the protective film 7 and penetrates the protective layer 5 and the protective film 7. In addition to being electrically connected to the electrode pad 6 through the through hole 9a, the post pad (not shown) formed at a predetermined position on the rewiring 9 and the electrode pad 6 are electrically connected.
Reference numeral 11 denotes a seal ring, which is an annular member formed in an annular shape with aluminum or the like on a region where the integrated circuit element around the active region 3 is not formed. The dicing region 4 is a dicing saw. It has a function of preventing the crack from reaching the integrated circuit by stopping the progress of the crack generated at the end of the protective layer 5 when it is cut by, for example.

Reference numeral 12 denotes a wiring as a first wiring, which is a wiring formed in an annular shape with aluminum or the like on the active region 3 by integrating power source wiring and the like for rationalization of circuit wiring of the integrated circuit. 3 is electrically connected to a predetermined portion of the integrated circuit formed in the circuit 3.
A groove 14 is formed in the protective layer 5 between the seal ring 11 and the wiring 12 when the seal ring 11 and the wiring 12 are covered with the protective layer 5.

  Reference numeral 16 denotes a resist film, which is a mask member formed by patterning a resist agent having a relatively high viscosity by photolithography when the rewiring 9 is formed. The resist agent is applied to the entire surface of the semiconductor wafer 1. Then, after being thermally cured by pre-baking, it has a positive type photosensitivity having a characteristic that the exposed portion is altered by exposure to light such as ultraviolet rays and is dissolved in the developer.

FIG. 1 and FIG. 2 are explanatory drawings drawn with exaggeration for the explanation of the present embodiment, so they are drawn in a state different from the actual dimensions, but the actual dimensions are very small. For example, the height of the seal ring 11 and the wiring 12 is about 2 μm, the distance between the seal ring 11 and the wiring 12 is about 2 μm, and the thickness of the protective layer 5 is less than 1 μm.
As described above, the groove 14 of this embodiment is narrowed by the formation of the protective layer 5 and the aspect ratio obtained by dividing the depth by the width is 0.5 or more. When the resist film 16 is formed, air or the like is formed in the groove 14. Since the probability of destroying the resist film 16 by entraining is increased, the protective film 7 is formed so as to cover the groove 14.

In this case, the edge 7a of the protective film 7 is positioned at the center of the seal ring 11 in the width direction, and the width of the seal ring 11 is equal to the upper and lower widths of the manufacturing accuracy of the edge 7a of the protective film 7. Good. For example, when the manufacturing accuracy of the edge 7a is ± 3 μm, the width of the seal ring 11 is set to 6 μm, which is the upper and lower width of the manufacturing accuracy.
In this manner, the width of the dicing region 4 is reduced due to the edge 7a being shifted to the dicing region 4 side beyond the seal ring 11, and the edge 7a cannot be formed with good quality over the end of the active region 3. In addition, it is possible to prevent the groove 14 from being covered by the edge 7a not reaching the seal ring 11, and to always form the edge 7a on the flat upper surface of the seal ring 11 with good quality. This is because the groove 14 can be reliably covered with the protective film 7.

Further, the protective film 7 of this embodiment is the above-described organic material, and it is desirable to set the material and film thickness of the protective film 7 so as to have a pressure resistance of 1.5 atmospheres or more.
That is, the heat treatment temperature at the time of pre-baking for curing after applying the resist agent when forming the resist film 16 is 100 to 150 ° C., and the air trapped in the groove 14 when the protective film 7 is formed by this heat treatment temperature. This is because a gas such as gas rises to 1.27 to 1.44 atm due to a change in isovolume, and a pressure resistance of 1.5 atm or more is required to withstand this.

In this embodiment, the protective film 7 is described as being formed of an organic material. However, the material for forming the protective film 7 may be an inorganic material such as silicon nitride or silicon dioxide. In short, any material may be used as long as it has a function as the protective film 7 and can form a film having a pressure resistance of 1.5 atm or more after the protective film 7 is formed.
Below, the manufacturing method of the semiconductor device by the semiconductor wafer 1 of a present Example is demonstrated.

  A semiconductor wafer 1 in which an integrated circuit (not shown) is formed at the center of a plurality of active regions 3 of a circular semiconductor substrate 2 formed by slicing columnar silicon is prepared, and the front surface side of the semiconductor substrate 2 is prepared. An aluminum film is deposited on the entire surface by sputtering or the like, and this is etched into a predetermined shape of the seal ring 11, the wiring 12 and the electrode pad 6 to form the seal ring 11, the wiring 12 and the electrode pad 6 on the active region 3. .

After the formation of the seal ring 11 and the like, the protective layer 5 made of silicon dioxide is formed by a CVD (Chemical Vapor Deposition) method or the like, and the portion of the electrode pad 6 and the protective layer 5 in the dicing region 4 are removed by etching.
At this time, a groove 14 is formed in the protective layer 5 between the seal ring 11 and the wiring 12.
A protective film 7 made of polyimide resin is formed on the protective layer 5 and the electrode pad 6 by spin coating or the like, and a portion of the electrode pad 6 is removed by etching to form a through hole 9a reaching the electrode pad 6, The protective film 7 at the site on the dicing region 4 side is removed from the center in the width direction of the seal ring 11 to expose the end of the protective layer 5, and the protective film 7 covering the groove 14 is formed.

A seed layer 8 is formed on the entire front surface of the semiconductor substrate 2 by sputtering or the like, and the exposed protective layer 5, protective film 7, and electrode pad 6 are covered with the seed layer 8.
A resist film 16 is formed on the seed layer 8 by lithography or the like to mask a region other than a portion where the rewiring 9 is formed, and copper is electroplated on the exposed seed layer 8 using the seed layer 8 as one electrode. A rewiring 9 that is deposited by the method and electrically connected to the electrode pad 6 is formed.

At this time, in the pre-bake for forming the resist film 16, the protective film 7 has sufficient pressure resistance even if the temperature rises, so there was a gas remaining in the groove 14 when the protective film 7 was formed. However, the protective film 7 is not broken by the pressure rise, and the resist film 16 is not broken.
The resist film 16 is removed using a release agent, and the exposed seed layer 8 is removed by plasma etching or the like in an oxygen gas atmosphere to expose the end portion of the protective layer 5.

Then, the dicing area 4 of the semiconductor wafer 1 is recognized by detecting the end of the protective layer 5, and the dicing area 4 is cut by a dicing saw or the like to be divided into individual pieces. A manufactured semiconductor device is formed.
Thereafter, the semiconductor device of this embodiment is sealed with a sealing resin such as an epoxy resin after a wire is bonded to a predetermined portion of the rewiring 9 by wire bonding.

  The semiconductor device of this embodiment is not formed as described above. After forming the rewiring 9 and removing the resist film 16, the identification mark indicating the cutting position in the vicinity of the dicing region 4 or the like is again formed by lithography or the like. A post is formed at a predetermined portion of the wiring 9, the seed layer 8 is removed, the front surface side of the semiconductor substrate 2 is sealed with a sealing resin, and then the dicing region of the semiconductor wafer 1 is based on the identification mark. 4 may be cut by a dicing saw or the like to form a semiconductor device divided into pieces.

  As described above, in this embodiment, this groove is protected when the aspect ratio of the groove formed in the protective layer between the seal ring and the wiring formed in the active region of the semiconductor wafer is 0.5 or more. By covering it with a film, the seal ring for preventing the progress of cracks that occur in the protective layer when the semiconductor wafer is divided into individual pieces and the wiring for rationalizing the circuit wiring of the integrated circuit are brought close to each other. The protective film covering the grooves formed between them can prevent the resist film from being damaged by the gas remaining in the grooves, and the plating can be deposited in an undefined shape at an unexpected part. Thus, it is possible to prevent appearance defects and variations in rewiring plating thickness.

In addition, since the edge of the protective film is positioned at the center in the width direction of the seal ring, the semiconductor wafer having a good quality protective film can be obtained by positioning the edge on the flat upper surface of the seal ring. And the groove can be reliably covered with a protective film.
Furthermore, by making the width of the seal ring equal to the width of the manufacturing accuracy of the edge of the protective film, the edge of the protective film can always be positioned on the flat upper surface of the seal ring.

Furthermore, by setting the pressure resistance of the protective film to 1.5 atm or higher, even if the temperature when the resist film is pre-baked is 150 ° C., the protective film can be reliably prevented from being broken.
Furthermore, by forming the protective film from an organic material such as a polyimide resin, an epoxy resin, or a polybenzoxazole resin, the protective film having the pressure resistance can be easily formed.

  In this embodiment, the seal ring and the wiring are described as being provided in an annular shape all around the edge of the active region. However, in order to prevent the inorganic protective film and the like from being damaged due to the thermal expansion of the seal ring and the wiring, respectively. You may make it provide a notch part and an overlap part in a part of.

FIG. 3 is an explanatory diagram viewed from the top showing a part of the semiconductor wafer of the second embodiment, and FIG. 4 is an explanatory diagram showing a partial cross section of the semiconductor wafer of the second embodiment.
4 is an enlarged view of the state after the formation of the rewiring of the partial cross section along the line BB in FIG. 3, and FIG. 3 is a state where the resist film is removed after the formation of the rewiring. .
Further, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  3 and 4, reference numeral 21 denotes a guide groove, which is formed by etching or the like between the outside of the active region 3 of the protective layer 5 covering the active region 3 and the dicing region 4 and the dicing region 4. An annular groove formed by exposing the front surface of the dicing area 4. When the dicing area 4 is cut by a dicing saw or the like, the dicing area 4 is identified and the cutting portion is indicated, and the dicing area 4 and active The protective layer 5 in the region 3 is separated and has a function of preventing the crack from reaching the integrated circuit by stopping the progress of the crack generated at the end of the protective layer 5 at the time of cutting.

The guide groove 21 of this embodiment is formed to have an aspect ratio of 0.5 or more in order to reduce the size of the semiconductor device or increase the number of manufactured semiconductor devices. For the same reason as in the first embodiment, the guide groove 21 is formed. A protective film 7 is formed so as to cover.
For this reason, the dicing region 4 of this embodiment is set between the edges 7 a of the protective film 7 between the adjacent active regions 3.

Further, the protective film 7 of this embodiment is formed of the same organic material as that of the first embodiment, and is set to have a pressure resistance of 1.5 atm or more.
Below, the manufacturing method of the semiconductor device by the semiconductor wafer 1 of a present Example is demonstrated.
The step of preparing the semiconductor wafer 1 in which an integrated circuit is formed in the central portion of the active region 3 is the same as that in the first embodiment.

An aluminum film is deposited on the entire front surface side of the semiconductor substrate 2 of the prepared semiconductor wafer 1 by sputtering or the like, and this is etched into a predetermined shape of the electrode pad 6 so that the electrode pad 6 is formed on the active region 3. Form.
After the formation of the electrode pad 6, a protective layer 5 made of silicon dioxide is formed on the entire front surface side of the semiconductor substrate 2 by the CVD method or the like, the portion of the electrode pad 6 is removed by etching, and the active region 3 The protective layer 5 in the region where the guide groove 21 is formed between the semiconductor substrate 2 and the dicing region 4 is dug to expose the front surface of the semiconductor substrate 2, and the guide groove 21 is formed outside the active region 3.

In the same manner as in Example 1, a protective film 7 is formed on the protective layer 5 and the like and the electrode pad 6, a through hole 9 a is formed by etching, and the protective film 7 in the dicing region 4 existing outside the guide groove 21 is formed. The protective layer 5 is exposed to be removed, and the protective film 7 covering the guide groove 21 is formed.
A seed layer 8 is formed in the same manner as in Example 1, and the exposed protective layer 5, protective film 7, and electrode pad 6 are covered with the seed layer 8.

A resist film 16 is formed in the same manner as in Example 1, and the rewiring 9 is formed by electrolytic plating.
At this time, in the pre-bake for forming the resist film 16, even if the temperature rises, the protective film 7 has sufficient pressure resistance, so there is a gas remaining in the guide groove 21 when the protective film 7 is formed. Even if the pressure rises, the protective film 7 is not broken, and the resist film 16 is not broken.

Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.
Thus, the semiconductor device manufactured by the semiconductor wafer 1 of the present embodiment is formed.
In this case, the dicing area 4 of the semiconductor wafer 1 is detected by detecting the guide groove 21.
Further, in the same manner as described in the first embodiment, the semiconductor device of the present embodiment is formed by sealing the front surface side of the semiconductor wafer 1 with a sealing resin and then dividing it into individual pieces. May be.

  As described above, in this embodiment, when the guide groove formed outside the active region of the semiconductor wafer has an aspect ratio of 0.5 or more, the guide groove is covered with the protective film. In addition to preventing the progress of cracks generated in the protective layer when the semiconductor wafer is divided into individual pieces by the groove, the protective film covering the guide groove can prevent the resist film from being destroyed by the gas remaining in the guide groove. It is possible to prevent the plating from being deposited in an indefinite shape at an undesired portion, and to prevent the appearance defect and the variation in the plating thickness of the rewiring.

Further, the protective film was formed of an organic material such as polyimide resin, epoxy resin, polybenzoxazole resin, etc., and the pressure resistance was 1.5 atm or higher, so that the temperature at the time of pre-baking the resist film was 150 ° C. However, it is possible to reliably prevent the protective film from being destroyed and to easily form the protective film having the pressure resistance.
In each of the above embodiments, the grooves covered with the protective layer and the grooves with the aspect ratio of 0.5 or more of the guide groove are covered with the protective film. However, the grooves with the aspect ratio of 0.5 or more are protected. Even if it is filled with a film, the same effects as those of the above-described embodiments can be obtained.

  In each of the above embodiments, a semiconductor wafer used for manufacturing a wafer level chip size package type semiconductor device has been described as an example. However, the same applies to a semiconductor wafer used for manufacturing an IC chip having bump electrodes.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor substrate 3 Active area | region 3a Edge part 4 Dicing area | region 5 Protective layer 6 Electrode pad 7 Protective film 7a Edge 8 Seed layer 9 Rewiring 9a Through hole 11 Seal ring 12 Wiring 14 Groove 16 Resist film 21 Guide groove

Claims (3)

A semiconductor substrate on which a plurality of active regions forming an integrated circuit are formed; a dicing region provided between the adjacent active regions; a protective layer covering the active region and the dicing region; and the active layer of the protective layer A guide groove formed by digging between the region and the dicing region until the semiconductor substrate is exposed, a protective film covering the protective layer of the active region, and formed on the protective film, the integrated circuit And a second wiring electrically connected to
A semiconductor wafer, wherein the guide groove is covered with the protective film when the aspect ratio of the guide groove is 0.5 or more. In claim 1,
A semiconductor wafer, wherein the protective film is formed of any one material of a polyimide resin, an epoxy resin, and a polybenzoxazole resin, and has a pressure resistance of 1.5 atm or more.   3. A semiconductor device, wherein a dicing region between guide grooves of a semiconductor wafer according to claim 1 or 2 is cut and formed into individual pieces.

Images