JP2013115350A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid throughput deterioration in formation of a through electrode and cost increase.SOLUTION: A semiconductor device manufacturing method comprises: forming a hole 26 for a through electrode in a silicon substrate 1; forming a groove 35 by etching insulation films 22, 23 including the hole 26; subsequently, laminating a barrier metal layer 41 and a seed layer 42 and polishing the seed layer 42 by a CMP method to leave the seed layer 42 on an inner wall of the hole 26 and in the groove 35; immersing the silicon substrate 1 in a plating tank and supplying a current in the hole 26 via the groove 35 thereby to grow a Cu film 47 only in the hole 26 and in the groove 35.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

An LSI (Large Scale Integration) may be composed of a plurality of chips (modules) such as a logic unit for arithmetic processing and a memory unit for recording data. Further, wire bonding using a thin gold wire is used for electrical connection between chips.

In recent years, miniaturization and high integration of circuit patterns have been attempted for miniaturization and high performance of LSIs. However, if the circuit pattern is miniaturized or highly integrated,
The signal propagation speed delay and the leakage current accompanied by heat generation are likely to increase. In addition, conventional LSI
In the thin wire used for the connection between the chips, the resistance value tends to be high, so that there is a possibility that a signal delay occurs with an increase in the wiring capacity. In addition, since wire bonding requires a space around the wire, it is difficult to further reduce the size of the LSI.

Therefore, in recent years, it has been attempted to improve LSI performance by increasing the speed of signal exchange between a plurality of chips constituting an LSI instead of or in addition to miniaturization of wiring. As an example, there is an inter-chip bonding structure called a through silicon via (TSV) as an alternative technique of wire bonding. The through silicon via is a wiring structure for bonding between chips formed using a via penetrating the chip,
If the through silicon vias are used for vertical chip integration, the chips can be joined with a shorter length, so that the speed of signal exchange and power loss can be reduced. Furthermore, space can be saved and the LSI can be easily downsized as compared with the case where the chip is three-dimensionally mounted using wire bonding.

Here, an example of a conventional method for manufacturing a silicon through electrode will be described. First, after element formation, an insulating film made of a silicon nitride film (hereinafter referred to as SiN) or the like is formed above the silicon substrate by CVD.
It is formed by (Chemical Vapor Deposition) method. Thereafter, a via hole is formed in the silicon substrate by anisotropic dry etching using a resist mask. Subsequently, an insulating film is formed so as to cover the inner wall of the via hole, that is, the side wall and the bottom. Further, a barrier metal layer and a seed layer are formed on the inner wall of the via hole, and a Cu film is embedded in the via hole by a plating method. In general, when a Cu film is embedded in a wiring groove or the like by an electrolytic plating method, a so-called bottom-up growth method is adopted in which Cu filling proceeds from the lower part to the upper part of the wiring groove. Accordingly, bottom-up growth is also used in the through silicon via manufacturing process, thereby preventing the occurrence of buried defects.

Thereafter, the Cu film, the barrier metal layer, and the insulating film on the surface are removed by a CMP (Chemical Mechanical Polishing) method. Furthermore, Cu in the via hole is located above the silicon substrate.
A wiring layer electrically connected to the film is formed. Subsequently, the back surface side of the silicon substrate is polished and etched to expose the Cu film in the via hole. As a result, a silicon through electrode in which a Cu film is embedded in a via hole that penetrates the silicon substrate is formed.

As another method for forming the through electrode, for example, there is a case in which the through electrode is formed on a glass epoxy substrate. In this case, an insulating layer is formed on the substrate on which the via hole is formed, and the insulating layer is patterned to form a wiring groove connected to the via hole. After depositing the electroless copper plating catalyst on the inner wall of the via hole and the entire surface of the insulating layer, the surface of the insulating layer is polished to remove the catalyst on the insulating layer, leaving the catalyst only on the inner wall of the via hole and the wiring groove. . Thereafter, an electroless plating layer is formed in the region where the catalyst is left.

JP 2010-205990 JP-A-8-307057

However, since the through silicon via has a larger volume than the wiring, a lot of time is required for bottom-up growth of the Cu film. For this reason, an excessive Cu film is deposited thickly above the silicon substrate until the via hole is filled with the Cu film. Since the Cu film deposited in this way is likely to be highly stressed, it may cause peeling of the Cu film and warping of the silicon substrate. Further, the excess Cu film is removed by polishing by the CMP method.
Since it takes time to polish the u film, the throughput of manufacturing the semiconductor device is lowered, resulting in an increase in cost.
This invention is made in view of such a situation, and it aims at avoiding the throughput and cost deterioration at the time of formation of a silicon penetration electrode.

According to one aspect of the embodiment, a step of forming a hole in the substrate, a step of forming a plurality of grooves extending from the hole to a peripheral portion of the substrate in an insulating film formed above the substrate, Forming a conductive seed layer covering the inner wall and the groove on the insulating film; removing the seed layer in the hole and other than the groove by polishing; and the groove in the peripheral portion of the substrate A step of energizing the seed layer in the hole from the seed layer formed to grow a conductive film in the hole; and a step of thinning the substrate to expose the conductive film at the bottom of the via hole; A method for manufacturing a semiconductor device is provided.

When the conductive film is formed in the hole of the through electrode, the conductive film can be grown only in the region where the seed layer is formed. Therefore, the conductive film can be formed as compared with the case where the conductive film is grown on the entire surface layer. It is possible to prevent the stress and the warpage of the substrate caused by the above.

FIG. 1A is a cross-sectional view (part 1) illustrating an example of a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1C is a cross-sectional view (part 3) illustrating an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1D is a sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1E is a cross-sectional view (part 5) illustrating the example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1F is a sectional view (No. 6) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1G is a sectional view (No. 7) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1H is a sectional view (No. 8) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1I is a sectional view (No. 9) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the invention. FIG. 1J is a sectional view (No. 10) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1K is a sectional view (No. 11) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1L is a sectional view (No. 12) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1M is a sectional view (No. 13) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1N is a cross-sectional view (No. 14) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 10 is a cross-sectional view (No. 15) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1P is a sectional view (No. 16) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1Q is a sectional view (No. 17) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1R is a cross-sectional view (No. 18) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1S is a sectional view (19) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 1T is a sectional view (No. 20) showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. 2A and 2B show an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 2A is a plan view showing the layout of the opening of the resist film, and FIG. FIG. 3A and 3B show an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 3A is a plan view showing a groove layout, and FIG. 3B is an enlarged plan view of an edge portion. FIG. 4A is a plan view showing an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention and showing the layout of the holes and grooves in the chip region. FIG. 4B shows an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is an enlarged view of a region A in FIG. 4A. FIG. 5A is a schematic diagram showing an example of an electroplating apparatus used in the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 5B shows an example of the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is an enlarged view of a region B in FIG. 5A. FIG. 6 is a plan view showing an example of the manufacturing process of the semiconductor device according to the modification of the embodiment of the present invention and showing the layout of holes and grooves in the chip region.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory, and
It is not intended to limit the invention.

First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.
First, one surface (front surface) of an n-type or p-type silicon (semiconductor) substrate 1 is, for example, ST
An element isolation insulating film 2 is formed by I (Shallow Trench Isolation) to define an active region.

Next, a dopant impurity is introduced into the active region of the silicon substrate 1 by ion implantation to form a well. When a p-type impurity such as boron is introduced as a dopant impurity,
A p-well 3 is formed on the silicon substrate 1. After forming the p-well 3, the surface of the active region is thermally oxidized to form the gate insulating film 5. The gate insulating film 5 is, for example, about 6 n of a thermal oxide film.
It is formed to a thickness of m to 7 nm. In the following, the case where the p-well 3 is formed will be described, but the same process is performed when the n-well is formed in the silicon substrate 1.

Subsequently, a polysilicon film is formed on the entire upper surface of the silicon substrate 1 by using, for example, a CVD method.
The film is formed to a thickness of 0 nm to 200 nm. Thereafter, the polysilicon film is patterned using a photolithography technique and an etching technique to form a gate electrode 6 on the silicon substrate 1.

Further, ions are implanted into the p-well 3 using the gate electrode 6 as a mask, and phosphorus is introduced into the p-well 3 next to the gate electrode 6 as an n-type impurity. Thereby, the first and second source / drain extensions 8 are formed. First and second source / drain extensions 8
Constitutes a shallow region of the extension source / drain region. Thereafter, a silicon oxide film is formed as an insulating film on the entire upper surface of the silicon substrate 1 by using, for example, a CVD method to a thickness of 100 nm.
Form a thickness of ˜200 nm. Thereafter, the insulating film is anisotropically etched. The insulating film is etched back, and an insulating sidewall 10 is formed on the side of the gate electrode 6.

Subsequently, an n-type dopant impurity such as arsenic is ion-implanted again into the silicon substrate 1 using the insulating sidewall 10 and the gate electrode 6 as a mask. As a result, the gate electrode 6
A source / drain diffusion layer 11 is formed in the p-well 3 on the side of the. The source / drain diffusion layer 11 forms a deep region of the extension source / drain.

Further, a refractory metal film such as a cobalt film is formed on the entire surface of the silicon substrate 1 by sputtering, for example. Thereafter, the refractory metal film is heated to react with silicon. As a result, a refractory metal silicide layer such as a cobalt silicide layer is formed on the silicon substrate 1 in the source / drain diffusion layer 11, and the resistance of each source / drain diffusion layer 11 is reduced.
Thereafter, the refractory metal film remaining unreacted on the element isolation insulating film 2 or the like is removed by, for example, wet etching. As a result, a source / drain electrode 12A made of, for example, cobalt silicide is formed on the source / drain diffusion layer 11. Further, a silicide layer 12B made of, for example, cobalt silicide is formed on the gate electrode 6.

Through the steps up to here, the active region of the silicon substrate 1 includes the transistor T, which is a semiconductor element including the gate insulating film 5, the gate electrode 6, the source / drain electrode 12A, and the like.
1, T2 is formed.

Further, a plasma CVD using a silicon oxide (SiO ₂ ) film as a contact via interlayer insulating film 14 on the entire upper surface of the silicon substrate 1 using TEOS (Tetra Ethyl Silane) gas.
By a method, it is formed to a thickness of about 300 nm.

Subsequently, the contact via interlayer insulating film 14 is etched to form a contact via 15. The diameter of the contact via 15 is, for example, 0.08 μm to 0.15 μm, and the source /
Until the source / drain electrode 12A of the drain diffusion layer 11 is reached.

Then, a conductive plug 16 that is electrically connected to the source / drain electrode 12A is formed using the contact via 15. Specifically, the thickness of the inner surface of the contact via 15 is 5 nm.
An adhesion film (glue film) having a two-layer structure is formed by sequentially forming a Ti film having a thickness of ˜15 nm and a TiN film having a thickness of 5 nm to 15 nm by a sputtering method or the like. Further, a W film is grown on the adhesion film by the CVD method. This film thickness is, for example, 200 nm to 300 nm on the contact via interlayer insulating film 14. As a result, the gap of the contact via 15 is filled with the W film. Thereafter, the excess W film and the adhesion film grown on the upper surface of the contact via interlayer insulating film 14 are removed by CMP. Thereby, the conductive plug 16 is formed in each contact via 15.

Next, steps required until a sectional structure shown in FIG.
An insulating film 22 is formed on the entire surface of the contact via interlayer insulating film 14. The insulating film 22 is a silicon carbide-based film, for example, by a CVD method, and the thickness thereof is, for example, 100 nm.
On the insulating film 23, for example, a 600 nm SiO ₂ film formed by plasma CVD using TEOS gas is formed. Further, a photoresist layer 24 is formed on the insulating film 23 to a thickness of, for example, 3 μm by a spin coating method, and a pattern for a through electrode is baked by using a lithography method. As a result, an opening 24A is formed in the photoresist film 24 outside the element formation region.

Next, steps required until a sectional structure shown in FIG.
By the anisotropic dry etching using the photoresist film 24 as a mask, the insulating film 22,
23, the contact via interlayer insulating film 14 and the silicon substrate 1 are etched to form a via hole 25 (first hole) for the through electrode. For example, C ₄ F ₆ , O ₂ , and Ar are used as the etching gas for the insulating film 22 and the contact via interlayer insulating film 14. For example, SF ₆ or C ₄ F ₈ is used as an etching gas for the silicon substrate 1. For example, the via hole 25 has a diameter of 1 μm to 20 μm and a depth of 50 μm or more. Here, the diameter of the via hole 25 is 5 μm.
m and the depth were 50 μm. Thereafter, the remaining photoresist film 24 is removed by ashing.

Subsequently, as shown in FIG. 1D, a sidewall protective film 31 is formed in the via hole 25 to a thickness of 200 nm by, for example, a CVD method. As a result, a hole 26 (second hole) is formed in the via hole 25 of the silicon substrate 1. Here, the sidewall protective film 31 is formed in the via hole 2.
5 may be formed simultaneously with the etching of the silicon substrate 1.

Further, as shown in FIG. 1E, for example, an i-line resist film 3 is formed on the entire surface including the hole 26.
2 is formed to a thickness of 2 μm using a spin coating method. The i-line resist film 32 is exposed and developed to form a plurality of openings 32A. The opening 32 </ b> A is formed in a line shape including the upper portion of the hole 26. The width of the opening 32A is larger than the width of the hole 26, and one opening 32A is formed.
Is formed so as to pass through a plurality of holes 26.

As shown in FIG. 2 as an example, the resist film 32 has a plurality of openings 32A, 32B, 32C.
Is formed. As shown in FIG. 2A, a plurality of openings 32 </ b> A are formed in each chip region 40. Each opening 32 </ b> A has a plurality of lines parallel to the outer periphery of the chip region 40, and is connected to an opening 32 </ b> B formed outside the chip region 40. Opening 32B
Are formed outside the chip region 40 in a lattice shape so as to surround each chip region 40. Further, the opening 32 </ b> B is connected to an opening 32 </ b> C formed at the edge portion of the silicon substrate 1. The opening 32C is formed along the edge portion and arranged in a ring shape. As shown partially in FIG. 2B, the opening 32C is a grid-like line.

Next, steps required until a sectional structure shown in FIG.
First, the sidewall protective film 31 and the insulating films 22 and 23 are dry-etched using the i-line resist film 32 to form the grooves 35. For example, a fluorine-based gas such as CF ₄ or CHF ₃ is used as the etching gas. Thereafter, the remaining i-line resist film 32 is removed using a downflow ashing device (not shown). The removal of the i-line resist film 32 is performed by SPM (Sulfuric aci
d Hydrogen Peroxide Mixture (sulfuric acid / hydrogen peroxide) may be used for dissolution removal.

Here, an example of the arrangement and shape of the grooves 35 formed above the silicon substrate 1 will be described with reference mainly to FIG. 1 (F) and FIGS. 3 to 4B.
As shown in FIG. 3A, the groove 35 includes a first groove 35A formed in the edge portion of the silicon substrate 1, a second groove 35B on the scribe line region that partitions the chip region 40, and And a third groove 35 </ b> C in the chip region 40. The third groove 35C corresponds to the groove 35 in FIG. 1F.

As shown in the enlarged view of the edge portion of the silicon substrate 1 in FIG.
The silicon substrate 1 is formed in a lattice shape in an area of 1 mm to 2 mm from the edge portion. The width of each groove 35A is 100 μm to 300 μm, and the arrangement interval is 100 μm or less. First
The shape and arrangement of the groove 35A substantially coincide with the opening 32C of the resist film 32 shown in FIG. These first grooves 35A are formed for electrical connection with contact pins of the plating apparatus.

As shown in FIG. 3A, the second groove 35B is formed in a lattice shape so as to surround the chip region 40, and has a line width of, for example, 100 μm to 300 μm and a depth of, for example, 0. .
8 μm. As shown in FIG. 3B, the second groove 35B is connected to the first groove 35A. Furthermore, as shown in FIG. 3A, the second groove 35B is connected to a plurality of third grooves 35C. Accordingly, the second groove 35B plays a role of connecting the first groove 35A and the third groove 35C. Such a second groove 35B has substantially the same shape and arrangement as the opening 24B of the resist film 24 shown in FIG. 2B, and is formed in the scribe line region.
A wide cross-sectional area is secured.

Further, as shown in FIG. 3A and the enlarged view of FIG. 4A, the third groove 35 </ b> C is formed as a line passing through the centers of the plurality of holes 26. Here, in the chip region 40, the hole 2
6 are formed in two rows along the outer periphery of the chip region 40. Accordingly, the third groove 3
5C is formed in two rows along the outer periphery of the chip region 40. Each third groove 35 </ b> C crosses or longitudinally crosses the chip region 40. As shown in FIG. 4 and FIG. 4B, which is an enlarged view of region A in FIG. 4A, each end of the third groove 35C is connected to the second groove 35B. The width of the third groove 35C is larger than the diameter of the via hole 25 and is 10 μm to 100 μm, and the depth is 0.1 mm.
8 μm. The shape and arrangement of the third groove 35C substantially match the opening 32A of the resist film 32 shown in FIG. The center of the third groove 35C and the center of the hole 26 may coincide with each other, or one may be offset with respect to the other.

Next, steps required until a sectional structure shown in FIG.
As a barrier metal layer 41, for example, a Ta compound is formed to a thickness of 200 nm using the PVD method on the entire inner surface of the hole 26 and the sidewall protective film 31 including the groove 35. A Ti-based compound may be used for the barrier metal layer 41. Further, before the formation of the barrier metal layer 41, heat treatment is performed at 150 to 350 ° C. for 1 to 5 minutes while introducing a reducing gas (H ₂ , NH _3, etc.) to remove adsorbed moisture and foreign matters on the substrate surface. Also good. Instead of heat treatment, the film surface may be physically etched using Ar ions. Thereafter, the seed layer 42 is formed on the barrier metal layer 41.
As an example, Cu is formed to a thickness of 800 nm using the PVD method.

Here, as shown in FIG. 1G (a), in the formation region of the hole 26, the entrance portion of the hole 26 of the third groove 35 is opened. In addition, as shown in FIG.
In the region where the hole 26 is not formed, the third groove 35C is almost filled with the barrier metal layer 41 and the seed layer 42, but a recess 43 is formed in a part thereof. As shown in FIG. 1G (c), in the region outside the chip region 40, the second groove 35B is almost filled with the barrier metal layer 41 and the seed layer 42, but a recess 44 is formed in the central portion. The The recess 44 is larger than the recess 43 of the third groove 35C. This is because the width of the second groove 35B is wider than that of the third groove 35C. Similarly, a recess 44 is also formed in the first groove 35A. Here, depending on the width of the groove 35 and the film thicknesses of the barrier metal layer 41 and the seed layer 42, the recesses 43 and 44 are formed.
May not be formed.

Subsequently, as shown in FIG. 1H, a resist film 45 is formed on the entire surface of the seed layer 42 by spin coating. As shown in FIG. 1H (a), the entrance of the hole 26 is capped by the entry of the resist material. For the resist film 45, for example, a novolak resin-based i-line resist is used. As shown in FIG. 1H (b), in the region where the hole 26 is not formed in the chip region 40, the entire surface of the seed layer 42 including the recess 43 is covered with a resist film 45. Similarly, as shown in FIG. 1H (c), the entire surface of the seed layer 42 including the recess 44 is covered with a resist film 45 also in the formation region of the first groove 35A and the second groove 35B.

Further, as shown in FIG. 1I, the resist film 45 except for the inside of the groove 35 and the inner wall of the hole 26.
Then, the seed layer 42 is removed by CMP to expose the barrier metal layer 41 on the outermost surface. Since the polishing process here only removes the seed layer 42 on the surface other than the holes 26 and the grooves 35, it is completed in a short time and easily.

As shown in FIG. 1I (a), since the resist film 45 remains embedded at the entrance of the hole 26, the inner surface of the hole 26 is protected from an abrasive or the like. The protective film of the hole 26 is
Instead of the resist film 45, an SOG (Spin On Glass) coating film may be used. C
A wet etching method may be used instead of the polishing by the MP method. In that case, a hydrofluoric acid aqueous solution, a sulfuric acid aqueous solution, or an ammonia aqueous solution is used as the etching solution. Thereafter, the protective film in the hole 26 is removed with an organic solvent such as NMP (N-methylpyrodoline).

Here, as shown in FIG. 1I (b), the third groove 3 in the region where the hole 26 is not formed.
Also in 5C, the seed layer 42 is exposed by the CMP method. The recess 43 formed by the barrier metal layer 41 and the seed layer 42 and the resist film 45 filling the recess 43 are removed by polishing. The cross-sectional area of the third groove 35 </ b> C has such a size that a current loss when a current is passed through the seed layer 42 can be ignored and a current sufficient for electrolytic plating of the hole 26 can be passed.

Similarly, as shown in FIG. 1I (c), the first groove 35A and the second groove 35B also have C.
The seed layer 42 is exposed by polishing by the MP method. The cross-sectional areas of the first groove 35A and the second groove 35B are larger than the cross-sectional area of the seed layer 42 of the third groove 35C. This includes a plurality of third grooves 3
This is because current is reliably supplied to each of 5.

Next, steps required until a sectional structure shown in FIG.
First, the resist film 45 filled at the entrance of the hole 26 is removed by ashing or chemical treatment. Subsequently, the Cu film 47 is filled in the hole 26 by using an electrolytic plating method.

Here, for the electrolytic plating, a plating apparatus 51 as shown in FIG. 5A and FIG. 5B is used.
5A, the plating apparatus 51 has a plating tank 52 in which a copper sulfate plating solution is stored. The copper sulfate plating solution is a mixture of 10 to 200 g / l of H ₂ SO ₄ , 20 to 50 g / l of Cu and 20 to 80 mg / l of HCl, an accelerator which is a sulfur organic compound as an additive, polyethylene 100-500 inhibitors such as nonionic surfactants
mg / l is added. The plating tank 52 circulates a copper sulfate plating solution or the like at a speed of 5 l / min to 20 l / min using a pump (not shown). The silicon substrate 1 is supported by the clamp 54 of the rotatable substrate holder 53 so that the entrance of the hole 26 faces downward.

A plurality of conductive pins 55 are attached to the clamp 54 as shown in FIG. The pin 55 is connected to the first groove 3 at the edge portion of the silicon substrate 1.
5A is brought into electrical contact. Since the first grooves 35A are formed in a lattice shape, the pins 5
5 is surely electrically connected.

At the time of plating, the substrate holder 53 is rotated at 10 rpm to 90 rpm. Substrate holder 5
As the silicon substrate 1 supported by 3 rotates in the plating solution, the copper sulfate plating solution is supplied into the hole 26 while being stirred. After inserting the silicon substrate 1 into the plating solution, the pin 5
5 a current is applied to the silicon substrate 1 through ^the current stepwise rise in the range of ^{1mA / cm 2 ~60mA / cm 2} , performing electroless plating of Cu.

Here, the current is initially first groove 3 electrically connected to pin 55 shown in FIG. 5B.
It is supplied to the seed layer 42 in 5A. The current flows from the seed layer 42 in the first groove 35A as shown in FIG.
This is supplied to the seed layer 42 embedded in the second groove 35B shown in I (c). Further, the current is supplied to the seed layer 42 in the third groove 35C in each chip region 40 shown in FIG. 1I (b) through the seed layer 42 in the second groove 35B. As shown in FIG. 1I (a), the third groove 3
The seed layer 42 in 5 C is electrically connected to the seed layer 42 on the inner wall of the hole 26.
For this reason, the current supplied from the pin 55 to the silicon substrate 1 is applied to the seed layer 42 in the groove 35.
Is supplied to each hole 26 through the. As a result, a Cu film 47 grows in the hole 26. The Cu film 47 is formed by bottom-up growth, for example. Similarly, a Cu film 47 grows above each groove 35 on the current path from the edge portion of the silicon substrate 1 to each hole 26. On the other hand, the Cu film does not grow on the surface other than the groove 35, that is, on the barrier metal layer 41. This is because the barrier metal layer 41 has a higher resistance than Cu.

When the hole 26 is filled with the Cu film 47, the silicon substrate 1 is taken out from the plating tank 52. Subsequently, the silicon substrate 1 is heat treated to crystallize and stabilize the Cu film 47 in the hole 26. The heat treatment conditions are, for example, a reducing atmosphere using H ₂ and N ₂ , or an Ar inert gas atmosphere, the substrate temperature is 350 ° C. to 450 ° C., and the treatment time is 10 minutes to 60 minutes.
Minutes. Here, when the Cu film 47 having a thickness of more than 5 μm is formed on the entire surface of the silicon substrate 1 as in the prior art, the film is peeled off by the stress caused by the thermal expansion of the Cu film 47 or the silicon substrate 1 is warped. May be born. On the other hand, in this embodiment, the Cu film 47 is formed only in the groove 35 and the hole 26 on the silicon substrate 1. For this reason, the stress of the outermost Cu film 47 is suppressed, and film peeling and warping do not occur.

Thereafter, as shown in FIG. 1K, the barrier metal layer 41, the sidewall protective film 31, and the insulating film 23 are removed by polishing using a CMP method. At this time, groove 3 used for conduction during plating
5 and the Cu film grown on the trench 35 are also removed at the same time. Since the Cu film on the groove 35 is smaller than the entire area of the silicon substrate 1, it can be easily removed by polishing in a short time.

Next, steps required until a sectional structure shown in FIG.
First, a protective film 60 is formed for preventing oxidation of the Cu film 47 on the surface of the hole 26 and preventing diffusion of the Cu film 47. The protective film 60 is made of, for example, SiC or Si formed by the CVD method.
N. The thickness of the protective film 60 is, for example, 30 nm to 50 nm.

Next, a wiring layer connected to the hole 26 and the contact via 15 is formed above the silicon substrate 1. An interlayer insulating film 61 is formed so as to cover the protective film 60. The interlayer insulating film 61 is
For example, SIOC formed by plasma CVD is used. The thickness of the interlayer insulating film 61 is set to 120 nm to 250 nm.

Subsequently, the interlayer insulating film 61 is dry etched using a resist film or a hard mask to form wiring grooves 68A and 68B. In the wiring grooves 58A and 58B, a barrier metal layer 69 and a seed layer (not shown) are sequentially formed by sputtering. Further, the Cu film 71 is embedded in the wiring grooves 68A and 68B by plating. Excessive Cu film 71 and barrier metal layer 69 are removed by CMP. As a result, the wiring 7
A first wiring layer 73 in which 2A and 72B are embedded is formed. The wiring 72A is connected to the hole 26
It is electrically connected to the inner Cu film 47. The wiring 72B is electrically connected to the transistors T1 and T2 through the conductive plug 16. Thereafter, the same processing is repeated to form the required number of multilayer wiring layers 80.

Next, with reference to FIG. 1M, processing on the back surface (the other surface) side of the silicon substrate 1 will be described.
First, the surface of the multilayer wiring layer 80 formed on the silicon substrate 1 is covered with a protective film 81 such as a polyimide film. Further, the protective film 81 is bonded to the support substrate (glass carrier) 83 using the adhesive 82. As a result, the silicon substrate 1 is fixed to the support substrate 83 with the surface facing down. Thereafter, the silicon substrate 1 is placed on the C in the hole 26 from the back side.
The film is ground and thinned until just before the u film 47 is exposed.

Next, steps required until a sectional structure shown in FIG.
For example, the back surface of the silicon substrate 1 is etched by anisotropic dry etching to expose the head (Cu post) 47A of the Cu film 47 formed at the bottom of the hole 26. C
The exposed length of the u post 47A is, for example, 5 μm to 10 μm. For example, SF ₆ or C ₄ F ₈ is used as the etching gas at this time.

Next, in order to protect the back surface of the silicon substrate 1, an insulating film 84 is formed by, for example, a CVD method. For the insulating film 84, for example, a porous silica film made of SiCOH or the like is used, and the thickness thereof is set to 10 μm to 15 μm. Here, the insulating film 84 is desirably the same film as the sidewall protective film 31 filled in the hole 26.

Further, steps required until a sectional structure shown in FIG.
The insulating film 84 is etched by anisotropic etch back. Etching is performed on the insulating film 8
4 is preferably performed under the condition that the etching selectivity of the Cu film 47 to 4 is high. By adjusting the etching time, only the head (vertex) of the Cu post 47A is exposed to Cu, or the Cu post 4
7A head (vertex) and Cu on the side wall can be exposed. The side wall protective film 31 on the side portion of the Cu post 47A may remain. Thereby, the through electrode 85 is formed.

Next, a process until a semiconductor chip is diced and mounted will be described.
First, steps required until a sectional structure shown in FIG. A resist film 90 is formed on the back surface of the silicon substrate 1 by coating. Further, the resist film 90 is exposed and developed to form an opening 90 </ b> A on each of the plurality of through electrodes 85. Subsequently, a conductive material such as Ni / Au, for example, is grown in the opening 90A by electrolytic plating, and the bump 9
1 is formed. After the bump 91 is formed, the resist film 90 is removed by ashing or the like.

Thereafter, as shown in FIG. 1Q, the silicon substrate 1 is turned over and attached to the dicing tape 92. Further, as shown in FIG. 1R, the adhesive 82 is peeled off from the silicon substrate 1 and the support substrate 83 is removed. Further, the protective film 81 is removed from the silicon substrate 1. Thereafter, as shown in FIG. 1S, a plurality of semiconductor devices 95 are formed by dicing the silicon substrate 1 into pieces. The semiconductor device 95 includes a semiconductor element, a multilayer wiring layer 80, and a plurality of through electrodes 85.
It is comprised including.

Here, the semiconductor device 95 can be three-dimensionally mounted using the through electrode 85 and the bump 91. For example, as illustrated in FIG. 1T, the semiconductor device 95 is mounted on another semiconductor device 101. The other semiconductor device 101 includes a wiring layer 102 on which a semiconductor circuit is formed, and a through electrode 85A electrically connected to the wiring layer 102. The through electrode 85A has a bump 91.
A is formed. The formation method of the through electrode 85 </ b> A and the bump 91 </ b> A is the same as that of the through electrode 85 and the bump 91 of the semiconductor device 95.

The semiconductor device 95 is removed from the dicing tape 92 by picking up using a mounter (not shown). Further, the bump 91 is positioned and placed so as to be disposed on the through electrode 85 </ b> A of the other semiconductor device 101. Thereafter, for example, the bump 91 is melted by a reflow process, and the through electrode 85A of the other semiconductor device 101 and the semiconductor device 95 are melted.
These through electrodes 85 are joined. Thereby, the plurality of semiconductor devices 95 and 101 are connected to the through electrode 8.
The electronic component 111 electrically connected using 5,85A is formed.

As described above, in this embodiment, the seed layer 42 partially formed above the silicon substrate 1 is used and the Cu film 47 is plated and grown in the hole 26. It becomes possible to grow the Cu film 47 only in a part of the region including it. This prevents the Cu film 47 from growing thick over the entire outermost surface, and the Cu film 47
It is possible to prevent peeling and warping of the silicon substrate 1 due to stress generated when the film is formed thick. Further, since the amount of the extra Cu film 47 is reduced, the polishing time by the CMP method can be shortened, and the manufacturing efficiency of the semiconductor device 95 is improved. Furthermore, the current required for the growth of the Cu film 47 can be reduced.

Since the insulating films 23 and 31 are formed by etching to form the groove 35 and then the seed layer 42 is formed and the seed layer 42 other than the groove 35 is removed, the seed layer 42 is easily formed only on a part thereof. it can. In addition, a plurality of line-shaped grooves 35 are formed from the edge portion of the silicon substrate 1.
Since it has been formed to reach each hole 26 in each chip region 40, it is easy to supply a current from the outside during electrolytic plating. Since the first grooves 35A at the edge portion of the silicon substrate 1 are formed in a lattice shape, the current supply pins 55 of the electrolytic plating apparatus 51 and the seed layer 42 can be reliably connected. 1
Since the one groove 35 is connected to a plurality of other grooves 35, a current supply path can be reliably ensured, and the Cu film 47 can be reliably embedded in the hole 26. First and second grooves 35A, 35B
Since the cross-sectional area is larger than that of the third groove 35C, current supply into the hole 26 via the seed layer 42 can be stably realized.

Here, as a modification of the embodiment, another example of the layout is shown in FIG.
In the chip region 40 on the silicon substrate 1, holes 26 are arranged in parallel in two rows on both sides and the center of the chip region 40. Accordingly, two third grooves 35 </ b> C are formed on each side and center of the chip region 40. Each third groove 35 </ b> C is connected to a second groove 35 </ b> B formed around the chip region 40. The lower limit values of the sizes of the grooves 35C are such that the cross-sectional area is sufficient to ignore the current loss during the plating process. Further, the upper limit value of the size of the groove 35C is such a value that current efficiency is improved as compared with the case where the entire surface is plated.

All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, and such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of the above embodiment will be added below.
(Supplementary Note 1) A step of forming a hole in the substrate, a step of forming a plurality of grooves from the hole to the peripheral portion of the substrate in an insulating film formed above the substrate, an inner wall of the hole and the groove Forming a conductive seed layer to cover the insulating film; removing the seed layer other than in the hole and in the groove by polishing; and forming the seed in the groove in a peripheral portion of the substrate Energizing the seed layer in the hole from a layer to grow a conductive film in the hole, and thinning the substrate to expose the conductive film at the bottom of the via hole. A method of manufacturing a semiconductor device.
(Additional remark 2) The manufacturing method of the semiconductor device of Additional remark 1 characterized by forming the said groove | channel wider than the diameter of the said hole in the chip | tip area | region in which a semiconductor circuit is formed.
(Additional remark 3) The manufacturing method of the semiconductor device according to Additional remark 1 or Additional remark 2 characterized by forming the said groove | channel on the edge part of the said board | substrate in a grid | lattice form over the perimeter of the said edge.
(Additional remark 4) The manufacturing method of the semiconductor device of Additional remark 2 or Additional remark 3 which forms the said groove | channel in the scribe line area | region on the said board | substrate.
(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 2 to 4, wherein a cross-sectional area of the groove in the chip region is equal to or less than a cross-sectional area of the groove outside the chip region. Manufacturing method.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to claim 1, wherein one groove is connected to the other groove in at least two places.

1 Silicon substrate 23 Insulating film 26 Hole 35 Groove 35A First groove 35B Second groove 35C Third groove 40 Chip region 42 Seed layer 47 Cu film (conductive film)
95 Semiconductor device

Claims (5)

Forming a hole in the substrate;
Forming a plurality of grooves from the hole to the peripheral portion of the substrate in the insulating film formed above the substrate;
Forming a conductive seed layer covering the inner wall of the hole and the groove on the insulating film;
Removing the seed layer other than in the hole and in the groove;
Energizing the seed layer in the hole from the seed layer formed in the groove in the peripheral portion of the substrate, and forming a conductive film in the hole;
Thinning the substrate to expose the conductive film at the bottom of the hole;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed wider than the diameter of the hole in a chip region where a semiconductor circuit is formed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed in a lattice shape over the entire periphery of the edge at an edge portion of the substrate. The method for manufacturing a semiconductor device according to claim 2, wherein the groove is formed in a scribe line region on the substrate. The one groove is connected to the other groove in at least two places.
The method for manufacturing a semiconductor device according to claim 1.

Images