JP2001056570A - Production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of cavities in dents and the resultant formation of resist holes when resists of large film thicknesses are formed in the level difference portions of the dents, etc., on a semiconductor integrated circuit device. SOLUTION: The narrow dents are formed on the surface of a barrier metal second layer 8 for forming gold bumps 11 between wiring parts 5a of MOS transistors in this process for production. While a wafer 1 is heated, the low- temperature resist 9 is first applied thereon and thereafter, the high-viscosity resist 10a is applied thereon, by which the resist materials are packed into the dents as well. Coverage is thus improved and the generation of the cavities and the resist holes after baking are eliminated. The resist 10 of the large film thickness for forming the selective plating of the gold bumps may be assured by the high-viscosity resist 10a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for applying a thick resist on a semiconductor substrate.

[0002]

2. Description of the Related Art In a part of a semiconductor integrated circuit device (hereinafter, referred to as a semiconductor device), a bump made of gold or the like is formed on an electrode pad made of an aluminum alloy or the like, and a lead for extracting a signal to the outside is joined to the bump. There is something.
At present, bumps of gold or the like are generally grown by plating. At this time, the periphery of the electrode pad is masked with a thick resist.

First, a conventional bump forming process will be described. FIG. 2 is a process sectional view showing a conventional bump forming process using a resist having a large thickness, and is an example of a semiconductor device including a MOS transistor. FIG. 2A shows a stage in which the main diffusion process of the semiconductor device has been completed, where 1 is a semiconductor wafer, 2 is an interlayer insulating film, 3 is a thin gate oxide film, and 4a is a gate electrode made of a polysilicon film or the like. , 4
b is a source, 4c is a drain, 5a is an alloy wiring portion mainly composed of aluminum or the like, 5b is an electrode pad on which a gold bump is formed, and 6 is a surface protective film.

As shown in FIG. 2B, a barrier metal first layer 7 and a barrier metal second layer 8 are formed on the surface of the semiconductor device. Usually, T
The barrier metal second layer 8, such as i or TiW, is made of Pd, Au, or the like, and is formed by sputtering or EB vapor deposition. Thereafter, as shown in FIG. 2C, a resist 10 having a large thickness is formed.

In order to form a thick resist 10,
Using the apparatus shown in FIG.
Apply to the surface of layer 8. FIG. 4 is an explanatory view of applying the resist using a spin coater. Reference numeral 14c denotes a resist nozzle, 15 denotes a spin table, and 16 denotes a hot plate. As a coating method, the semiconductor wafer 1 is fixed on the spin table 15, and a high-viscosity resist is dropped from the resist nozzle 14c. After that, the spin table 15 is rotated at a high speed to spread the high-viscosity resist on the semiconductor wafer 1. Subsequently, in order to dry and solidify the high-viscosity resist, the semiconductor wafer 1 is transferred onto a hot plate 16 and
Bake.

Thereafter, although not shown in FIG. 2, an opening is provided in the electrode pad 5b portion of the thick resist 10, and a gold bump is selectively grown on the electrode pad 5b by plating.

[0007]

However, the surface of the semiconductor device as shown in FIG. 2 has considerable irregularities because a large number of semiconductor elements are formed. In addition, for example, in FIG. 2C, the interval itself between the wiring portions 5a connected to the diffusion layers of the source 4b and the drain 4c has a certain width. As the layer 7 and the barrier metal second layer 8 are successively deposited, the distance decreases, and particularly the surface of the barrier metal second layer 8 has a very narrow depression. It has been found that when a high-viscosity resist is applied to such a surface, the occurrence of a defective portion 12 of the resist coverage, that is, a portion that is not coated with the resist and becomes a cavity increases.

When baking is performed at several tens to one hundred and several tens of degrees in order to cure the resist in a state where the resist coverage defective portion 12 is formed, as shown in FIG. 12 changes to a resist hole 13. Thereafter, when plating is performed to form a gold bump, when the barrier metal second layer 8 in this portion has an extremely small area, but is exposed, an abnormality occurs in which gold plating is performed. . This gold plating is undesirable because it causes a reduction in manufacturing yield and reliability for semiconductor devices. For example, the gold plating is not removed and may eventually cause an electrical short circuit.

[0009] The above-mentioned resist coverage defective portion 12
Is used because a high-viscosity resist is used to form a resist 10 having a large thickness, so that the narrow holes are not filled, and the resist holes 13 are filled with a solvent contained in the high-viscosity resist during baking. It is conceivable that it is generated by being expelled into the cavity of the defective portion 12 and rapidly expanding, or by bubbles of the defective portion 12 of the resist coverage reaching the surface.

The present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device in which a resist coverage of a narrow step portion or the like is improved and a thick resist film is formed without forming a resist hole or the like. With the goal.

[0011]

In order to achieve the above object, a manufacturing method of the present invention basically comprises a step of applying a first photosensitive resin on a semiconductor substrate, and a step of applying the first photosensitive resin to the semiconductor substrate. A step of applying a second photosensitive resin on the film, and a step of baking at least the applied first photosensitive resin, wherein the first photosensitive resin is the second photosensitive resin. Characterized by a lower viscosity than

More specifically, a step of applying a first photosensitive resin on a semiconductor substrate on which a semiconductor element and an electrode pad are formed, and a step of applying a second photosensitive resin on the film of the first photosensitive resin. Applying a resin; baking at least the applied first photosensitive resin; forming openings in the first and second photosensitive resin portions on the electrode pads; Selectively forming a conductor in a portion, wherein the first photosensitive resin has a lower viscosity than the second photosensitive resin.

Further, the application of the first photosensitive resin can be performed while heating the semiconductor substrate, and the formation of the conductor can be performed by a plating method.

According to the above method, by applying a low-viscosity photosensitive resin (resist or the like) on a semiconductor substrate, it is possible to prevent the formation of a resist cavity in the surface irregularities, and to form a resist hole by later baking. Will not be done. In addition, by applying the resist while heating the semiconductor substrate, the effect of suppressing the generation of cavities is further improved.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a process sectional view showing a process of forming a gold bump on a MOS type semiconductor device by employing the method of applying a high-thickness resist of the present invention. FIG.
(A), 1 is a semiconductor wafer, 2 is an interlayer insulating film,
3 is a thin gate oxide film, 4a is a gate electrode made of polysilicon or the like, 4b is a source, 4c is a drain, 5a
Is a wiring portion connected to the diffusion layers of the source 4b and the drain 4c and made of an aluminum alloy film or the like, 5b is an electrode pad on which a gold bump is formed, and 6 is a surface protection film such as a silicon nitride film. FIG. 1A shows a stage where the formation of the MOS transistor is completed.

Further, the steps up to the formation of the first barrier metal layer 7 and the second barrier metal layer 8 in FIG. Here, very narrow depressions are formed on the surface of the barrier metal second layer 8 corresponding to between the wiring portions 5a.

After forming these barrier metals, FIG.
As shown in (1), a thick resist 10 is formed. In this case, first, a low-viscosity resist 9 is applied on the second barrier metal layer 8, and then a high-viscosity resist 10a is applied. Specifically, a spin coater shown in FIG. 3 is used for applying the resist having the two-layer structure.

The resist coating operation will be described. First, the low-viscosity resist 9 is dropped on the semiconductor wafer 1 from the low-viscosity resist coating nozzle 14a. Usually, there are two types of resists, a positive type and a negative type. Here, the positive type resist will be described. The low-viscosity resist 9 has a viscosity of, for example, about 100 to 200 mPa · s. Thereafter, the spin table 15 is rotated to spread the low-viscosity resist 9 evenly on the semiconductor wafer 1. The thickness is in the range of about 1.0 to 2.0 μm,
It is almost the same as the film thickness used in a normal semiconductor device manufacturing process. Further, the semiconductor wafer 1 is heated at a temperature of 8 ° C.
Heat at 0-120 ° C.

Thereafter, the high-viscosity resist coating nozzle 14
b, a high-viscosity resist 10 a is dropped on the semiconductor wafer 1. The high-viscosity resist 10a has a viscosity adjusted to a predetermined resist film thickness. For example, if the resist film thickness is 20
If necessary, a material having a viscosity of about 900 to 1000 mPa · s can be used. Then, spin table 1
5 to rotate the high-viscosity resist 10a into the semiconductor wafer 1
Spread evenly on top. Also at this time, the semiconductor wafer 1 is heated by the spin table hot plate 17 in a temperature range of about 80 to 120 ° C.

After forming a thick resist 10 having a two-layer structure in this manner, as shown in FIG. 1D, an opening pattern is formed on the electrode pad 5b. Post-bake may be performed again after the opening pattern is formed. Next, as shown in FIG. 1D, a gold bump 11 is selectively formed by plating or the like using the resists 9 and 10 as masks.

According to the present embodiment as described above, the low-viscosity resist 9 is applied to the surface of the semiconductor wafer 1 while heating the semiconductor wafer 1. However, since the resist 9 has a low viscosity, the resist 9 has a low viscosity. Even if a narrow depression exists, it flows sufficiently in that part, and the depression can be filled. Then, a thick resist capable of being plated with gold can be secured by a high-viscosity resist 10 a applied on the low-viscosity resist 9. Further, applying the resist while heating the semiconductor wafer 1 promotes the volatilization of the solvent in the resist even during the application, and enables the formation of a resist film in which the content of the solvent component is smaller than that of the resist applied at room temperature. I do. This is true not only for the low-viscosity resist 9 but also for the application of the high-viscosity resist 10a. The low-viscosity resist 9 fills the narrow dents on the surface of the element on the semiconductor device.
Even if baking or post-baking is performed after application of a, no resist hole is formed in the recessed portion, and application at room temperature is possible. However, when the solvent content in the resist immediately after application is large, the solvent is vaporized even if the resist is filled in a narrow recess, and in some cases it may expand and form a resist hole, If the content of the solvent is reduced by heat coating, the generation of such resist holes can be more efficiently suppressed.

In this manner, the resist coverage of the narrow step portion is improved by the low-viscosity resist 9, so that the conventional resist cavities and resist holes are not generated, and extra gold is formed on the surface of the semiconductor device by plating. No more.

[0023]

As described above, according to the present invention,
By first applying a low-viscosity resist to the uneven surface of the semiconductor device, and then applying a high-viscosity resist,
This makes it possible to improve the resist coverage of a narrow step, and to form a gold bump without lowering the yield and reliability of the semiconductor device. In addition, by applying a low-viscosity resist while heating the wafer, the effect of preventing the generation of holes due to solvent expansion of the resist is further increased.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a method of applying a thick film resist according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of applying a thick resist film according to the prior art.

FIG. 3 is an explanatory view of a resist coating step in the embodiment of the present invention.

FIG. 4 is an explanatory view of a resist coating step in a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Interlayer insulating film 3 Gate oxide film 4a Gate electrode 4b Source 4c Drain 5a Wiring part 5b Electrode pad 6 Surface protective film 7 Barrier metal first layer 8 Barrier metal second layer 9 Low viscosity resist 10 Thick resist 10a High-viscosity resist 11 Bump 12 Resist-coverage defective part 13 Resist hole 14a Low-viscosity resist application nozzle 14b High-viscosity resist application nozzle 15 Spin table 16 Hot plate 17 Hot plate for spin table

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H096 AA25 CA05 CA12 DA01 GA60 HA27 KA30 4M104 BB14 CC01 DD52 DD62 FF16 HH13 5F033 HH07 HH08 HH13 HH18 HH23 JJ13 JJ18 JJ23 KK01 KK08 MM08 MM13 PP15 V19PP27

Claims (4)

[Claims] A step of applying a first photosensitive resin on a semiconductor substrate; a step of applying a second photosensitive resin on a film of the first photosensitive resin; Baking the first photosensitive resin, wherein the first photosensitive resin has a lower viscosity than the second photosensitive resin. 2. A step of applying a first photosensitive resin on a semiconductor substrate on which a semiconductor element and an electrode pad are formed, and applying a second photosensitive resin on the film of the first photosensitive resin. A step of baking at least the applied first photosensitive resin; a step of forming openings in the first and second photosensitive resin portions on the electrode pads; Forming a conductive material in the first photosensitive resin, wherein the first photosensitive resin has a lower viscosity than the second photosensitive resin. 3. The method according to claim 1, wherein the application of the first photosensitive resin is performed while heating the semiconductor substrate. 4. The method according to claim 2, wherein the conductor is formed by a plating method.